| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 |
| // RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -O3 \ |
| // RUN: -o - %s | FileCheck --check-prefix=AMDGCNSPIRV %s |
| // RUN: %clang_cc1 -triple amdgpu9.06-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -O3 \ |
| // RUN: -o - %s | FileCheck --check-prefix=AMDGPU %s |
| |
| #define __global__ __attribute__((global)) |
| #define __device__ __attribute__((device)) |
| |
| union Transparent { unsigned x; }; |
| using V1 = unsigned __attribute__((ext_vector_type(1))); |
| using V2 = unsigned __attribute__((ext_vector_type(2))); |
| using V3 = unsigned __attribute__((ext_vector_type(3))); |
| using V4 = unsigned __attribute__((ext_vector_type(4))); |
| struct SingleElement { unsigned x; }; |
| struct ByRef { unsigned x[17]; }; |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k0s( |
| // AMDGCNSPIRV-SAME: i16 noundef [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0:[0-9]+]] !max_work_group_size [[META8:![0-9]+]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k0s( |
| // AMDGPU-SAME: i16 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k0(short) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k1j( |
| // AMDGCNSPIRV-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] !max_work_group_size [[META8]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k1j( |
| // AMDGPU-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k1(unsigned) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k2d( |
| // AMDGCNSPIRV-SAME: double noundef [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] !max_work_group_size [[META8]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k2d( |
| // AMDGPU-SAME: double noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k2(double) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k311Transparent( |
| // AMDGCNSPIRV-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] !max_work_group_size [[META8]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k311Transparent( |
| // AMDGPU-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr #[[ATTR0]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k3(Transparent) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k413SingleElement( |
| // AMDGCNSPIRV-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] !max_work_group_size [[META8]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k413SingleElement( |
| // AMDGPU-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr #[[ATTR0]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k4(SingleElement) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k55ByRef( |
| // AMDGCNSPIRV-SAME: ptr addrspace(2) nofree noundef readnone byref([[STRUCT_BYREF:%.*]]) align 4 captures(none) [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] !max_work_group_size [[META8]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k55ByRef( |
| // AMDGPU-SAME: ptr addrspace(4) nofree noundef readnone byref([[STRUCT_BYREF:%.*]]) align 4 captures(none) [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k5(ByRef) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k6Dv1_jDv2_jDv3_jDv4_j( |
| // AMDGCNSPIRV-SAME: <1 x i32> noundef [[TMP0:%.*]], <2 x i32> noundef [[TMP1:%.*]], <3 x i32> noundef [[TMP2:%.*]], <4 x i32> noundef [[TMP3:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] !max_work_group_size [[META8]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k6Dv1_jDv2_jDv3_jDv4_j( |
| // AMDGPU-SAME: <1 x i32> noundef [[TMP0:%.*]], <2 x i32> noundef [[TMP1:%.*]], <3 x i32> noundef [[TMP2:%.*]], <4 x i32> noundef [[TMP3:%.*]]) local_unnamed_addr #[[ATTR0]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k6(V1, V2, V3, V4) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_kernel void @_Z2k7Pj( |
| // AMDGCNSPIRV-SAME: ptr addrspace(1) nofree noundef readnone captures(none) [[DOTCOERCE:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] !max_work_group_size [[META8]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local amdgpu_kernel void @_Z2k7Pj( |
| // AMDGPU-SAME: ptr addrspace(1) nofree noundef readnone captures(none) [[DOTCOERCE:%.*]]) local_unnamed_addr #[[ATTR0]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __global__ void k7(unsigned*) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z2f0s( |
| // AMDGCNSPIRV-SAME: i16 noundef signext [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z2f0s( |
| // AMDGPU-SAME: i16 noundef signext [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f0(short) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z2f1j( |
| // AMDGCNSPIRV-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z2f1j( |
| // AMDGPU-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f1(unsigned) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z2f2d( |
| // AMDGCNSPIRV-SAME: double noundef [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z2f2d( |
| // AMDGPU-SAME: double noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f2(double) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z2f311Transparent( |
| // AMDGCNSPIRV-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z2f311Transparent( |
| // AMDGPU-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f3(Transparent) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z2f413SingleElement( |
| // AMDGCNSPIRV-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z2f413SingleElement( |
| // AMDGPU-SAME: i32 [[DOTCOERCE:%.*]]) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f4(SingleElement) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z2f55ByRef( |
| // AMDGCNSPIRV-SAME: ptr nofree noundef readnone byref([[STRUCT_BYREF:%.*]]) align 4 captures(none) [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z2f55ByRef( |
| // AMDGPU-SAME: ptr addrspace(5) nofree noundef readnone byref([[STRUCT_BYREF:%.*]]) align 4 captures(none) [[TMP0:%.*]]) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f5(ByRef) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z2f6Dv1_jDv2_jDv3_jDv4_j( |
| // AMDGCNSPIRV-SAME: <1 x i32> noundef [[TMP0:%.*]], <2 x i32> noundef [[TMP1:%.*]], <3 x i32> noundef [[TMP2:%.*]], <4 x i32> noundef [[TMP3:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z2f6Dv1_jDv2_jDv3_jDv4_j( |
| // AMDGPU-SAME: <1 x i32> noundef [[TMP0:%.*]], <2 x i32> noundef [[TMP1:%.*]], <3 x i32> noundef [[TMP2:%.*]], <4 x i32> noundef [[TMP3:%.*]]) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f6(V1, V2, V3, V4) { } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef signext i16 @_Z2f7v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret i16 0 |
| // |
| // AMDGPU-LABEL: define dso_local noundef signext i16 @_Z2f7v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret i16 0 |
| // |
| __device__ short f7() { return 0; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef i32 @_Z2f8v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret i32 0 |
| // |
| // AMDGPU-LABEL: define dso_local noundef i32 @_Z2f8v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret i32 0 |
| // |
| __device__ unsigned f8() { return 0; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef double @_Z2f9v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret double 0.000000e+00 |
| // |
| // AMDGPU-LABEL: define dso_local noundef double @_Z2f9v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret double 0.000000e+00 |
| // |
| __device__ double f9() { return 0.; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef i32 @_Z3f10v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret i32 0 |
| // |
| // AMDGPU-LABEL: define dso_local noundef i32 @_Z3f10v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret i32 0 |
| // |
| __device__ Transparent f10() { return {}; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef i32 @_Z3f11v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret i32 0 |
| // |
| // AMDGPU-LABEL: define dso_local noundef i32 @_Z3f11v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret i32 0 |
| // |
| __device__ SingleElement f11() { return {}; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z3f12v( |
| // AMDGCNSPIRV-SAME: ptr dead_on_unwind noalias nofree writable writeonly sret([[STRUCT_BYREF:%.*]]) align 4 captures(none) initializes((0, 68)) [[AGG_RESULT:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR1:[0-9]+]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: tail call addrspace(4) void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(68) [[AGG_RESULT]], i8 0, i64 68, i1 false) |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z3f12v( |
| // AMDGPU-SAME: ptr addrspace(5) dead_on_unwind noalias nofree writable writeonly sret([[STRUCT_BYREF:%.*]]) align 4 captures(none) initializes((0, 68)) [[AGG_RESULT:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: tail call void @llvm.memset.p5.i64(ptr addrspace(5) noundef align 4 dereferenceable(68) [[AGG_RESULT]], i8 0, i64 68, i1 false) |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ ByRef f12() { return {}; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef <1 x i32> @_Z3f13v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret <1 x i32> zeroinitializer |
| // |
| // AMDGPU-LABEL: define dso_local noundef <1 x i32> @_Z3f13v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret <1 x i32> zeroinitializer |
| // |
| __device__ V1 f13() { return {}; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef <2 x i32> @_Z3f14v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret <2 x i32> zeroinitializer |
| // |
| // AMDGPU-LABEL: define dso_local noundef <2 x i32> @_Z3f14v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret <2 x i32> zeroinitializer |
| // |
| __device__ V2 f14() { return {}; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef <3 x i32> @_Z3f15v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret <3 x i32> zeroinitializer |
| // |
| // AMDGPU-LABEL: define dso_local noundef <3 x i32> @_Z3f15v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret <3 x i32> zeroinitializer |
| // |
| __device__ V3 f15() { return {}; } |
| |
| // AMDGCNSPIRV-LABEL: define spir_func noundef <4 x i32> @_Z3f16v( |
| // AMDGCNSPIRV-SAME: ) local_unnamed_addr addrspace(4) #[[ATTR0]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: ret <4 x i32> zeroinitializer |
| // |
| // AMDGPU-LABEL: define dso_local noundef <4 x i32> @_Z3f16v( |
| // AMDGPU-SAME: ) local_unnamed_addr #[[ATTR1]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: ret <4 x i32> zeroinitializer |
| // |
| __device__ V4 f16() { return {}; } |
| |
| extern "C" __device__ void variadic(int, ...); |
| // AMDGCNSPIRV-LABEL: define spir_func void @_Z3f175ByRef( |
| // AMDGCNSPIRV-SAME: ptr nofree noundef readonly byref([[STRUCT_BYREF:%.*]]) align 4 captures(none) [[TMP0:%.*]]) local_unnamed_addr addrspace(4) #[[ATTR3:[0-9]+]] { |
| // AMDGCNSPIRV-NEXT: [[ENTRY:.*:]] |
| // AMDGCNSPIRV-NEXT: [[B_SROA_0_0_COPYLOAD:%.*]] = load i32, ptr [[TMP0]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_2_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_2_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_3_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 8 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_3_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_3_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_4_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 12 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_4_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_4_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_5_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 16 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_5_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_5_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_6_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 20 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_6_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_6_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_7_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 24 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_7_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_7_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_8_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 28 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_8_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_8_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_9_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 32 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_9_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_9_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_10_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 36 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_10_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_10_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_11_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 40 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_11_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_11_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_12_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 44 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_12_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_12_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_13_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 48 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_13_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_13_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_14_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 52 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_14_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_14_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_15_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 56 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_15_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_15_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_16_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 60 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_16_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_16_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_17_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 64 |
| // AMDGCNSPIRV-NEXT: [[B_SROA_17_0_COPYLOAD:%.*]] = load i32, ptr [[B_SROA_17_0__SROA_IDX]], align 4 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] poison, i32 [[B_SROA_0_0_COPYLOAD]], 0, 0 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_0_INSERT]], i32 [[B_SROA_2_0_COPYLOAD]], 0, 1 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_1_INSERT]], i32 [[B_SROA_3_0_COPYLOAD]], 0, 2 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_2_INSERT]], i32 [[B_SROA_4_0_COPYLOAD]], 0, 3 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_4_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_3_INSERT]], i32 [[B_SROA_5_0_COPYLOAD]], 0, 4 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_5_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_4_INSERT]], i32 [[B_SROA_6_0_COPYLOAD]], 0, 5 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_6_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_5_INSERT]], i32 [[B_SROA_7_0_COPYLOAD]], 0, 6 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_7_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_6_INSERT]], i32 [[B_SROA_8_0_COPYLOAD]], 0, 7 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_8_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_7_INSERT]], i32 [[B_SROA_9_0_COPYLOAD]], 0, 8 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_9_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_8_INSERT]], i32 [[B_SROA_10_0_COPYLOAD]], 0, 9 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_10_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_9_INSERT]], i32 [[B_SROA_11_0_COPYLOAD]], 0, 10 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_11_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_10_INSERT]], i32 [[B_SROA_12_0_COPYLOAD]], 0, 11 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_12_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_11_INSERT]], i32 [[B_SROA_13_0_COPYLOAD]], 0, 12 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_13_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_12_INSERT]], i32 [[B_SROA_14_0_COPYLOAD]], 0, 13 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_14_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_13_INSERT]], i32 [[B_SROA_15_0_COPYLOAD]], 0, 14 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_15_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_14_INSERT]], i32 [[B_SROA_16_0_COPYLOAD]], 0, 15 |
| // AMDGCNSPIRV-NEXT: [[DOTFCA_0_16_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_15_INSERT]], i32 [[B_SROA_17_0_COPYLOAD]], 0, 16 |
| // AMDGCNSPIRV-NEXT: tail call spir_func addrspace(4) void (i32, ...) @variadic(i32 noundef 1, [[STRUCT_BYREF]] [[DOTFCA_0_16_INSERT]]) #[[ATTR5:[0-9]+]] |
| // AMDGCNSPIRV-NEXT: ret void |
| // |
| // AMDGPU-LABEL: define dso_local void @_Z3f175ByRef( |
| // AMDGPU-SAME: ptr addrspace(5) nofree noundef readonly byref([[STRUCT_BYREF:%.*]]) align 4 captures(none) [[TMP0:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] { |
| // AMDGPU-NEXT: [[ENTRY:.*:]] |
| // AMDGPU-NEXT: [[B_SROA_0_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_2_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 4 |
| // AMDGPU-NEXT: [[B_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_2_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_3_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 8 |
| // AMDGPU-NEXT: [[B_SROA_3_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_3_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_4_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 12 |
| // AMDGPU-NEXT: [[B_SROA_4_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_4_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_5_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 16 |
| // AMDGPU-NEXT: [[B_SROA_5_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_5_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_6_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 20 |
| // AMDGPU-NEXT: [[B_SROA_6_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_6_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_7_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 24 |
| // AMDGPU-NEXT: [[B_SROA_7_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_7_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_8_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 28 |
| // AMDGPU-NEXT: [[B_SROA_8_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_8_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_9_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 32 |
| // AMDGPU-NEXT: [[B_SROA_9_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_9_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_10_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 36 |
| // AMDGPU-NEXT: [[B_SROA_10_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_10_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_11_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 40 |
| // AMDGPU-NEXT: [[B_SROA_11_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_11_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_12_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 44 |
| // AMDGPU-NEXT: [[B_SROA_12_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_12_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_13_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 48 |
| // AMDGPU-NEXT: [[B_SROA_13_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_13_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_14_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 52 |
| // AMDGPU-NEXT: [[B_SROA_14_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_14_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_15_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 56 |
| // AMDGPU-NEXT: [[B_SROA_15_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_15_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_16_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 60 |
| // AMDGPU-NEXT: [[B_SROA_16_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_16_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[B_SROA_17_0__SROA_IDX:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(5) [[TMP0]], i32 64 |
| // AMDGPU-NEXT: [[B_SROA_17_0_COPYLOAD:%.*]] = load i32, ptr addrspace(5) [[B_SROA_17_0__SROA_IDX]], align 4 |
| // AMDGPU-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] poison, i32 [[B_SROA_0_0_COPYLOAD]], 0, 0 |
| // AMDGPU-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_0_INSERT]], i32 [[B_SROA_2_0_COPYLOAD]], 0, 1 |
| // AMDGPU-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_1_INSERT]], i32 [[B_SROA_3_0_COPYLOAD]], 0, 2 |
| // AMDGPU-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_2_INSERT]], i32 [[B_SROA_4_0_COPYLOAD]], 0, 3 |
| // AMDGPU-NEXT: [[DOTFCA_0_4_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_3_INSERT]], i32 [[B_SROA_5_0_COPYLOAD]], 0, 4 |
| // AMDGPU-NEXT: [[DOTFCA_0_5_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_4_INSERT]], i32 [[B_SROA_6_0_COPYLOAD]], 0, 5 |
| // AMDGPU-NEXT: [[DOTFCA_0_6_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_5_INSERT]], i32 [[B_SROA_7_0_COPYLOAD]], 0, 6 |
| // AMDGPU-NEXT: [[DOTFCA_0_7_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_6_INSERT]], i32 [[B_SROA_8_0_COPYLOAD]], 0, 7 |
| // AMDGPU-NEXT: [[DOTFCA_0_8_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_7_INSERT]], i32 [[B_SROA_9_0_COPYLOAD]], 0, 8 |
| // AMDGPU-NEXT: [[DOTFCA_0_9_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_8_INSERT]], i32 [[B_SROA_10_0_COPYLOAD]], 0, 9 |
| // AMDGPU-NEXT: [[DOTFCA_0_10_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_9_INSERT]], i32 [[B_SROA_11_0_COPYLOAD]], 0, 10 |
| // AMDGPU-NEXT: [[DOTFCA_0_11_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_10_INSERT]], i32 [[B_SROA_12_0_COPYLOAD]], 0, 11 |
| // AMDGPU-NEXT: [[DOTFCA_0_12_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_11_INSERT]], i32 [[B_SROA_13_0_COPYLOAD]], 0, 12 |
| // AMDGPU-NEXT: [[DOTFCA_0_13_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_12_INSERT]], i32 [[B_SROA_14_0_COPYLOAD]], 0, 13 |
| // AMDGPU-NEXT: [[DOTFCA_0_14_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_13_INSERT]], i32 [[B_SROA_15_0_COPYLOAD]], 0, 14 |
| // AMDGPU-NEXT: [[DOTFCA_0_15_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_14_INSERT]], i32 [[B_SROA_16_0_COPYLOAD]], 0, 15 |
| // AMDGPU-NEXT: [[DOTFCA_0_16_INSERT:%.*]] = insertvalue [[STRUCT_BYREF]] [[DOTFCA_0_15_INSERT]], i32 [[B_SROA_17_0_COPYLOAD]], 0, 16 |
| // AMDGPU-NEXT: tail call void (i32, ...) @variadic(i32 noundef 1, [[STRUCT_BYREF]] [[DOTFCA_0_16_INSERT]]) #[[ATTR6:[0-9]+]] |
| // AMDGPU-NEXT: ret void |
| // |
| __device__ void f17(ByRef b) { variadic(1, b); } |
| //. |
| // AMDGCNSPIRV: [[META8]] = !{i32 1024, i32 1, i32 1} |
| //. |
