llvm/test/Transforms/LoopInterchange/inner-latch-lcssa-feeds-exit-condition.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -passes=loop-interchange -loop-interchange-profitabilities=ignore \
; RUN:     -verify-dom-info -verify-loop-info -verify-loop-lcssa -S | FileCheck %s

; After interchanging the innermost and the middle loop, an lcssa phi in the new
; inner latch feeds the latch's exit condition. Interchanging the (new) middle
; and outermost loop would clone that condition and leave the lcssa phi with a
; stale incoming block, producing invalid IR. Make sure the second interchange
; is rejected instead of crashing, even though the outermost latch has a single
; predecessor.

define void @t(i32 %b) {
; CHECK-LABEL: define void @t(
; CHECK-SAME: i32 [[B:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[OUTER_HEADER:.*]]
; CHECK:       [[OUTER_HEADER]]:
; CHECK-NEXT:    [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
; CHECK-NEXT:    br label %[[INNER_HEADER_PREHEADER:.*]]
; CHECK:       [[MID_HEADER_PREHEADER:.*]]:
; CHECK-NEXT:    br label %[[MID_HEADER:.*]]
; CHECK:       [[MID_HEADER]]:
; CHECK-NEXT:    [[J:%.*]] = phi i64 [ [[J_NEXT:%.*]], %[[MID_LATCH:.*]] ], [ 0, %[[MID_HEADER_PREHEADER]] ]
; CHECK-NEXT:    [[MWIDE:%.*]] = zext i32 [[B]] to i64
; CHECK-NEXT:    br label %[[INNER_LATCH:.*]]
; CHECK:       [[INNER_HEADER_PREHEADER]]:
; CHECK-NEXT:    br label %[[INNER_HEADER:.*]]
; CHECK:       [[INNER_HEADER]]:
; CHECK-NEXT:    [[K:%.*]] = phi i64 [ [[TMP0:%.*]], %[[INNER_LATCH_SPLIT:.*]] ], [ 0, %[[INNER_HEADER_PREHEADER]] ]
; CHECK-NEXT:    br label %[[MID_HEADER_PREHEADER]]
; CHECK:       [[INNER_LATCH]]:
; CHECK-NEXT:    [[K_NEXT:%.*]] = add nsw i64 [[K]], 1
; CHECK-NEXT:    [[EC_K:%.*]] = icmp eq i64 [[K_NEXT]], [[MWIDE]]
; CHECK-NEXT:    br label %[[MID_LATCH]]
; CHECK:       [[INNER_LATCH_SPLIT]]:
; CHECK-NEXT:    [[MWIDE_LCSSA:%.*]] = phi i64 [ [[MWIDE]], %[[MID_LATCH]] ]
; CHECK-NEXT:    [[TMP0]] = add nsw i64 [[K]], 1
; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 [[TMP0]], [[MWIDE_LCSSA]]
; CHECK-NEXT:    br i1 [[TMP1]], label %[[OUTER_LATCH]], label %[[INNER_HEADER]]
; CHECK:       [[MID_LATCH]]:
; CHECK-NEXT:    [[J_NEXT]] = add nsw i64 [[J]], 1
; CHECK-NEXT:    [[EC_J:%.*]] = icmp eq i64 [[J_NEXT]], 100
; CHECK-NEXT:    br i1 [[EC_J]], label %[[INNER_LATCH_SPLIT]], label %[[MID_HEADER]]
; CHECK:       [[OUTER_LATCH]]:
; CHECK-NEXT:    [[I_NEXT]] = add nsw i64 [[I]], 1
; CHECK-NEXT:    [[EC_I:%.*]] = icmp eq i64 [[I_NEXT]], 100
; CHECK-NEXT:    br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %outer.header

outer.header:
  %i = phi i64 [ 0, %entry ], [ %i.next, %outer.latch ]
  br label %mid.header

mid.header:
  %j = phi i64 [ 0, %outer.header ], [ %j.next, %mid.latch ]
  %mwide = zext i32 %b to i64                 ; non-induction value, middle-loop invariant
  br label %inner.header

inner.header:
  %k = phi i64 [ 0, %mid.header ], [ %k.next, %inner.header ]
  %k.next = add nsw i64 %k, 1
  %ec.k = icmp eq i64 %k.next, %mwide         ; inner exit uses the middle-header value
  br i1 %ec.k, label %mid.latch, label %inner.header

mid.latch:
  %j.next = add nsw i64 %j, 1
  %ec.j = icmp eq i64 %j.next, 100
  br i1 %ec.j, label %outer.latch, label %mid.header

outer.latch:
  %i.next = add nsw i64 %i, 1
  %ec.i = icmp eq i64 %i.next, 100
  br i1 %ec.i, label %exit, label %outer.header

exit:
  ret void
}