llvm/test/Transforms/LoopInterchange/inner-header-has-duplicate-succs.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -passes=loop-interchange -loop-interchange-profitabilities=ignore -S | FileCheck %s

; These test cases verify that we do not interchange loops when the inner loop
; header contains duplicate successors. Previously, some of these cases were
; not handled correctly and resulted in crashes.

; The inner loop header contains a br instruction with duplicate successors, so
; we cannot interchange the loops.
;
define void @inner_header_br_dup(i1 %cond, ptr %A) {
; CHECK-LABEL: define void @inner_header_br_dup(
; CHECK-SAME: i1 [[COND:%.*]], ptr [[A:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[OUTER_HEADER:.*]]
; CHECK:       [[OUTER_HEADER]]:
; CHECK-NEXT:    [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[OUTER_LATCH:.*]] ]
; CHECK-NEXT:    br label %[[INNER_HEADER:.*]]
; CHECK:       [[INNER_HEADER]]:
; CHECK-NEXT:    [[J:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[J_INC:%.*]], %[[INNER_LATCH:.*]] ]
; CHECK-NEXT:    br i1 [[COND]], label %[[INNER_LATCH]], label %[[INNER_LATCH]]
; CHECK:       [[INNER_LATCH]]:
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr [8 x i8], ptr [[A]], i64 [[J]], i64 [[I]]
; CHECK-NEXT:    store i8 0, ptr [[GEP]], align 1
; CHECK-NEXT:    [[J_INC]] = add i64 [[J]], 1
; CHECK-NEXT:    [[EC_J:%.*]] = icmp eq i64 [[J_INC]], 8
; CHECK-NEXT:    br i1 [[EC_J]], label %[[OUTER_LATCH]], label %[[INNER_HEADER]]
; CHECK:       [[OUTER_LATCH]]:
; CHECK-NEXT:    [[I_INC]] = add i64 [[I]], 1
; CHECK-NEXT:    [[EC_I:%.*]] = icmp eq i64 [[I_INC]], 8
; CHECK-NEXT:    br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %outer.header

outer.header:
  %i = phi i64 [ 0, %entry ], [ %i.inc, %outer.latch ]
  br label %inner.header

inner.header:
  %j = phi i64 [ 0, %outer.header ], [ %j.inc, %inner.latch ]
  br i1 %cond, label %inner.latch, label %inner.latch

inner.latch:
  %gep = getelementptr [8 x i8], ptr %A, i64 %j, i64 %i
  store i8 0, ptr %gep
  %j.inc = add i64 %j, 1
  %ec.j = icmp eq i64 %j.inc, 8
  br i1 %ec.j, label %outer.latch, label %inner.header

outer.latch:
  %i.inc = add i64 %i, 1
  %ec.i = icmp eq i64 %i.inc, 8
  br i1 %ec.i, label %exit, label %outer.header

exit:
  ret void
}

; The inner loop header contains a switch instruction with duplicate
; successors, so we cannot interchange the loops.
;
define void @inner_header_switch_dup0(i8 %sel, ptr %A) {
; CHECK-LABEL: define void @inner_header_switch_dup0(
; CHECK-SAME: i8 [[SEL:%.*]], ptr [[A:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[OUTER_HEADER:.*]]
; CHECK:       [[OUTER_HEADER]]:
; CHECK-NEXT:    [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[OUTER_LATCH:.*]] ]
; CHECK-NEXT:    br label %[[INNER_HEADER:.*]]
; CHECK:       [[INNER_HEADER]]:
; CHECK-NEXT:    [[J:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[J_INC:%.*]], %[[INNER_LATCH:.*]] ]
; CHECK-NEXT:    switch i8 [[SEL]], label %[[INNER_LATCH]] [
; CHECK-NEXT:      i8 0, label %[[INNER_LATCH]]
; CHECK-NEXT:      i8 1, label %[[INNER_BODY:.*]]
; CHECK-NEXT:    ]
; CHECK:       [[INNER_BODY]]:
; CHECK-NEXT:    br label %[[INNER_LATCH]]
; CHECK:       [[INNER_LATCH]]:
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr [8 x i8], ptr [[A]], i64 [[J]], i64 [[I]]
; CHECK-NEXT:    store i8 0, ptr [[GEP]], align 1
; CHECK-NEXT:    [[J_INC]] = add i64 [[J]], 1
; CHECK-NEXT:    [[EC_J:%.*]] = icmp eq i64 [[J_INC]], 8
; CHECK-NEXT:    br i1 [[EC_J]], label %[[OUTER_LATCH]], label %[[INNER_HEADER]]
; CHECK:       [[OUTER_LATCH]]:
; CHECK-NEXT:    [[I_INC]] = add i64 [[I]], 1
; CHECK-NEXT:    [[EC_I:%.*]] = icmp eq i64 [[I_INC]], 8
; CHECK-NEXT:    br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %outer.header

outer.header:
  %i = phi i64 [ 0, %entry ], [ %i.inc, %outer.latch ]
  br label %inner.header

inner.header:
  %j = phi i64 [ 0, %outer.header ], [ %j.inc, %inner.latch ]
  switch i8 %sel, label %inner.latch [ i8 0, label %inner.latch i8 1, label %inner.body ]

inner.body:
  br label %inner.latch

inner.latch:
  %gep = getelementptr [8 x i8], ptr %A, i64 %j, i64 %i
  store i8 0, ptr %gep
  %j.inc = add i64 %j, 1
  %ec.j = icmp eq i64 %j.inc, 8
  br i1 %ec.j, label %outer.latch, label %inner.header

outer.latch:
  %i.inc = add i64 %i, 1
  %ec.i = icmp eq i64 %i.inc, 8
  br i1 %ec.i, label %exit, label %outer.header

exit:
  ret void
}

; The inner loop header contains a switch instruction with duplicate
; successors, so we cannot interchange the loops.
;
define void @inner_header_switch_dup1(i8 %sel, ptr %A) {
; CHECK-LABEL: define void @inner_header_switch_dup1(
; CHECK-SAME: i8 [[SEL:%.*]], ptr [[A:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[OUTER_HEADER:.*]]
; CHECK:       [[OUTER_HEADER]]:
; CHECK-NEXT:    [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_INC:%.*]], %[[OUTER_LATCH:.*]] ]
; CHECK-NEXT:    br label %[[INNER_HEADER:.*]]
; CHECK:       [[INNER_HEADER]]:
; CHECK-NEXT:    [[J:%.*]] = phi i64 [ 0, %[[OUTER_HEADER]] ], [ [[J_INC:%.*]], %[[INNER_LATCH:.*]] ]
; CHECK-NEXT:    switch i8 [[SEL]], label %[[INNER_LATCH]] [
; CHECK-NEXT:      i8 0, label %[[INNER_LATCH]]
; CHECK-NEXT:      i8 1, label %[[INNER_LATCH]]
; CHECK-NEXT:    ]
; CHECK:       [[INNER_BODY:.*:]]
; CHECK-NEXT:    unreachable
; CHECK:       [[INNER_LATCH]]:
; CHECK-NEXT:    [[GEP:%.*]] = getelementptr [8 x i8], ptr [[A]], i64 [[J]], i64 [[I]]
; CHECK-NEXT:    store i8 0, ptr [[GEP]], align 1
; CHECK-NEXT:    [[J_INC]] = add i64 [[J]], 1
; CHECK-NEXT:    [[EC_J:%.*]] = icmp eq i64 [[J_INC]], 8
; CHECK-NEXT:    br i1 [[EC_J]], label %[[OUTER_LATCH]], label %[[INNER_HEADER]]
; CHECK:       [[OUTER_LATCH]]:
; CHECK-NEXT:    [[I_INC]] = add i64 [[I]], 1
; CHECK-NEXT:    [[EC_I:%.*]] = icmp eq i64 [[I_INC]], 8
; CHECK-NEXT:    br i1 [[EC_I]], label %[[EXIT:.*]], label %[[OUTER_HEADER]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %outer.header

outer.header:
  %i = phi i64 [ 0, %entry ], [ %i.inc, %outer.latch ]
  br label %inner.header

inner.header:
  %j = phi i64 [ 0, %outer.header ], [ %j.inc, %inner.latch ]
  switch i8 %sel, label %inner.latch [ i8 0, label %inner.latch i8 1, label %inner.latch ]

inner.body:
  br label %inner.latch

inner.latch:
  %gep = getelementptr [8 x i8], ptr %A, i64 %j, i64 %i
  store i8 0, ptr %gep
  %j.inc = add i64 %j, 1
  %ec.j = icmp eq i64 %j.inc, 8
  br i1 %ec.j, label %outer.latch, label %inner.header

outer.latch:
  %i.inc = add i64 %i, 1
  %ec.i = icmp eq i64 %i.inc, 8
  br i1 %ec.i, label %exit, label %outer.header

exit:
  ret void
}