llvm/test/CodeGen/X86/vector-idiv-strictfp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,NODQ
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=CHECK,DQ

define <16 x i8> @test_divv_16i8_strictfp(<16 x i8> %a, <16 x i8> %b) nounwind strictfp {
; CHECK-LABEL: test_divv_16i8_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2udq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vpmovdb %zmm0, %xmm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = udiv <16 x i8> %a, %b
  ret <16 x i8> %res
}

define <4 x i32> @test_sdivv_4i32_strictfp(<4 x i32> %a, <4 x i32> %b) nounwind strictfp {
; CHECK-LABEL: test_sdivv_4i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %xmm1, %ymm1
; CHECK-NEXT:    vcvtdq2pd %xmm0, %ymm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <4 x i32> %a, %b
  ret <4 x i32> %res
}

define <8 x i16> @test_sdivv_8i16_strictfp(<8 x i16> %a, <8 x i16> %b) nounwind strictfp {
; CHECK-LABEL: test_sdivv_8i16_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpmovsxwd %xmm1, %ymm1
; CHECK-NEXT:    vcvtdq2ps %ymm1, %ymm1
; CHECK-NEXT:    vpmovsxwd %xmm0, %ymm0
; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2dq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vpmovdw %zmm0, %ymm0
; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <8 x i16> %a, %b
  ret <8 x i16> %res
}

define <8 x i32> @test_remv_8i32_strictfp(<8 x i32> %a, <8 x i32> %b) nounwind strictfp {
; CHECK-LABEL: test_remv_8i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vpmulld %ymm1, %ymm2, %ymm1
; CHECK-NEXT:    vpsubd %ymm1, %ymm0, %ymm0
; CHECK-NEXT:    retq
  %res = urem <8 x i32> %a, %b
  ret <8 x i32> %res
}

define <8 x i32> @test_masked_divv_8i32_strictfp(<8 x i32> %a, <8 x i32> %b, <8 x i1> %m) nounwind strictfp {
; CHECK-LABEL: test_masked_divv_8i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm1
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    retq
  %res = call <8 x i32> @llvm.masked.udiv(<8 x i32> %a, <8 x i32> %b, <8 x i1> %m)
  ret <8 x i32> %res
}

define <16 x i32> @test_masked_divv_16i32_strictfp(<16 x i32> %a, <16 x i32> %b, <16 x i1> %m) nounwind strictfp {
; CHECK-LABEL: test_masked_divv_16i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm1, %ymm1
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm1
; CHECK-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vinsertf64x4 $1, %ymm0, %zmm2, %zmm0
; CHECK-NEXT:    retq
  %res = call <16 x i32> @llvm.masked.udiv(<16 x i32> %a, <16 x i32> %b, <16 x i1> %m)
  ret <16 x i32> %res
}

define <16 x i32> @test_divv_16i32_strictfp(<16 x i32> %a, <16 x i32> %b) nounwind strictfp {
; CHECK-LABEL: test_divv_16i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm1, %ymm1
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm1
; CHECK-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vinsertf64x4 $1, %ymm0, %zmm2, %zmm0
; CHECK-NEXT:    retq
  %res = udiv <16 x i32> %a, %b
  ret <16 x i32> %res
}

define void @test_divv_9i32_strictfp(<9 x i32> %a, <9 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_9i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm2
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextracti32x4 $2, %zmm0, %xmm0
; CHECK-NEXT:    vmovd %xmm0, %eax
; CHECK-NEXT:    vextracti32x4 $2, %zmm1, %xmm0
; CHECK-NEXT:    vmovd %xmm0, %ecx
; CHECK-NEXT:    cltd
; CHECK-NEXT:    idivl %ecx
; CHECK-NEXT:    movl %eax, 32(%rdi)
; CHECK-NEXT:    vmovaps %ymm2, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <9 x i32> %a, %b
  store <9 x i32> %res, ptr %p
  ret void
}

define void @test_divv_12i32_strictfp(<12 x i32> %a, <12 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_12i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vextractf32x4 $2, %zmm1, %xmm2
; CHECK-NEXT:    vcvtdq2pd %xmm2, %ymm2
; CHECK-NEXT:    vextractf32x4 $2, %zmm0, %xmm3
; CHECK-NEXT:    vcvtdq2pd %xmm3, %ymm3
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm3, %zmm2
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm1
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vmovaps %ymm0, (%rdi)
; CHECK-NEXT:    vmovaps %xmm2, 32(%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <12 x i32> %a, %b
  store <12 x i32> %res, ptr %p
  ret void
}

define <6 x i32> @test_masked_divv_6i32_strictfp(<6 x i32> %a, <6 x i32> %b, <6 x i1> %m) nounwind strictfp {
; CHECK-LABEL: test_masked_divv_6i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm1
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    retq
  %res = call <6 x i32> @llvm.masked.sdiv(<6 x i32> %a, <6 x i32> %b, <6 x i1> %m)
  ret <6 x i32> %res
}

define void @test_divv_32i32_strictfp(<32 x i32> %a, <32 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_32i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtdq2pd %ymm2, %zmm4
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm5
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm4, %zmm5, %zmm4
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm4, %ymm4
; CHECK-NEXT:    vextractf64x4 $1, %zmm2, %ymm2
; CHECK-NEXT:    vcvtdq2pd %ymm2, %zmm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm0, %ymm0
; CHECK-NEXT:    vcvtdq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vinsertf64x4 $1, %ymm0, %zmm4, %zmm0
; CHECK-NEXT:    vcvtdq2pd %ymm3, %zmm2
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm4
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm2, %zmm4, %zmm2
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm2, %ymm2
; CHECK-NEXT:    vextractf64x4 $1, %zmm3, %ymm3
; CHECK-NEXT:    vcvtdq2pd %ymm3, %zmm3
; CHECK-NEXT:    vextractf64x4 $1, %zmm1, %ymm1
; CHECK-NEXT:    vcvtdq2pd %ymm1, %zmm1
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm3, %zmm1, %zmm1
; CHECK-NEXT:    vcvttpd2dq {sae}, %zmm1, %ymm1
; CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm2, %zmm1
; CHECK-NEXT:    vmovaps %zmm1, 64(%rdi)
; CHECK-NEXT:    vmovaps %zmm0, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = sdiv <32 x i32> %a, %b
  store <32 x i32> %res, ptr %p
  ret void
}

define void @test_divv_7i32_strictfp(<7 x i32> %a, <7 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_7i32_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vcvtudq2pd %ymm1, %zmm1
; CHECK-NEXT:    vcvtudq2pd %ymm0, %zmm0
; CHECK-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttpd2udq {sae}, %zmm0, %ymm0
; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
; CHECK-NEXT:    vextractps $2, %xmm1, 24(%rdi)
; CHECK-NEXT:    vmovlps %xmm1, 16(%rdi)
; CHECK-NEXT:    vmovaps %xmm0, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = udiv <7 x i32> %a, %b
  store <7 x i32> %res, ptr %p
  ret void
}

define void @test_divv_7i16_strictfp(<7 x i16> %a, <7 x i16> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_7i16_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; CHECK-NEXT:    vcvtdq2ps %ymm1, %ymm1
; CHECK-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2udq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vpmovdw %zmm0, %ymm0
; CHECK-NEXT:    vpextrw $6, %xmm0, 12(%rdi)
; CHECK-NEXT:    vpextrd $2, %xmm0, 8(%rdi)
; CHECK-NEXT:    vmovq %xmm0, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = udiv <7 x i16> %a, %b
  store <7 x i16> %res, ptr %p
  ret void
}

define void @test_divv_15i8_strictfp(<15 x i8> %a, <15 x i8> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_15i8_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2udq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vpmovdb %zmm0, %xmm0
; CHECK-NEXT:    vpextrb $14, %xmm0, 14(%rdi)
; CHECK-NEXT:    vpextrw $6, %xmm0, 12(%rdi)
; CHECK-NEXT:    vpextrd $2, %xmm0, 8(%rdi)
; CHECK-NEXT:    vmovq %xmm0, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = udiv <15 x i8> %a, %b
  store <15 x i8> %res, ptr %p
  ret void
}

define void @test_divv_15i16_strictfp(<15 x i16> %a, <15 x i16> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_15i16_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
; CHECK-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2udq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vpmovdw %zmm0, %ymm0
; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm1
; CHECK-NEXT:    vpextrw $6, %xmm1, 28(%rdi)
; CHECK-NEXT:    vpextrd $2, %xmm1, 24(%rdi)
; CHECK-NEXT:    vmovq %xmm1, 16(%rdi)
; CHECK-NEXT:    vmovdqa %xmm0, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %res = udiv <15 x i16> %a, %b
  store <15 x i16> %res, ptr %p
  ret void
}

define <8 x i64> @test_divv_8i64_strictfp(<8 x i64> %a, <8 x i64> %b) nounwind strictfp {
; NODQ-LABEL: test_divv_8i64_strictfp:
; NODQ:       # %bb.0:
; NODQ-NEXT:    vextracti32x4 $3, %zmm0, %xmm2
; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
; NODQ-NEXT:    vextracti32x4 $3, %zmm1, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %rcx
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rcx
; NODQ-NEXT:    movq %rax, %rcx
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vmovq %xmm3, %rsi
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rsi
; NODQ-NEXT:    movq %rax, %rsi
; NODQ-NEXT:    vextracti32x4 $2, %zmm0, %xmm2
; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
; NODQ-NEXT:    vextracti32x4 $2, %zmm1, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %rdi
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rdi
; NODQ-NEXT:    movq %rax, %rdi
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vmovq %xmm3, %r8
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r8
; NODQ-NEXT:    movq %rax, %r8
; NODQ-NEXT:    vextracti128 $1, %ymm0, %xmm2
; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
; NODQ-NEXT:    vextracti128 $1, %ymm1, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %r9
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r9
; NODQ-NEXT:    movq %rax, %r9
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vmovq %xmm3, %r10
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r10
; NODQ-NEXT:    movq %rax, %r10
; NODQ-NEXT:    vpextrq $1, %xmm0, %rax
; NODQ-NEXT:    vpextrq $1, %xmm1, %r11
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r11
; NODQ-NEXT:    vmovq %rcx, %xmm2
; NODQ-NEXT:    vmovq %rsi, %xmm3
; NODQ-NEXT:    vmovq %rdi, %xmm4
; NODQ-NEXT:    vmovq %r8, %xmm5
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; NODQ-NEXT:    vmovq %r9, %xmm3
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
; NODQ-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
; NODQ-NEXT:    vmovq %r10, %xmm4
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
; NODQ-NEXT:    vmovq %rax, %xmm4
; NODQ-NEXT:    vmovq %xmm0, %rax
; NODQ-NEXT:    vmovq %xmm1, %rcx
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rcx
; NODQ-NEXT:    vmovq %rax, %xmm0
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
; NODQ-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
; NODQ-NEXT:    vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; NODQ-NEXT:    retq
;
; DQ-LABEL: test_divv_8i64_strictfp:
; DQ:       # %bb.0:
; DQ-NEXT:    vcvtuqq2pd {ru-sae}, %zmm1, %zmm2
; DQ-NEXT:    vbroadcastsd {{.*#+}} zmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; DQ-NEXT:    vdivpd {rd-sae}, %zmm2, %zmm3, %zmm2
; DQ-NEXT:    vcvtuqq2pd {rd-sae}, %zmm0, %zmm3
; DQ-NEXT:    vmulpd {rd-sae}, %zmm2, %zmm3, %zmm3
; DQ-NEXT:    vcvtpd2uqq {rd-sae}, %zmm3, %zmm3
; DQ-NEXT:    vpmullq %zmm1, %zmm3, %zmm4
; DQ-NEXT:    vpsubq %zmm4, %zmm0, %zmm0
; DQ-NEXT:    vcvtuqq2pd {rd-sae}, %zmm0, %zmm4
; DQ-NEXT:    vmulpd {rd-sae}, %zmm2, %zmm4, %zmm2
; DQ-NEXT:    vcvtpd2uqq {rd-sae}, %zmm2, %zmm2
; DQ-NEXT:    vpaddq %zmm2, %zmm3, %zmm3
; DQ-NEXT:    vpmullq %zmm1, %zmm2, %zmm2
; DQ-NEXT:    vpsubq %zmm2, %zmm0, %zmm0
; DQ-NEXT:    vpcmpnltuq %zmm1, %zmm0, %k0
; DQ-NEXT:    vpmovm2q %k0, %zmm0
; DQ-NEXT:    vpsubq %zmm0, %zmm3, %zmm0
; DQ-NEXT:    retq
  %res = udiv <8 x i64> %a, %b
  ret <8 x i64> %res
}
define <8 x i64> @test_divv_8i64_narrow_strictfp(<8 x i64> %a, <8 x i64> %b) nounwind strictfp {
; NODQ-LABEL: test_divv_8i64_narrow_strictfp:
; NODQ:       # %bb.0:
; NODQ-NEXT:    vpsrlq $12, %zmm0, %zmm0
; NODQ-NEXT:    vpsrlq $12, %zmm1, %zmm1
; NODQ-NEXT:    vextracti32x4 $3, %zmm0, %xmm2
; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
; NODQ-NEXT:    vextracti32x4 $3, %zmm1, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %rcx
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rcx
; NODQ-NEXT:    movq %rax, %rcx
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vmovq %xmm3, %rsi
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rsi
; NODQ-NEXT:    movq %rax, %rsi
; NODQ-NEXT:    vextracti32x4 $2, %zmm0, %xmm2
; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
; NODQ-NEXT:    vextracti32x4 $2, %zmm1, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %rdi
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rdi
; NODQ-NEXT:    movq %rax, %rdi
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vmovq %xmm3, %r8
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r8
; NODQ-NEXT:    movq %rax, %r8
; NODQ-NEXT:    vextracti128 $1, %ymm0, %xmm2
; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
; NODQ-NEXT:    vextracti128 $1, %ymm1, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %r9
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r9
; NODQ-NEXT:    movq %rax, %r9
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vmovq %xmm3, %r10
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r10
; NODQ-NEXT:    movq %rax, %r10
; NODQ-NEXT:    vpextrq $1, %xmm0, %rax
; NODQ-NEXT:    vpextrq $1, %xmm1, %r11
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r11
; NODQ-NEXT:    vmovq %rcx, %xmm2
; NODQ-NEXT:    vmovq %rsi, %xmm3
; NODQ-NEXT:    vmovq %rdi, %xmm4
; NODQ-NEXT:    vmovq %r8, %xmm5
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; NODQ-NEXT:    vmovq %r9, %xmm3
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
; NODQ-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
; NODQ-NEXT:    vmovq %r10, %xmm4
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0]
; NODQ-NEXT:    vmovq %rax, %xmm4
; NODQ-NEXT:    vmovq %xmm0, %rax
; NODQ-NEXT:    vmovq %xmm1, %rcx
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rcx
; NODQ-NEXT:    vmovq %rax, %xmm0
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
; NODQ-NEXT:    vinserti128 $1, %xmm3, %ymm0, %ymm0
; NODQ-NEXT:    vinserti64x4 $1, %ymm2, %zmm0, %zmm0
; NODQ-NEXT:    retq
;
; DQ-LABEL: test_divv_8i64_narrow_strictfp:
; DQ:       # %bb.0:
; DQ-NEXT:    vpsrlq $12, %zmm0, %zmm0
; DQ-NEXT:    vpsrlq $12, %zmm1, %zmm1
; DQ-NEXT:    vcvtqq2pd %zmm1, %zmm1
; DQ-NEXT:    vcvtqq2pd %zmm0, %zmm0
; DQ-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; DQ-NEXT:    vcvttpd2uqq {sae}, %zmm0, %zmm0
; DQ-NEXT:    retq
  %aa = lshr <8 x i64> %a, splat (i64 12)
  %bb = lshr <8 x i64> %b, splat (i64 12)
  %res = udiv <8 x i64> %aa, %bb
  ret <8 x i64> %res
}

define void @test_divv_7i64_narrow_strictfp(<7 x i64> %a, <7 x i64> %b, ptr %p) nounwind strictfp {
; NODQ-LABEL: test_divv_7i64_narrow_strictfp:
; NODQ:       # %bb.0:
; NODQ-NEXT:    vpsrlq $12, %zmm0, %zmm2
; NODQ-NEXT:    vpsrlq $12, %zmm1, %zmm0
; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
; NODQ-NEXT:    vpextrq $1, %xmm0, %rcx
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rcx
; NODQ-NEXT:    movq %rax, %rcx
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vmovq %xmm0, %rsi
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rsi
; NODQ-NEXT:    movq %rax, %rsi
; NODQ-NEXT:    vextracti128 $1, %ymm2, %xmm1
; NODQ-NEXT:    vpextrq $1, %xmm1, %rax
; NODQ-NEXT:    vextracti128 $1, %ymm0, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %r8
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r8
; NODQ-NEXT:    movq %rax, %r8
; NODQ-NEXT:    vmovq %xmm1, %rax
; NODQ-NEXT:    vmovq %xmm3, %r9
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r9
; NODQ-NEXT:    movq %rax, %r9
; NODQ-NEXT:    vextracti32x4 $2, %zmm2, %xmm1
; NODQ-NEXT:    vpextrq $1, %xmm1, %rax
; NODQ-NEXT:    vextracti32x4 $2, %zmm0, %xmm3
; NODQ-NEXT:    vpextrq $1, %xmm3, %r10
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r10
; NODQ-NEXT:    movq %rax, %r10
; NODQ-NEXT:    vmovq %xmm1, %rax
; NODQ-NEXT:    vmovq %xmm3, %r11
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %r11
; NODQ-NEXT:    vmovq %rcx, %xmm1
; NODQ-NEXT:    vmovq %rsi, %xmm3
; NODQ-NEXT:    vmovq %r8, %xmm4
; NODQ-NEXT:    vmovq %r9, %xmm5
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm3 = xmm5[0],xmm4[0]
; NODQ-NEXT:    vmovq %r10, %xmm4
; NODQ-NEXT:    vmovq %rax, %xmm5
; NODQ-NEXT:    vpunpcklqdq {{.*#+}} xmm4 = xmm5[0],xmm4[0]
; NODQ-NEXT:    vextracti32x4 $3, %zmm2, %xmm2
; NODQ-NEXT:    vmovq %xmm2, %rax
; NODQ-NEXT:    vextracti32x4 $3, %zmm0, %xmm0
; NODQ-NEXT:    vmovq %xmm0, %rcx
; NODQ-NEXT:    xorl %edx, %edx
; NODQ-NEXT:    divq %rcx
; NODQ-NEXT:    movq %rax, 48(%rdi)
; NODQ-NEXT:    vmovdqa %xmm4, 32(%rdi)
; NODQ-NEXT:    vmovdqa %xmm3, 16(%rdi)
; NODQ-NEXT:    vmovdqa %xmm1, (%rdi)
; NODQ-NEXT:    vzeroupper
; NODQ-NEXT:    retq
;
; DQ-LABEL: test_divv_7i64_narrow_strictfp:
; DQ:       # %bb.0:
; DQ-NEXT:    vpsrlq $12, %zmm0, %zmm0
; DQ-NEXT:    vpsrlq $12, %zmm1, %zmm1
; DQ-NEXT:    vcvtqq2pd %zmm1, %zmm1
; DQ-NEXT:    vcvtqq2pd %zmm0, %zmm0
; DQ-NEXT:    vdivpd {rn-sae}, %zmm1, %zmm0, %zmm0
; DQ-NEXT:    vcvttpd2uqq {sae}, %zmm0, %zmm0
; DQ-NEXT:    vextractf32x4 $2, %zmm0, 32(%rdi)
; DQ-NEXT:    vextractf32x4 $3, %zmm0, %xmm1
; DQ-NEXT:    vmovlps %xmm1, 48(%rdi)
; DQ-NEXT:    vmovaps %ymm0, (%rdi)
; DQ-NEXT:    vzeroupper
; DQ-NEXT:    retq
  %aa = lshr <7 x i64> %a, splat (i64 12)
  %bb = lshr <7 x i64> %b, splat (i64 12)
  %res = udiv <7 x i64> %aa, %bb
  store <7 x i64> %res, ptr %p
  ret void
}

define void @test_divv_7i32_narrow_strictfp(<7 x i32> %a, <7 x i32> %b, ptr %p) nounwind strictfp {
; CHECK-LABEL: test_divv_7i32_narrow_strictfp:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vpsrld $12, %ymm0, %ymm0
; CHECK-NEXT:    vpsrld $12, %ymm1, %ymm1
; CHECK-NEXT:    vcvtdq2ps %ymm1, %ymm1
; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
; CHECK-NEXT:    vcvttps2udq {sae}, %zmm0, %zmm0
; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
; CHECK-NEXT:    vextractps $2, %xmm1, 24(%rdi)
; CHECK-NEXT:    vmovlps %xmm1, 16(%rdi)
; CHECK-NEXT:    vmovaps %xmm0, (%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %aa = lshr <7 x i32> %a, splat (i32 12)
  %bb = lshr <7 x i32> %b, splat (i32 12)
  %res = udiv <7 x i32> %aa, %bb
  store <7 x i32> %res, ptr %p
  ret void
}