llvm/test/CodeGen/X86/domain-reassignment-closure-stats.mir

# REQUIRES: asserts
# RUN: llc -run-pass x86-domain-reassignment -mtriple=x86_64-unknown-unknown \
# RUN:   -mattr=+avx512f,+avx512bw,+avx512dq -stats %s -o /dev/null 2>&1 \
# RUN:   | FileCheck %s

# Regression test for buildClosure recording the seed register instead of the
# register actually added to the closure. Before the fix EnclosedEdges only ever
# held the seed of each closure, so every other member of an already-built
# closure looked like a fresh seed and a redundant closure was built for it and
# immediately discarded. The generated code is identical either way (the
# converted-closure count is unaffected); only the amount of redundant work
# changes. For test_8bitops the closure has eight members: buggy builds 12
# closures, the fix builds 2. The number of converted closures stays at 1.

# The leading {{^ *}} anchor prevents a stale "12" count from matching "2".
# CHECK-DAG: {{^ *}}2 x86-domain-reassignment - Number of closures built by the pass
# CHECK-DAG: {{^ *}}1 x86-domain-reassignment - Number of closures converted by the pass

--- |
  target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
  target triple = "x86_64-unknown-unknown"

  define void @test_8bitops() #0 {
    ret void
  }

  attributes #0 = { "target-cpu"="skylake-avx512" }
...
---
name:            test_8bitops
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vr512, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: vk8, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr8, preferred-register: '' }
  - { id: 8, class: gr32, preferred-register: '' }
  - { id: 9, class: gr32, preferred-register: '' }
  - { id: 10, class: vk8wm, preferred-register: '' }
  - { id: 11, class: vr512, preferred-register: '' }
  - { id: 12, class: gr8, preferred-register: '' }
  - { id: 13, class: gr8, preferred-register: '' }
  - { id: 14, class: gr8, preferred-register: '' }
  - { id: 15, class: gr8, preferred-register: '' }
  - { id: 16, class: gr8, preferred-register: '' }
  - { id: 17, class: gr8, preferred-register: '' }
  - { id: 18, class: gr8, preferred-register: '' }
liveins:
  - { reg: '$rdi', virtual-reg: '%0' }
  - { reg: '$zmm0', virtual-reg: '%1' }
  - { reg: '$zmm1', virtual-reg: '%2' }
  - { reg: '$zmm2', virtual-reg: '%3' }
  - { reg: '$zmm3', virtual-reg: '%4' }
body:             |
  bb.0:
    liveins: $rdi, $zmm0, $zmm1, $zmm2, $zmm3

    %0 = COPY $rdi
    %1 = COPY $zmm0
    %2 = COPY $zmm1
    %3 = COPY $zmm2
    %4 = COPY $zmm3

    %5 = VCMPPDZrri %3, %4, 0, implicit $mxcsr
    %6 = COPY %5
    %7 = COPY %6.sub_8bit

    %12 = SHR8ri %7, 2, implicit-def dead $eflags
    %13 = SHL8ri %12, 1, implicit-def dead $eflags
    %14 = NOT8r %13
    %15 = OR8rr %14, %12, implicit-def dead $eflags
    %16 = AND8rr %15, %13, implicit-def dead $eflags
    %17 = XOR8rr %16, %12, implicit-def dead $eflags
    %18 = ADD8rr %17, %14, implicit-def dead $eflags

    %8 = IMPLICIT_DEF
    %9 = INSERT_SUBREG %8, %18, %subreg.sub_8bit_hi
    %10 = COPY %9
    %11 = VMOVAPDZrrk %2, killed %10, %1
    VMOVAPDZmr %0, 1, $noreg, 0, $noreg, killed %11

  bb.1:

  bb.2:
    RET 0

...