llvm/test/CodeGen/RISCV/rvv/stlf.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s

define <vscale x 4 x i32> @test_stlf_riscv_scalable(ptr %p, <vscale x 4 x i32> %v) {
; CHECK-LABEL: test_stlf_riscv_scalable:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vs2r.v v8, (a0)
; CHECK-NEXT:    ret
  store <vscale x 4 x i32> %v, ptr %p
  %res = load <vscale x 4 x i32>, ptr %p
  ret <vscale x 4 x i32> %res
}

define void @test_stlf_i32_to_v2i8_assertion(ptr %arg, ptr %arg1) {
; CHECK-LABEL: test_stlf_i32_to_v2i8_assertion:
; CHECK:       # %bb.0: # %bb
; CHECK-NEXT:    addi sp, sp, -16
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    sw zero, 0(zero)
; CHECK-NEXT:    lbu a2, 5(a0)
; CHECK-NEXT:    lbu a3, 4(a0)
; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT:    vle8.v v8, (a0)
; CHECK-NEXT:    slli a2, a2, 8
; CHECK-NEXT:    or a2, a2, a3
; CHECK-NEXT:    addi a3, sp, 12
; CHECK-NEXT:    sh a2, 12(sp)
; CHECK-NEXT:    vle8.v v9, (a3)
; CHECK-NEXT:    lbu a2, 1(a0)
; CHECK-NEXT:    lbu a3, 2(a0)
; CHECK-NEXT:    lbu a4, 3(a0)
; CHECK-NEXT:    lbu a5, 0(a0)
; CHECK-NEXT:    vse8.v v8, (a1)
; CHECK-NEXT:    slli a2, a2, 8
; CHECK-NEXT:    slli a3, a3, 16
; CHECK-NEXT:    slli a4, a4, 24
; CHECK-NEXT:    or a2, a2, a5
; CHECK-NEXT:    addi a5, a0, 2
; CHECK-NEXT:    or a3, a4, a3
; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT:    vle8.v v8, (a5)
; CHECK-NEXT:    or a2, a3, a2
; CHECK-NEXT:    sw a2, 8(sp)
; CHECK-NEXT:    addi a2, sp, 10
; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT:    vle8.v v10, (a2)
; CHECK-NEXT:    addi a2, sp, 8
; CHECK-NEXT:    vle8.v v11, (a2)
; CHECK-NEXT:    addi a1, a1, 2
; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT:    vse8.v v8, (a1)
; CHECK-NEXT:    addi a1, a0, 4
; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT:    vse8.v v9, (a1)
; CHECK-NEXT:    vse8.v v10, (a5)
; CHECK-NEXT:    vse8.v v11, (a0)
; CHECK-NEXT:    addi sp, sp, 16
; CHECK-NEXT:    .cfi_def_cfa_offset 0
; CHECK-NEXT:    ret
bb:
  %alloca = alloca { i8, i8, i16, i16 }, align 1
  store volatile i32 0, ptr null, align 4
  call void @llvm.memcpy.p0.p0.i64(ptr %alloca, ptr %arg, i64 6, i1 false)
  call void @llvm.memcpy.p0.p0.i64(ptr %arg1, ptr %arg, i64 6, i1 false)
  call void @llvm.memcpy.p0.p0.i64(ptr %arg, ptr %alloca, i64 6, i1 false)
  ret void
}