| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 |
| ; RUN: llc < %s -mtriple=riscv32 -mattr=+zve32x | FileCheck %s --check-prefixes=ZVL32 |
| ; RUN: llc < %s -mtriple=riscv32 -mattr=+zve32x,+zvl64b | FileCheck %s --check-prefix=ZVL64 |
| |
| ; We can't vectorize this currently with VLEN=32, due to RVVBitsPerBlock==64. |
| ; Make sure we don't crash. |
| |
| define i1 @test() { |
| ; ZVL32-LABEL: test: |
| ; ZVL32: # %bb.0: |
| ; ZVL32-NEXT: lw a0, 0(zero) |
| ; ZVL32-NEXT: lw a1, 4(zero) |
| ; ZVL32-NEXT: or a0, a0, a1 |
| ; ZVL32-NEXT: seqz a0, a0 |
| ; ZVL32-NEXT: ret |
| ; |
| ; ZVL64-LABEL: test: |
| ; ZVL64: # %bb.0: |
| ; ZVL64-NEXT: vsetivli zero, 8, e8, m1, ta, ma |
| ; ZVL64-NEXT: vle8.v v8, (zero) |
| ; ZVL64-NEXT: vmsne.vi v8, v8, 0 |
| ; ZVL64-NEXT: vcpop.m a0, v8 |
| ; ZVL64-NEXT: seqz a0, a0 |
| ; ZVL64-NEXT: ret |
| %1 = load i64, ptr null, align 8 |
| %2 = icmp eq i64 %1, 0 |
| ret i1 %2 |
| } |
