llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v,+zvbc < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVBC,RV32ZVBC64
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v,+zvbc < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVBC,RV64ZVBC64
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v,+experimental-zvbc32e < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVBC,RV32ZVBC32
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v,+experimental-zvbc32e < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVBC,RV64ZVBC32

define <vscale x 1 x i8> @clmulh_nxv1i8_vv(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv1i8_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v9
; RV32V-NEXT:    vzext.vf2 v9, v8
; RV32V-NEXT:    vand.vi v8, v10, 2
; RV32V-NEXT:    vand.vi v11, v10, 1
; RV32V-NEXT:    vmul.vv v8, v9, v8
; RV32V-NEXT:    vmul.vv v11, v9, v11
; RV32V-NEXT:    vand.vi v12, v10, 4
; RV32V-NEXT:    vand.vi v13, v10, 8
; RV32V-NEXT:    vmul.vv v12, v9, v12
; RV32V-NEXT:    vxor.vv v8, v11, v8
; RV32V-NEXT:    vand.vx v11, v10, a0
; RV32V-NEXT:    vmul.vv v13, v9, v13
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vmul.vv v11, v9, v11
; RV32V-NEXT:    vand.vx v12, v10, a0
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vxor.vv v8, v8, v13
; RV32V-NEXT:    vand.vx v13, v10, a0
; RV32V-NEXT:    vmul.vv v12, v9, v12
; RV32V-NEXT:    vxor.vv v8, v8, v11
; RV32V-NEXT:    vmul.vv v11, v9, v13
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v10, v10, a0
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vmul.vv v9, v9, v10
; RV32V-NEXT:    vxor.vv v8, v8, v11
; RV32V-NEXT:    vxor.vv v8, v8, v9
; RV32V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i8_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v9
; RV64V-NEXT:    vzext.vf2 v9, v8
; RV64V-NEXT:    vand.vi v8, v10, 2
; RV64V-NEXT:    vand.vi v11, v10, 1
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vmul.vv v11, v9, v11
; RV64V-NEXT:    vand.vi v12, v10, 4
; RV64V-NEXT:    vand.vi v13, v10, 8
; RV64V-NEXT:    vmul.vv v12, v9, v12
; RV64V-NEXT:    vxor.vv v8, v11, v8
; RV64V-NEXT:    vand.vx v11, v10, a0
; RV64V-NEXT:    vmul.vv v13, v9, v13
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vmul.vv v11, v9, v11
; RV64V-NEXT:    vand.vx v12, v10, a0
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vxor.vv v8, v8, v13
; RV64V-NEXT:    vand.vx v13, v10, a0
; RV64V-NEXT:    vmul.vv v12, v9, v12
; RV64V-NEXT:    vxor.vv v8, v8, v11
; RV64V-NEXT:    vmul.vv v11, v9, v13
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v10, v10, a0
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    vmul.vv v9, v9, v10
; RV64V-NEXT:    vxor.vv v8, v8, v11
; RV64V-NEXT:    vxor.vv v8, v8, v9
; RV64V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i8_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v10, v9
; RV32ZVBC64-NEXT:    vzext.vf8 v9, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v9, v10
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i8_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v10, v9
; RV64ZVBC64-NEXT:    vzext.vf8 v9, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v9, v10
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i8_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i8_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 1 x i8> %va to <vscale x 1 x i16>
  %vb.ext = zext <vscale x 1 x i8> %vb to <vscale x 1 x i16>
  %clmul = call <vscale x 1 x i16> @llvm.clmul.nxv1i16(<vscale x 1 x i16> %va.ext, <vscale x 1 x i16> %vb.ext)
  %res.ext = lshr <vscale x 1 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 1 x i16> %res.ext to <vscale x 1 x i8>
  ret <vscale x 1 x i8> %res
}

define <vscale x 1 x i8> @clmulh_nxv1i8_vx(<vscale x 1 x i8> %va, i8 %b) nounwind {
; RV32V-LABEL: clmulh_nxv1i8_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a0
; RV32V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v8
; RV32V-NEXT:    vzext.vf2 v8, v9
; RV32V-NEXT:    vand.vi v9, v8, 2
; RV32V-NEXT:    vand.vi v11, v8, 1
; RV32V-NEXT:    vmul.vv v9, v10, v9
; RV32V-NEXT:    vmul.vv v11, v10, v11
; RV32V-NEXT:    vand.vi v12, v8, 4
; RV32V-NEXT:    vand.vi v13, v8, 8
; RV32V-NEXT:    vmul.vv v12, v10, v12
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vxor.vv v9, v11, v9
; RV32V-NEXT:    vand.vx v11, v8, a0
; RV32V-NEXT:    vmul.vv v13, v10, v13
; RV32V-NEXT:    vxor.vv v9, v9, v12
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vmul.vv v11, v10, v11
; RV32V-NEXT:    vand.vx v12, v8, a0
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vxor.vv v9, v9, v13
; RV32V-NEXT:    vand.vx v13, v8, a0
; RV32V-NEXT:    vmul.vv v12, v10, v12
; RV32V-NEXT:    vxor.vv v9, v9, v11
; RV32V-NEXT:    vmul.vv v11, v10, v13
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vxor.vv v9, v9, v12
; RV32V-NEXT:    vmul.vv v8, v10, v8
; RV32V-NEXT:    vxor.vv v9, v9, v11
; RV32V-NEXT:    vxor.vv v8, v9, v8
; RV32V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i8_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
; RV64V-NEXT:    vmv.v.x v9, a0
; RV64V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    vzext.vf2 v8, v9
; RV64V-NEXT:    vand.vi v9, v8, 2
; RV64V-NEXT:    vand.vi v11, v8, 1
; RV64V-NEXT:    vmul.vv v9, v10, v9
; RV64V-NEXT:    vmul.vv v11, v10, v11
; RV64V-NEXT:    vand.vi v12, v8, 4
; RV64V-NEXT:    vand.vi v13, v8, 8
; RV64V-NEXT:    vmul.vv v12, v10, v12
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vxor.vv v9, v11, v9
; RV64V-NEXT:    vand.vx v11, v8, a0
; RV64V-NEXT:    vmul.vv v13, v10, v13
; RV64V-NEXT:    vxor.vv v9, v9, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vmul.vv v11, v10, v11
; RV64V-NEXT:    vand.vx v12, v8, a0
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vxor.vv v9, v9, v13
; RV64V-NEXT:    vand.vx v13, v8, a0
; RV64V-NEXT:    vmul.vv v12, v10, v12
; RV64V-NEXT:    vxor.vv v9, v9, v11
; RV64V-NEXT:    vmul.vv v11, v10, v13
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vxor.vv v9, v9, v12
; RV64V-NEXT:    vmul.vv v8, v10, v8
; RV64V-NEXT:    vxor.vv v9, v9, v11
; RV64V-NEXT:    vxor.vv v8, v9, v8
; RV64V-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i8_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v9, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v10, v8
; RV32ZVBC64-NEXT:    vzext.vf8 v8, v9
; RV32ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i8_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v9, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v10, v8
; RV64ZVBC64-NEXT:    vzext.vf8 v8, v9
; RV64ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i8_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i8_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
  %va.ext = zext <vscale x 1 x i8> %va to <vscale x 1 x i16>
  %vb.ext = zext <vscale x 1 x i8> %vb to <vscale x 1 x i16>
  %clmul = call <vscale x 1 x i16> @llvm.clmul.nxv1i16(<vscale x 1 x i16> %va.ext, <vscale x 1 x i16> %vb.ext)
  %res.ext = lshr <vscale x 1 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 1 x i16> %res.ext to <vscale x 1 x i8>
  ret <vscale x 1 x i8> %res
}

define <vscale x 2 x i8> @clmulh_nxv2i8_vv(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv2i8_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v9
; RV32V-NEXT:    vzext.vf2 v9, v8
; RV32V-NEXT:    vand.vi v8, v10, 2
; RV32V-NEXT:    vand.vi v11, v10, 1
; RV32V-NEXT:    vmul.vv v8, v9, v8
; RV32V-NEXT:    vmul.vv v11, v9, v11
; RV32V-NEXT:    vand.vi v12, v10, 4
; RV32V-NEXT:    vand.vi v13, v10, 8
; RV32V-NEXT:    vmul.vv v12, v9, v12
; RV32V-NEXT:    vxor.vv v8, v11, v8
; RV32V-NEXT:    vand.vx v11, v10, a0
; RV32V-NEXT:    vmul.vv v13, v9, v13
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vmul.vv v11, v9, v11
; RV32V-NEXT:    vand.vx v12, v10, a0
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vxor.vv v8, v8, v13
; RV32V-NEXT:    vand.vx v13, v10, a0
; RV32V-NEXT:    vmul.vv v12, v9, v12
; RV32V-NEXT:    vxor.vv v8, v8, v11
; RV32V-NEXT:    vmul.vv v11, v9, v13
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v10, v10, a0
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vmul.vv v9, v9, v10
; RV32V-NEXT:    vxor.vv v8, v8, v11
; RV32V-NEXT:    vxor.vv v8, v8, v9
; RV32V-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i8_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v9
; RV64V-NEXT:    vzext.vf2 v9, v8
; RV64V-NEXT:    vand.vi v8, v10, 2
; RV64V-NEXT:    vand.vi v11, v10, 1
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vmul.vv v11, v9, v11
; RV64V-NEXT:    vand.vi v12, v10, 4
; RV64V-NEXT:    vand.vi v13, v10, 8
; RV64V-NEXT:    vmul.vv v12, v9, v12
; RV64V-NEXT:    vxor.vv v8, v11, v8
; RV64V-NEXT:    vand.vx v11, v10, a0
; RV64V-NEXT:    vmul.vv v13, v9, v13
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vmul.vv v11, v9, v11
; RV64V-NEXT:    vand.vx v12, v10, a0
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vxor.vv v8, v8, v13
; RV64V-NEXT:    vand.vx v13, v10, a0
; RV64V-NEXT:    vmul.vv v12, v9, v12
; RV64V-NEXT:    vxor.vv v8, v8, v11
; RV64V-NEXT:    vmul.vv v11, v9, v13
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v10, v10, a0
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    vmul.vv v9, v9, v10
; RV64V-NEXT:    vxor.vv v8, v8, v11
; RV64V-NEXT:    vxor.vv v8, v8, v9
; RV64V-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i8_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v10, v9
; RV32ZVBC64-NEXT:    vzext.vf8 v12, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v12, v10
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v10, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i8_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v10, v9
; RV64ZVBC64-NEXT:    vzext.vf8 v12, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v12, v10
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v10, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i8_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i8_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 2 x i8> %va to <vscale x 2 x i16>
  %vb.ext = zext <vscale x 2 x i8> %vb to <vscale x 2 x i16>
  %clmul = call <vscale x 2 x i16> @llvm.clmul.nxv2i16(<vscale x 2 x i16> %va.ext, <vscale x 2 x i16> %vb.ext)
  %res.ext = lshr <vscale x 2 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 2 x i16> %res.ext to <vscale x 2 x i8>
  ret <vscale x 2 x i8> %res
}

define <vscale x 2 x i8> @clmulh_nxv2i8_vx(<vscale x 2 x i8> %va, i8 %b) nounwind {
; RV32V-LABEL: clmulh_nxv2i8_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a0
; RV32V-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v8
; RV32V-NEXT:    vzext.vf2 v8, v9
; RV32V-NEXT:    vand.vi v9, v8, 2
; RV32V-NEXT:    vand.vi v11, v8, 1
; RV32V-NEXT:    vmul.vv v9, v10, v9
; RV32V-NEXT:    vmul.vv v11, v10, v11
; RV32V-NEXT:    vand.vi v12, v8, 4
; RV32V-NEXT:    vand.vi v13, v8, 8
; RV32V-NEXT:    vmul.vv v12, v10, v12
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vxor.vv v9, v11, v9
; RV32V-NEXT:    vand.vx v11, v8, a0
; RV32V-NEXT:    vmul.vv v13, v10, v13
; RV32V-NEXT:    vxor.vv v9, v9, v12
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vmul.vv v11, v10, v11
; RV32V-NEXT:    vand.vx v12, v8, a0
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vxor.vv v9, v9, v13
; RV32V-NEXT:    vand.vx v13, v8, a0
; RV32V-NEXT:    vmul.vv v12, v10, v12
; RV32V-NEXT:    vxor.vv v9, v9, v11
; RV32V-NEXT:    vmul.vv v11, v10, v13
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vxor.vv v9, v9, v12
; RV32V-NEXT:    vmul.vv v8, v10, v8
; RV32V-NEXT:    vxor.vv v9, v9, v11
; RV32V-NEXT:    vxor.vv v8, v9, v8
; RV32V-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i8_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
; RV64V-NEXT:    vmv.v.x v9, a0
; RV64V-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    vzext.vf2 v8, v9
; RV64V-NEXT:    vand.vi v9, v8, 2
; RV64V-NEXT:    vand.vi v11, v8, 1
; RV64V-NEXT:    vmul.vv v9, v10, v9
; RV64V-NEXT:    vmul.vv v11, v10, v11
; RV64V-NEXT:    vand.vi v12, v8, 4
; RV64V-NEXT:    vand.vi v13, v8, 8
; RV64V-NEXT:    vmul.vv v12, v10, v12
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vxor.vv v9, v11, v9
; RV64V-NEXT:    vand.vx v11, v8, a0
; RV64V-NEXT:    vmul.vv v13, v10, v13
; RV64V-NEXT:    vxor.vv v9, v9, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vmul.vv v11, v10, v11
; RV64V-NEXT:    vand.vx v12, v8, a0
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vxor.vv v9, v9, v13
; RV64V-NEXT:    vand.vx v13, v8, a0
; RV64V-NEXT:    vmul.vv v12, v10, v12
; RV64V-NEXT:    vxor.vv v9, v9, v11
; RV64V-NEXT:    vmul.vv v11, v10, v13
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vxor.vv v9, v9, v12
; RV64V-NEXT:    vmul.vv v8, v10, v8
; RV64V-NEXT:    vxor.vv v9, v9, v11
; RV64V-NEXT:    vxor.vv v8, v9, v8
; RV64V-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i8_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v12, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v10, v8
; RV32ZVBC64-NEXT:    vzext.vf8 v8, v12
; RV32ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v10, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i8_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v12, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v10, v8
; RV64ZVBC64-NEXT:    vzext.vf8 v8, v12
; RV64ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v10, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i8_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i8_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
  %va.ext = zext <vscale x 2 x i8> %va to <vscale x 2 x i16>
  %vb.ext = zext <vscale x 2 x i8> %vb to <vscale x 2 x i16>
  %clmul = call <vscale x 2 x i16> @llvm.clmul.nxv2i16(<vscale x 2 x i16> %va.ext, <vscale x 2 x i16> %vb.ext)
  %res.ext = lshr <vscale x 2 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 2 x i16> %res.ext to <vscale x 2 x i8>
  ret <vscale x 2 x i8> %res
}

define <vscale x 4 x i8> @clmulh_nxv4i8_vv(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv4i8_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v9
; RV32V-NEXT:    vzext.vf2 v9, v8
; RV32V-NEXT:    vand.vi v8, v10, 2
; RV32V-NEXT:    vand.vi v11, v10, 1
; RV32V-NEXT:    vmul.vv v8, v9, v8
; RV32V-NEXT:    vmul.vv v11, v9, v11
; RV32V-NEXT:    vand.vi v12, v10, 4
; RV32V-NEXT:    vand.vi v13, v10, 8
; RV32V-NEXT:    vmul.vv v12, v9, v12
; RV32V-NEXT:    vxor.vv v8, v11, v8
; RV32V-NEXT:    vand.vx v11, v10, a0
; RV32V-NEXT:    vmul.vv v13, v9, v13
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v12, v10, a0
; RV32V-NEXT:    vmul.vv v11, v9, v11
; RV32V-NEXT:    vxor.vv v8, v8, v13
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v13, v10, a0
; RV32V-NEXT:    vmul.vv v12, v9, v12
; RV32V-NEXT:    vxor.vv v8, v8, v11
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vmul.vv v11, v9, v13
; RV32V-NEXT:    vand.vx v10, v10, a0
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vmul.vv v9, v9, v10
; RV32V-NEXT:    vxor.vv v8, v8, v11
; RV32V-NEXT:    vxor.vv v8, v8, v9
; RV32V-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i8_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v9
; RV64V-NEXT:    vzext.vf2 v9, v8
; RV64V-NEXT:    vand.vi v8, v10, 2
; RV64V-NEXT:    vand.vi v11, v10, 1
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vmul.vv v11, v9, v11
; RV64V-NEXT:    vand.vi v12, v10, 4
; RV64V-NEXT:    vand.vi v13, v10, 8
; RV64V-NEXT:    vmul.vv v12, v9, v12
; RV64V-NEXT:    vxor.vv v8, v11, v8
; RV64V-NEXT:    vand.vx v11, v10, a0
; RV64V-NEXT:    vmul.vv v13, v9, v13
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v12, v10, a0
; RV64V-NEXT:    vmul.vv v11, v9, v11
; RV64V-NEXT:    vxor.vv v8, v8, v13
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v13, v10, a0
; RV64V-NEXT:    vmul.vv v12, v9, v12
; RV64V-NEXT:    vxor.vv v8, v8, v11
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vmul.vv v11, v9, v13
; RV64V-NEXT:    vand.vx v10, v10, a0
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    vmul.vv v9, v9, v10
; RV64V-NEXT:    vxor.vv v8, v8, v11
; RV64V-NEXT:    vxor.vv v8, v8, v9
; RV64V-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i8_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v12, v9
; RV32ZVBC64-NEXT:    vzext.vf8 v16, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v16, v12
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v12, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i8_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v12, v9
; RV64ZVBC64-NEXT:    vzext.vf8 v16, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v16, v12
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v12, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i8_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i8_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 4 x i8> %va to <vscale x 4 x i16>
  %vb.ext = zext <vscale x 4 x i8> %vb to <vscale x 4 x i16>
  %clmul = call <vscale x 4 x i16> @llvm.clmul.nxv4i16(<vscale x 4 x i16> %va.ext, <vscale x 4 x i16> %vb.ext)
  %res.ext = lshr <vscale x 4 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 4 x i16> %res.ext to <vscale x 4 x i8>
  ret <vscale x 4 x i8> %res
}

define <vscale x 4 x i8> @clmulh_nxv4i8_vx(<vscale x 4 x i8> %va, i8 %b) nounwind {
; RV32V-LABEL: clmulh_nxv4i8_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a0
; RV32V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v8
; RV32V-NEXT:    vzext.vf2 v8, v9
; RV32V-NEXT:    vand.vi v9, v8, 2
; RV32V-NEXT:    vand.vi v11, v8, 1
; RV32V-NEXT:    vmul.vv v9, v10, v9
; RV32V-NEXT:    vmul.vv v11, v10, v11
; RV32V-NEXT:    vand.vi v12, v8, 4
; RV32V-NEXT:    vand.vi v13, v8, 8
; RV32V-NEXT:    vmul.vv v12, v10, v12
; RV32V-NEXT:    vxor.vv v9, v11, v9
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vand.vx v11, v8, a0
; RV32V-NEXT:    vmul.vv v13, v10, v13
; RV32V-NEXT:    vxor.vv v9, v9, v12
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v12, v8, a0
; RV32V-NEXT:    vmul.vv v11, v10, v11
; RV32V-NEXT:    vxor.vv v9, v9, v13
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v13, v8, a0
; RV32V-NEXT:    vmul.vv v12, v10, v12
; RV32V-NEXT:    vxor.vv v9, v9, v11
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vmul.vv v11, v10, v13
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vxor.vv v9, v9, v12
; RV32V-NEXT:    vmul.vv v8, v10, v8
; RV32V-NEXT:    vxor.vv v9, v9, v11
; RV32V-NEXT:    vxor.vv v8, v9, v8
; RV32V-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i8_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
; RV64V-NEXT:    vmv.v.x v9, a0
; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    vzext.vf2 v8, v9
; RV64V-NEXT:    vand.vi v9, v8, 2
; RV64V-NEXT:    vand.vi v11, v8, 1
; RV64V-NEXT:    vmul.vv v9, v10, v9
; RV64V-NEXT:    vmul.vv v11, v10, v11
; RV64V-NEXT:    vand.vi v12, v8, 4
; RV64V-NEXT:    vand.vi v13, v8, 8
; RV64V-NEXT:    vmul.vv v12, v10, v12
; RV64V-NEXT:    vxor.vv v9, v11, v9
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vand.vx v11, v8, a0
; RV64V-NEXT:    vmul.vv v13, v10, v13
; RV64V-NEXT:    vxor.vv v9, v9, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v12, v8, a0
; RV64V-NEXT:    vmul.vv v11, v10, v11
; RV64V-NEXT:    vxor.vv v9, v9, v13
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v13, v8, a0
; RV64V-NEXT:    vmul.vv v12, v10, v12
; RV64V-NEXT:    vxor.vv v9, v9, v11
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vmul.vv v11, v10, v13
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vxor.vv v9, v9, v12
; RV64V-NEXT:    vmul.vv v8, v10, v8
; RV64V-NEXT:    vxor.vv v9, v9, v11
; RV64V-NEXT:    vxor.vv v8, v9, v8
; RV64V-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i8_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v16, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v12, v8
; RV32ZVBC64-NEXT:    vzext.vf8 v8, v16
; RV32ZVBC64-NEXT:    vclmul.vv v8, v12, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v12, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i8_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v12, v8
; RV64ZVBC64-NEXT:    vzext.vf8 v8, v16
; RV64ZVBC64-NEXT:    vclmul.vv v8, v12, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v12, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i8_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i8_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
  %va.ext = zext <vscale x 4 x i8> %va to <vscale x 4 x i16>
  %vb.ext = zext <vscale x 4 x i8> %vb to <vscale x 4 x i16>
  %clmul = call <vscale x 4 x i16> @llvm.clmul.nxv4i16(<vscale x 4 x i16> %va.ext, <vscale x 4 x i16> %vb.ext)
  %res.ext = lshr <vscale x 4 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 4 x i16> %res.ext to <vscale x 4 x i8>
  ret <vscale x 4 x i8> %res
}

define <vscale x 8 x i8> @clmulh_nxv8i8_vv(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv8i8_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v8
; RV32V-NEXT:    vzext.vf2 v12, v9
; RV32V-NEXT:    vand.vi v8, v12, 2
; RV32V-NEXT:    vand.vi v14, v12, 1
; RV32V-NEXT:    vmul.vv v8, v10, v8
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    vxor.vv v8, v14, v8
; RV32V-NEXT:    vand.vi v14, v12, 4
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    vand.vi v16, v12, 8
; RV32V-NEXT:    vmul.vv v16, v10, v16
; RV32V-NEXT:    vxor.vv v8, v8, v14
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vand.vx v14, v12, a0
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v16, v12, a0
; RV32V-NEXT:    vmul.vv v16, v10, v16
; RV32V-NEXT:    vxor.vv v8, v8, v14
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v14, v12, a0
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v12, v12, a0
; RV32V-NEXT:    vmul.vv v10, v10, v12
; RV32V-NEXT:    vxor.vv v8, v8, v14
; RV32V-NEXT:    vxor.vv v10, v8, v10
; RV32V-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v10, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i8_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    vzext.vf2 v12, v9
; RV64V-NEXT:    vand.vi v8, v12, 2
; RV64V-NEXT:    vand.vi v14, v12, 1
; RV64V-NEXT:    vmul.vv v8, v10, v8
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    vxor.vv v8, v14, v8
; RV64V-NEXT:    vand.vi v14, v12, 4
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    vand.vi v16, v12, 8
; RV64V-NEXT:    vmul.vv v16, v10, v16
; RV64V-NEXT:    vxor.vv v8, v8, v14
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vand.vx v14, v12, a0
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v16, v12, a0
; RV64V-NEXT:    vmul.vv v16, v10, v16
; RV64V-NEXT:    vxor.vv v8, v8, v14
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v14, v12, a0
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v12, v12, a0
; RV64V-NEXT:    vmul.vv v10, v10, v12
; RV64V-NEXT:    vxor.vv v8, v8, v14
; RV64V-NEXT:    vxor.vv v10, v8, v10
; RV64V-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v10, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i8_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v16, v9
; RV32ZVBC64-NEXT:    vzext.vf8 v24, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v24, v16
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v10, v16, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v10, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i8_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v16, v9
; RV64ZVBC64-NEXT:    vzext.vf8 v24, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v24, v16
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v10, v16, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v10, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i8_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i8_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 8 x i8> %va to <vscale x 8 x i16>
  %vb.ext = zext <vscale x 8 x i8> %vb to <vscale x 8 x i16>
  %clmul = call <vscale x 8 x i16> @llvm.clmul.nxv8i16(<vscale x 8 x i16> %va.ext, <vscale x 8 x i16> %vb.ext)
  %res.ext = lshr <vscale x 8 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 8 x i16> %res.ext to <vscale x 8 x i8>
  ret <vscale x 8 x i8> %res
}

define <vscale x 8 x i8> @clmulh_nxv8i8_vx(<vscale x 8 x i8> %va, i8 %b) nounwind {
; RV32V-LABEL: clmulh_nxv8i8_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v12, a0
; RV32V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v8
; RV32V-NEXT:    vzext.vf2 v8, v12
; RV32V-NEXT:    vand.vi v12, v8, 2
; RV32V-NEXT:    vand.vi v14, v8, 1
; RV32V-NEXT:    vmul.vv v12, v10, v12
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    vxor.vv v12, v14, v12
; RV32V-NEXT:    vand.vi v14, v8, 4
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    vand.vi v16, v8, 8
; RV32V-NEXT:    vmul.vv v16, v10, v16
; RV32V-NEXT:    vxor.vv v12, v12, v14
; RV32V-NEXT:    vxor.vv v12, v12, v16
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vand.vx v14, v8, a0
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v16, v8, a0
; RV32V-NEXT:    vmul.vv v16, v10, v16
; RV32V-NEXT:    vxor.vv v12, v12, v14
; RV32V-NEXT:    vxor.vv v12, v12, v16
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v14, v8, a0
; RV32V-NEXT:    vmul.vv v14, v10, v14
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vmul.vv v8, v10, v8
; RV32V-NEXT:    vxor.vv v10, v12, v14
; RV32V-NEXT:    vxor.vv v10, v10, v8
; RV32V-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v10, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i8_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
; RV64V-NEXT:    vmv.v.x v12, a0
; RV64V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    vzext.vf2 v8, v12
; RV64V-NEXT:    vand.vi v12, v8, 2
; RV64V-NEXT:    vand.vi v14, v8, 1
; RV64V-NEXT:    vmul.vv v12, v10, v12
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    vxor.vv v12, v14, v12
; RV64V-NEXT:    vand.vi v14, v8, 4
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    vand.vi v16, v8, 8
; RV64V-NEXT:    vmul.vv v16, v10, v16
; RV64V-NEXT:    vxor.vv v12, v12, v14
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vand.vx v14, v8, a0
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v16, v8, a0
; RV64V-NEXT:    vmul.vv v16, v10, v16
; RV64V-NEXT:    vxor.vv v12, v12, v14
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v14, v8, a0
; RV64V-NEXT:    vmul.vv v14, v10, v14
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vmul.vv v8, v10, v8
; RV64V-NEXT:    vxor.vv v10, v12, v14
; RV64V-NEXT:    vxor.vv v10, v10, v8
; RV64V-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v10, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i8_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v24, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf8 v16, v8
; RV32ZVBC64-NEXT:    vzext.vf8 v8, v24
; RV32ZVBC64-NEXT:    vclmul.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v10, v16, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v10, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i8_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v24, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf8 v16, v8
; RV64ZVBC64-NEXT:    vzext.vf8 v8, v24
; RV64ZVBC64-NEXT:    vclmul.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v10, v16, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v10, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i8_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i8_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
  %va.ext = zext <vscale x 8 x i8> %va to <vscale x 8 x i16>
  %vb.ext = zext <vscale x 8 x i8> %vb to <vscale x 8 x i16>
  %clmul = call <vscale x 8 x i16> @llvm.clmul.nxv8i16(<vscale x 8 x i16> %va.ext, <vscale x 8 x i16> %vb.ext)
  %res.ext = lshr <vscale x 8 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 8 x i16> %res.ext to <vscale x 8 x i8>
  ret <vscale x 8 x i8> %res
}

define <vscale x 16 x i8> @clmulh_nxv16i8_vv(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv16i8_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; RV32V-NEXT:    vzext.vf2 v12, v8
; RV32V-NEXT:    vzext.vf2 v16, v10
; RV32V-NEXT:    vand.vi v8, v16, 2
; RV32V-NEXT:    vand.vi v20, v16, 1
; RV32V-NEXT:    vmul.vv v8, v12, v8
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    vxor.vv v8, v20, v8
; RV32V-NEXT:    vand.vi v20, v16, 4
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    vand.vi v24, v16, 8
; RV32V-NEXT:    vmul.vv v24, v12, v24
; RV32V-NEXT:    vxor.vv v8, v8, v20
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    vand.vx v20, v16, a0
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v24, v16, a0
; RV32V-NEXT:    vmul.vv v24, v12, v24
; RV32V-NEXT:    vxor.vv v8, v8, v20
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v20, v16, a0
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vmul.vv v12, v12, v16
; RV32V-NEXT:    vxor.vv v8, v8, v20
; RV32V-NEXT:    vxor.vv v12, v8, v12
; RV32V-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v12, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv16i8_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; RV64V-NEXT:    vzext.vf2 v12, v8
; RV64V-NEXT:    vzext.vf2 v16, v10
; RV64V-NEXT:    vand.vi v8, v16, 2
; RV64V-NEXT:    vand.vi v20, v16, 1
; RV64V-NEXT:    vmul.vv v8, v12, v8
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    vxor.vv v8, v20, v8
; RV64V-NEXT:    vand.vi v20, v16, 4
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    vand.vi v24, v16, 8
; RV64V-NEXT:    vmul.vv v24, v12, v24
; RV64V-NEXT:    vxor.vv v8, v8, v20
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vand.vx v20, v16, a0
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v24, v16, a0
; RV64V-NEXT:    vmul.vv v24, v12, v24
; RV64V-NEXT:    vxor.vv v8, v8, v20
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v20, v16, a0
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vmul.vv v12, v12, v16
; RV64V-NEXT:    vxor.vv v8, v8, v20
; RV64V-NEXT:    vxor.vv v12, v8, v12
; RV64V-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v12, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv16i8_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    li a0, 16
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v16, v10
; RV32ZVBC64-NEXT:    vand.vi v8, v16, 2
; RV32ZVBC64-NEXT:    vand.vi v20, v16, 1
; RV32ZVBC64-NEXT:    vmul.vv v8, v12, v8
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    vxor.vv v8, v20, v8
; RV32ZVBC64-NEXT:    vand.vi v20, v16, 4
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v20
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vand.vx v20, v16, a0
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a0
; RV32ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v20
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    li a0, 64
; RV32ZVBC64-NEXT:    vand.vx v20, v16, a0
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    li a0, 128
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vmul.vv v12, v12, v16
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v20
; RV32ZVBC64-NEXT:    vxor.vv v12, v8, v12
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v12, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv16i8_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    li a0, 16
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v16, v10
; RV64ZVBC64-NEXT:    vand.vi v8, v16, 2
; RV64ZVBC64-NEXT:    vand.vi v20, v16, 1
; RV64ZVBC64-NEXT:    vmul.vv v8, v12, v8
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    vxor.vv v8, v20, v8
; RV64ZVBC64-NEXT:    vand.vi v20, v16, 4
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v20
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vand.vx v20, v16, a0
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a0
; RV64ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v20
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    li a0, 64
; RV64ZVBC64-NEXT:    vand.vx v20, v16, a0
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    li a0, 128
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vmul.vv v12, v12, v16
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v20
; RV64ZVBC64-NEXT:    vxor.vv v12, v8, v12
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v12, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv16i8_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v10
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv16i8_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v10
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 16 x i8> %va to <vscale x 16 x i16>
  %vb.ext = zext <vscale x 16 x i8> %vb to <vscale x 16 x i16>
  %clmul = call <vscale x 16 x i16> @llvm.clmul.nxv16i16(<vscale x 16 x i16> %va.ext, <vscale x 16 x i16> %vb.ext)
  %res.ext = lshr <vscale x 16 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 16 x i16> %res.ext to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %res
}

define <vscale x 16 x i8> @clmulh_nxv16i8_vx(<vscale x 16 x i8> %va, i8 %b) nounwind {
; RV32V-LABEL: clmulh_nxv16i8_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32V-NEXT:    vzext.vf2 v12, v8
; RV32V-NEXT:    vzext.vf2 v8, v16
; RV32V-NEXT:    vand.vi v16, v8, 2
; RV32V-NEXT:    vand.vi v20, v8, 1
; RV32V-NEXT:    vmul.vv v16, v12, v16
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    vxor.vv v16, v20, v16
; RV32V-NEXT:    vand.vi v20, v8, 4
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    vand.vi v24, v8, 8
; RV32V-NEXT:    vmul.vv v24, v12, v24
; RV32V-NEXT:    vxor.vv v16, v16, v20
; RV32V-NEXT:    vxor.vv v16, v16, v24
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vand.vx v20, v8, a0
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v24, v8, a0
; RV32V-NEXT:    vmul.vv v24, v12, v24
; RV32V-NEXT:    vxor.vv v16, v16, v20
; RV32V-NEXT:    vxor.vv v16, v16, v24
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v20, v8, a0
; RV32V-NEXT:    vmul.vv v20, v12, v20
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vmul.vv v8, v12, v8
; RV32V-NEXT:    vxor.vv v12, v16, v20
; RV32V-NEXT:    vxor.vv v12, v12, v8
; RV32V-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v12, 8
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv16i8_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
; RV64V-NEXT:    vmv.v.x v16, a0
; RV64V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64V-NEXT:    vzext.vf2 v12, v8
; RV64V-NEXT:    vzext.vf2 v8, v16
; RV64V-NEXT:    vand.vi v16, v8, 2
; RV64V-NEXT:    vand.vi v20, v8, 1
; RV64V-NEXT:    vmul.vv v16, v12, v16
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    vxor.vv v16, v20, v16
; RV64V-NEXT:    vand.vi v20, v8, 4
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    vand.vi v24, v8, 8
; RV64V-NEXT:    vmul.vv v24, v12, v24
; RV64V-NEXT:    vxor.vv v16, v16, v20
; RV64V-NEXT:    vxor.vv v16, v16, v24
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vand.vx v20, v8, a0
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v24, v8, a0
; RV64V-NEXT:    vmul.vv v24, v12, v24
; RV64V-NEXT:    vxor.vv v16, v16, v20
; RV64V-NEXT:    vxor.vv v16, v16, v24
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v20, v8, a0
; RV64V-NEXT:    vmul.vv v20, v12, v20
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vmul.vv v8, v12, v8
; RV64V-NEXT:    vxor.vv v12, v16, v20
; RV64V-NEXT:    vxor.vv v12, v12, v8
; RV64V-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v12, 8
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv16i8_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v16, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v16
; RV32ZVBC64-NEXT:    vand.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vi v20, v8, 1
; RV32ZVBC64-NEXT:    vmul.vv v16, v12, v16
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    vxor.vv v16, v20, v16
; RV32ZVBC64-NEXT:    vand.vi v20, v8, 4
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    vand.vi v24, v8, 8
; RV32ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v20
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    li a0, 16
; RV32ZVBC64-NEXT:    vand.vx v20, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vand.vx v24, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v20
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    li a0, 64
; RV32ZVBC64-NEXT:    vand.vx v20, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV32ZVBC64-NEXT:    li a0, 128
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v8, v12, v8
; RV32ZVBC64-NEXT:    vxor.vv v12, v16, v20
; RV32ZVBC64-NEXT:    vxor.vv v12, v12, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v12, 8
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv16i8_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v16
; RV64ZVBC64-NEXT:    vand.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vi v20, v8, 1
; RV64ZVBC64-NEXT:    vmul.vv v16, v12, v16
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    vxor.vv v16, v20, v16
; RV64ZVBC64-NEXT:    vand.vi v20, v8, 4
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    vand.vi v24, v8, 8
; RV64ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV64ZVBC64-NEXT:    vxor.vv v16, v16, v20
; RV64ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    li a0, 16
; RV64ZVBC64-NEXT:    vand.vx v20, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vand.vx v24, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v24, v12, v24
; RV64ZVBC64-NEXT:    vxor.vv v16, v16, v20
; RV64ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    li a0, 64
; RV64ZVBC64-NEXT:    vand.vx v20, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v20, v12, v20
; RV64ZVBC64-NEXT:    li a0, 128
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v8, v12, v8
; RV64ZVBC64-NEXT:    vxor.vv v12, v16, v20
; RV64ZVBC64-NEXT:    vxor.vv v12, v12, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v12, 8
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv16i8_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv16i8_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
  %va.ext = zext <vscale x 16 x i8> %va to <vscale x 16 x i16>
  %vb.ext = zext <vscale x 16 x i8> %vb to <vscale x 16 x i16>
  %clmul = call <vscale x 16 x i16> @llvm.clmul.nxv16i16(<vscale x 16 x i16> %va.ext, <vscale x 16 x i16> %vb.ext)
  %res.ext = lshr <vscale x 16 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 16 x i16> %res.ext to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %res
}

define <vscale x 32 x i8> @clmulh_nxv32i8_vv(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv32i8_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV32V-NEXT:    vzext.vf2 v16, v8
; RV32V-NEXT:    vzext.vf2 v24, v12
; RV32V-NEXT:    vand.vi v8, v24, 2
; RV32V-NEXT:    vand.vi v0, v24, 1
; RV32V-NEXT:    vmul.vv v8, v16, v8
; RV32V-NEXT:    vmul.vv v0, v16, v0
; RV32V-NEXT:    vxor.vv v8, v0, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v0, v24, 4
; RV32V-NEXT:    vmul.vv v8, v16, v0
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v8, v24, 8
; RV32V-NEXT:    vmul.vv v8, v16, v8
; RV32V-NEXT:    addi a1, sp, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v8
; RV32V-NEXT:    addi a1, sp, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v0, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v24, a0
; RV32V-NEXT:    vmul.vv v8, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v8, v24, a0
; RV32V-NEXT:    vmul.vv v8, v16, v8
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v8
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v0, v8
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v0, v24, a0
; RV32V-NEXT:    vmul.vv v0, v16, v0
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vmul.vv v16, v16, v24
; RV32V-NEXT:    vxor.vv v8, v8, v0
; RV32V-NEXT:    vxor.vv v16, v8, v16
; RV32V-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v16, 8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv32i8_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV64V-NEXT:    vzext.vf2 v16, v8
; RV64V-NEXT:    vzext.vf2 v24, v12
; RV64V-NEXT:    vand.vi v8, v24, 2
; RV64V-NEXT:    vand.vi v0, v24, 1
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    vmul.vv v0, v16, v0
; RV64V-NEXT:    vxor.vv v8, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v0, v24, 4
; RV64V-NEXT:    vmul.vv v8, v16, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v8, v24, 8
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    addi a1, sp, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v8
; RV64V-NEXT:    addi a1, sp, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v24, a0
; RV64V-NEXT:    vmul.vv v8, v16, v0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v8, v24, a0
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    addi a0, sp, 16
; RV64V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v8
; RV64V-NEXT:    addi a0, sp, 16
; RV64V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v0, v8
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v0, v24, a0
; RV64V-NEXT:    vmul.vv v0, v16, v0
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vmul.vv v16, v16, v24
; RV64V-NEXT:    vxor.vv v8, v8, v0
; RV64V-NEXT:    vxor.vv v16, v8, v16
; RV64V-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v16, 8
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv32i8_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    sub sp, sp, a0
; RV32ZVBC64-NEXT:    li a0, 16
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v24, v12
; RV32ZVBC64-NEXT:    vand.vi v8, v24, 2
; RV32ZVBC64-NEXT:    vand.vi v0, v24, 1
; RV32ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV32ZVBC64-NEXT:    vxor.vv v8, v0, v8
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v0, v24, 4
; RV32ZVBC64-NEXT:    vmul.vv v8, v16, v0
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v8, v24, 8
; RV32ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV32ZVBC64-NEXT:    addi a1, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV32ZVBC64-NEXT:    addi a1, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v0, v8
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v24, a0
; RV32ZVBC64-NEXT:    vmul.vv v8, v16, v0
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vand.vx v8, v24, a0
; RV32ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV32ZVBC64-NEXT:    addi a0, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV32ZVBC64-NEXT:    addi a0, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v0, v8
; RV32ZVBC64-NEXT:    li a0, 64
; RV32ZVBC64-NEXT:    vand.vx v0, v24, a0
; RV32ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV32ZVBC64-NEXT:    li a0, 128
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vmul.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV32ZVBC64-NEXT:    vxor.vv v16, v8, v16
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v16, 8
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv32i8_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    sub sp, sp, a0
; RV64ZVBC64-NEXT:    li a0, 16
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v24, v12
; RV64ZVBC64-NEXT:    vand.vi v8, v24, 2
; RV64ZVBC64-NEXT:    vand.vi v0, v24, 1
; RV64ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v0, v8
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v0, v24, 4
; RV64ZVBC64-NEXT:    vmul.vv v8, v16, v0
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v8, v24, 8
; RV64ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV64ZVBC64-NEXT:    addi a1, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV64ZVBC64-NEXT:    addi a1, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v8, v0, v8
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v24, a0
; RV64ZVBC64-NEXT:    vmul.vv v8, v16, v0
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vand.vx v8, v24, a0
; RV64ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV64ZVBC64-NEXT:    addi a0, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV64ZVBC64-NEXT:    addi a0, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v8, v0, v8
; RV64ZVBC64-NEXT:    li a0, 64
; RV64ZVBC64-NEXT:    vand.vx v0, v24, a0
; RV64ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV64ZVBC64-NEXT:    li a0, 128
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    vxor.vv v16, v8, v16
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v16, 8
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv32i8_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v12
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv32i8_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v12
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 32 x i8> %va to <vscale x 32 x i16>
  %vb.ext = zext <vscale x 32 x i8> %vb to <vscale x 32 x i16>
  %clmul = call <vscale x 32 x i16> @llvm.clmul.nxv32i16(<vscale x 32 x i16> %va.ext, <vscale x 32 x i16> %vb.ext)
  %res.ext = lshr <vscale x 32 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 32 x i16> %res.ext to <vscale x 32 x i8>
  ret <vscale x 32 x i8> %res
}

define <vscale x 32 x i8> @clmulh_nxv32i8_vx(<vscale x 32 x i8> %va, i8 %b) nounwind {
; RV32V-LABEL: clmulh_nxv32i8_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a0
; RV32V-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
; RV32V-NEXT:    vzext.vf2 v16, v8
; RV32V-NEXT:    vzext.vf2 v8, v24
; RV32V-NEXT:    vand.vi v24, v8, 2
; RV32V-NEXT:    vand.vi v0, v8, 1
; RV32V-NEXT:    vmul.vv v24, v16, v24
; RV32V-NEXT:    vmul.vv v0, v16, v0
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v0, v8, 4
; RV32V-NEXT:    vmul.vv v24, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v24, v8, 8
; RV32V-NEXT:    vmul.vv v24, v16, v24
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a0, 16
; RV32V-NEXT:    vand.vx v0, v8, a0
; RV32V-NEXT:    vmul.vv v24, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vand.vx v24, v8, a0
; RV32V-NEXT:    vmul.vv v24, v16, v24
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    li a0, 64
; RV32V-NEXT:    vand.vx v0, v8, a0
; RV32V-NEXT:    vmul.vv v0, v16, v0
; RV32V-NEXT:    li a0, 128
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vmul.vv v8, v16, v8
; RV32V-NEXT:    vxor.vv v16, v24, v0
; RV32V-NEXT:    vxor.vv v16, v16, v8
; RV32V-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v16, 8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv32i8_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
; RV64V-NEXT:    vmv.v.x v24, a0
; RV64V-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
; RV64V-NEXT:    vzext.vf2 v16, v8
; RV64V-NEXT:    vzext.vf2 v8, v24
; RV64V-NEXT:    vand.vi v24, v8, 2
; RV64V-NEXT:    vand.vi v0, v8, 1
; RV64V-NEXT:    vmul.vv v24, v16, v24
; RV64V-NEXT:    vmul.vv v0, v16, v0
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v0, v8, 4
; RV64V-NEXT:    vmul.vv v24, v16, v0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v24, v8, 8
; RV64V-NEXT:    vmul.vv v24, v16, v24
; RV64V-NEXT:    addi a0, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a0, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a0, 16
; RV64V-NEXT:    vand.vx v0, v8, a0
; RV64V-NEXT:    vmul.vv v24, v16, v0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vand.vx v24, v8, a0
; RV64V-NEXT:    vmul.vv v24, v16, v24
; RV64V-NEXT:    addi a0, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a0, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    li a0, 64
; RV64V-NEXT:    vand.vx v0, v8, a0
; RV64V-NEXT:    vmul.vv v0, v16, v0
; RV64V-NEXT:    li a0, 128
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    vxor.vv v16, v24, v0
; RV64V-NEXT:    vxor.vv v16, v16, v8
; RV64V-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v16, 8
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv32i8_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    sub sp, sp, a1
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v24, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v24
; RV32ZVBC64-NEXT:    vand.vi v24, v8, 2
; RV32ZVBC64-NEXT:    vand.vi v0, v8, 1
; RV32ZVBC64-NEXT:    vmul.vv v24, v16, v24
; RV32ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v0, v8, 4
; RV32ZVBC64-NEXT:    vmul.vv v24, v16, v0
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v24, v8, 8
; RV32ZVBC64-NEXT:    vmul.vv v24, v16, v24
; RV32ZVBC64-NEXT:    addi a0, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a0, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a0, 16
; RV32ZVBC64-NEXT:    vand.vx v0, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v24, v16, v0
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vand.vx v24, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v24, v16, v24
; RV32ZVBC64-NEXT:    addi a0, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a0, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    li a0, 64
; RV32ZVBC64-NEXT:    vand.vx v0, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV32ZVBC64-NEXT:    li a0, 128
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v16, 8
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv32i8_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    sub sp, sp, a1
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v24, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v24
; RV64ZVBC64-NEXT:    vand.vi v24, v8, 2
; RV64ZVBC64-NEXT:    vand.vi v0, v8, 1
; RV64ZVBC64-NEXT:    vmul.vv v24, v16, v24
; RV64ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v0, v8, 4
; RV64ZVBC64-NEXT:    vmul.vv v24, v16, v0
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v24, v8, 8
; RV64ZVBC64-NEXT:    vmul.vv v24, v16, v24
; RV64ZVBC64-NEXT:    addi a0, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a0, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a0, 16
; RV64ZVBC64-NEXT:    vand.vx v0, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v24, v16, v0
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vand.vx v24, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v24, v16, v24
; RV64ZVBC64-NEXT:    addi a0, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a0, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    li a0, 64
; RV64ZVBC64-NEXT:    vand.vx v0, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v0, v16, v0
; RV64ZVBC64-NEXT:    li a0, 128
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV64ZVBC64-NEXT:    vxor.vv v16, v16, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v16, 8
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv32i8_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv32i8_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
  %va.ext = zext <vscale x 32 x i8> %va to <vscale x 32 x i16>
  %vb.ext = zext <vscale x 32 x i8> %vb to <vscale x 32 x i16>
  %clmul = call <vscale x 32 x i16> @llvm.clmul.nxv32i16(<vscale x 32 x i16> %va.ext, <vscale x 32 x i16> %vb.ext)
  %res.ext = lshr <vscale x 32 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 32 x i16> %res.ext to <vscale x 32 x i8>
  ret <vscale x 32 x i8> %res
}

define <vscale x 64 x i8> @clmulh_nxv64i8_vv(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv64i8_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    li a0, 51
; RV32V-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV32V-NEXT:    vsll.vi v24, v8, 4
; RV32V-NEXT:    vsrl.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vsrl.vi v24, v8, 2
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 1
; RV32V-NEXT:    li a1, 85
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsll.vi v24, v16, 4
; RV32V-NEXT:    vsrl.vi v16, v16, 4
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsrl.vi v24, v16, 2
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 1
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vadd.vv v16, v16, v16
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vand.vi v24, v16, 2
; RV32V-NEXT:    vand.vi v0, v16, 1
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v0, v16, 4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v24, v16, 8
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a2, 16
; RV32V-NEXT:    vand.vx v0, v16, a2
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a2, 32
; RV32V-NEXT:    vand.vx v24, v16, a2
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    li a2, 64
; RV32V-NEXT:    vand.vx v0, v16, a2
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    li a2, 128
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v16, v24, v0
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsll.vi v16, v16, 4
; RV32V-NEXT:    vsrl.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv64i8_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    li a0, 51
; RV64V-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV64V-NEXT:    vsll.vi v24, v8, 4
; RV64V-NEXT:    vsrl.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    vsrl.vi v24, v8, 2
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v8, 1
; RV64V-NEXT:    li a1, 85
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsll.vi v24, v16, 4
; RV64V-NEXT:    vsrl.vi v16, v16, 4
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsrl.vi v24, v16, 2
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsll.vi v16, v16, 2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 1
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vadd.vv v16, v16, v16
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vi v24, v16, 2
; RV64V-NEXT:    vand.vi v0, v16, 1
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v0, v16, 4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v24, v16, 8
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a2, 16
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a2, 32
; RV64V-NEXT:    vand.vx v24, v16, a2
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    li a2, 64
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    li a2, 128
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    vxor.vv v16, v24, v0
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vsll.vi v16, v16, 4
; RV64V-NEXT:    vsrl.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv64i8_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    sub sp, sp, a0
; RV32ZVBC64-NEXT:    li a0, 51
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV32ZVBC64-NEXT:    vsll.vi v24, v8, 4
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV32ZVBC64-NEXT:    li a1, 85
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsll.vi v24, v16, 4
; RV32ZVBC64-NEXT:    vsrl.vi v16, v16, 4
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a2, 16
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a2, 32
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    li a2, 64
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    li a2, 128
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv64i8_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    sub sp, sp, a0
; RV64ZVBC64-NEXT:    li a0, 51
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV64ZVBC64-NEXT:    vsll.vi v24, v8, 4
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV64ZVBC64-NEXT:    li a1, 85
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsll.vi v24, v16, 4
; RV64ZVBC64-NEXT:    vsrl.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a2, 16
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a2, 32
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    li a2, 64
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    li a2, 128
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv64i8_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv64i8_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v16
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 64 x i8> %va to <vscale x 64 x i16>
  %vb.ext = zext <vscale x 64 x i8> %vb to <vscale x 64 x i16>
  %clmul = call <vscale x 64 x i16> @llvm.clmul.nxv64i16(<vscale x 64 x i16> %va.ext, <vscale x 64 x i16> %vb.ext)
  %res.ext = lshr <vscale x 64 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 64 x i16> %res.ext to <vscale x 64 x i8>
  ret <vscale x 64 x i8> %res
}

define <vscale x 64 x i8> @clmulh_nxv64i8_vx(<vscale x 64 x i8> %va, i8 %b) nounwind {
; RV32V-LABEL: clmulh_nxv64i8_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsll.vi v24, v8, 4
; RV32V-NEXT:    vsrl.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vsrl.vi v24, v8, 2
; RV32V-NEXT:    li a0, 51
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 1
; RV32V-NEXT:    li a1, 85
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsll.vi v24, v16, 4
; RV32V-NEXT:    vsrl.vi v16, v16, 4
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsrl.vi v24, v16, 2
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 1
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vadd.vv v16, v16, v16
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vand.vi v24, v16, 2
; RV32V-NEXT:    vand.vi v0, v16, 1
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v0, v16, 4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v24, v16, 8
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a2, 16
; RV32V-NEXT:    vand.vx v0, v16, a2
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a2, 32
; RV32V-NEXT:    vand.vx v24, v16, a2
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    li a2, 64
; RV32V-NEXT:    vand.vx v0, v16, a2
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    li a2, 128
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v16, v24, v0
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsll.vi v16, v16, 4
; RV32V-NEXT:    vsrl.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv64i8_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV64V-NEXT:    vmv.v.x v16, a0
; RV64V-NEXT:    vsll.vi v24, v8, 4
; RV64V-NEXT:    vsrl.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    vsrl.vi v24, v8, 2
; RV64V-NEXT:    li a0, 51
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v8, 1
; RV64V-NEXT:    li a1, 85
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsll.vi v24, v16, 4
; RV64V-NEXT:    vsrl.vi v16, v16, 4
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsrl.vi v24, v16, 2
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsll.vi v16, v16, 2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 1
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vadd.vv v16, v16, v16
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vi v24, v16, 2
; RV64V-NEXT:    vand.vi v0, v16, 1
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v0, v16, 4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v24, v16, 8
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a2, 16
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a2, 32
; RV64V-NEXT:    vand.vx v24, v16, a2
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    li a2, 64
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    li a2, 128
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    vxor.vv v16, v24, v0
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vsll.vi v16, v16, 4
; RV64V-NEXT:    vsrl.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv64i8_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    sub sp, sp, a1
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v16, a0
; RV32ZVBC64-NEXT:    vsll.vi v24, v8, 4
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV32ZVBC64-NEXT:    li a0, 51
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV32ZVBC64-NEXT:    li a1, 85
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsll.vi v24, v16, 4
; RV32ZVBC64-NEXT:    vsrl.vi v16, v16, 4
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a2, 16
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a2, 32
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    li a2, 64
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    li a2, 128
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv64i8_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    sub sp, sp, a1
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsll.vi v24, v8, 4
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV64ZVBC64-NEXT:    li a0, 51
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV64ZVBC64-NEXT:    li a1, 85
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsll.vi v24, v16, 4
; RV64ZVBC64-NEXT:    vsrl.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a2, 16
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a2, 32
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    li a2, 64
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    li a2, 128
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv64i8_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv64i8_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
  %va.ext = zext <vscale x 64 x i8> %va to <vscale x 64 x i16>
  %vb.ext = zext <vscale x 64 x i8> %vb to <vscale x 64 x i16>
  %clmul = call <vscale x 64 x i16> @llvm.clmul.nxv64i16(<vscale x 64 x i16> %va.ext, <vscale x 64 x i16> %vb.ext)
  %res.ext = lshr <vscale x 64 x i16> %clmul, splat(i16 8)
  %res = trunc <vscale x 64 x i16> %res.ext to <vscale x 64 x i8>
  ret <vscale x 64 x i8> %res
}

define <vscale x 1 x i16> @clmulh_nxv1i16_vv(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv1i16_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v9
; RV32V-NEXT:    vzext.vf2 v9, v8
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    lui a1, 139810
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    addi a1, a1, 546
; RV32V-NEXT:    vand.vx v8, v10, a0
; RV32V-NEXT:    lui a2, 559241
; RV32V-NEXT:    vand.vx v11, v9, a1
; RV32V-NEXT:    lui a3, 279620
; RV32V-NEXT:    vand.vx v12, v10, a1
; RV32V-NEXT:    addi a2, a2, -1912
; RV32V-NEXT:    vand.vx v13, v9, a0
; RV32V-NEXT:    addi a3, a3, 1092
; RV32V-NEXT:    vand.vx v14, v10, a2
; RV32V-NEXT:    vand.vx v15, v9, a3
; RV32V-NEXT:    vand.vx v10, v10, a3
; RV32V-NEXT:    vmul.vv v16, v11, v8
; RV32V-NEXT:    vmul.vv v17, v13, v12
; RV32V-NEXT:    vmul.vv v18, v11, v14
; RV32V-NEXT:    vmul.vv v19, v13, v8
; RV32V-NEXT:    vand.vx v9, v9, a2
; RV32V-NEXT:    vmul.vv v20, v15, v14
; RV32V-NEXT:    vxor.vv v16, v17, v16
; RV32V-NEXT:    vmul.vv v17, v9, v10
; RV32V-NEXT:    vxor.vv v18, v19, v18
; RV32V-NEXT:    vmul.vv v19, v15, v10
; RV32V-NEXT:    vxor.vv v16, v16, v20
; RV32V-NEXT:    vmul.vv v20, v11, v12
; RV32V-NEXT:    vmul.vv v11, v11, v10
; RV32V-NEXT:    vmul.vv v10, v13, v10
; RV32V-NEXT:    vxor.vv v16, v16, v17
; RV32V-NEXT:    vmul.vv v17, v9, v12
; RV32V-NEXT:    vmul.vv v12, v15, v12
; RV32V-NEXT:    vmul.vv v15, v15, v8
; RV32V-NEXT:    vmul.vv v13, v13, v14
; RV32V-NEXT:    vxor.vv v18, v18, v19
; RV32V-NEXT:    vxor.vv v10, v10, v20
; RV32V-NEXT:    vmul.vv v14, v9, v14
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vxor.vv v17, v18, v17
; RV32V-NEXT:    vxor.vv v10, v10, v15
; RV32V-NEXT:    vxor.vv v11, v13, v11
; RV32V-NEXT:    vmul.vv v8, v9, v8
; RV32V-NEXT:    vand.vx v9, v17, a0
; RV32V-NEXT:    vxor.vv v10, v10, v14
; RV32V-NEXT:    vxor.vv v11, v11, v12
; RV32V-NEXT:    vor.vv v9, v9, v16
; RV32V-NEXT:    vand.vx v10, v10, a3
; RV32V-NEXT:    vxor.vv v8, v11, v8
; RV32V-NEXT:    vor.vv v9, v9, v10
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vor.vv v8, v9, v8
; RV32V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i16_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v9
; RV64V-NEXT:    vzext.vf2 v9, v8
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    lui a1, 139810
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    addi a1, a1, 546
; RV64V-NEXT:    vand.vx v8, v10, a0
; RV64V-NEXT:    lui a2, 559241
; RV64V-NEXT:    vand.vx v11, v9, a1
; RV64V-NEXT:    lui a3, 279620
; RV64V-NEXT:    vand.vx v12, v10, a1
; RV64V-NEXT:    addi a2, a2, -1912
; RV64V-NEXT:    vand.vx v13, v9, a0
; RV64V-NEXT:    addi a3, a3, 1092
; RV64V-NEXT:    vand.vx v14, v10, a2
; RV64V-NEXT:    vand.vx v15, v9, a3
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vmul.vv v16, v11, v8
; RV64V-NEXT:    vmul.vv v17, v13, v12
; RV64V-NEXT:    vmul.vv v18, v11, v14
; RV64V-NEXT:    vmul.vv v19, v13, v8
; RV64V-NEXT:    vand.vx v9, v9, a2
; RV64V-NEXT:    vmul.vv v20, v15, v14
; RV64V-NEXT:    vxor.vv v16, v17, v16
; RV64V-NEXT:    vmul.vv v17, v9, v10
; RV64V-NEXT:    vxor.vv v18, v19, v18
; RV64V-NEXT:    vmul.vv v19, v15, v10
; RV64V-NEXT:    vxor.vv v16, v16, v20
; RV64V-NEXT:    vmul.vv v20, v11, v12
; RV64V-NEXT:    vmul.vv v11, v11, v10
; RV64V-NEXT:    vmul.vv v10, v13, v10
; RV64V-NEXT:    vxor.vv v16, v16, v17
; RV64V-NEXT:    vmul.vv v17, v9, v12
; RV64V-NEXT:    vmul.vv v12, v15, v12
; RV64V-NEXT:    vmul.vv v15, v15, v8
; RV64V-NEXT:    vmul.vv v13, v13, v14
; RV64V-NEXT:    vxor.vv v18, v18, v19
; RV64V-NEXT:    vxor.vv v10, v10, v20
; RV64V-NEXT:    vmul.vv v14, v9, v14
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vxor.vv v17, v18, v17
; RV64V-NEXT:    vxor.vv v10, v10, v15
; RV64V-NEXT:    vxor.vv v11, v13, v11
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vand.vx v9, v17, a0
; RV64V-NEXT:    vxor.vv v10, v10, v14
; RV64V-NEXT:    vxor.vv v11, v11, v12
; RV64V-NEXT:    vor.vv v9, v9, v16
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vxor.vv v8, v11, v8
; RV64V-NEXT:    vor.vv v9, v9, v10
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i16_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v10, v9
; RV32ZVBC64-NEXT:    vzext.vf4 v9, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v9, v10
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i16_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v10, v9
; RV64ZVBC64-NEXT:    vzext.vf4 v9, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v9, v10
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i16_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i16_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>
  %vb.ext = zext <vscale x 1 x i16> %vb to <vscale x 1 x i32>
  %clmul = call <vscale x 1 x i32> @llvm.clmul.nxv1i32(<vscale x 1 x i32> %va.ext, <vscale x 1 x i32> %vb.ext)
  %res.ext = lshr <vscale x 1 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 1 x i32> %res.ext to <vscale x 1 x i16>
  ret <vscale x 1 x i16> %res
}

define <vscale x 1 x i16> @clmulh_nxv1i16_vx(<vscale x 1 x i16> %va, i16 %b) nounwind {
; RV32V-LABEL: clmulh_nxv1i16_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a0
; RV32V-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    lui a1, 69905
; RV32V-NEXT:    lui a2, 279620
; RV32V-NEXT:    addi a3, a0, 546
; RV32V-NEXT:    vzext.vf2 v8, v9
; RV32V-NEXT:    addi a1, a1, 273
; RV32V-NEXT:    vand.vx v9, v10, a3
; RV32V-NEXT:    addi a0, a2, 1092
; RV32V-NEXT:    vand.vx v11, v10, a1
; RV32V-NEXT:    vand.vx v12, v10, a0
; RV32V-NEXT:    lui a2, 559241
; RV32V-NEXT:    vand.vx v13, v8, a1
; RV32V-NEXT:    addi a2, a2, -1912
; RV32V-NEXT:    vand.vx v14, v8, a3
; RV32V-NEXT:    vand.vx v15, v8, a2
; RV32V-NEXT:    vand.vx v10, v10, a2
; RV32V-NEXT:    vmul.vv v16, v9, v13
; RV32V-NEXT:    vmul.vv v17, v11, v14
; RV32V-NEXT:    vmul.vv v18, v9, v15
; RV32V-NEXT:    vmul.vv v19, v11, v13
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vmul.vv v20, v12, v15
; RV32V-NEXT:    vxor.vv v16, v17, v16
; RV32V-NEXT:    vmul.vv v17, v10, v8
; RV32V-NEXT:    vxor.vv v18, v19, v18
; RV32V-NEXT:    vmul.vv v19, v12, v8
; RV32V-NEXT:    vxor.vv v16, v16, v20
; RV32V-NEXT:    vmul.vv v20, v9, v14
; RV32V-NEXT:    vmul.vv v9, v9, v8
; RV32V-NEXT:    vmul.vv v8, v11, v8
; RV32V-NEXT:    vxor.vv v16, v16, v17
; RV32V-NEXT:    vmul.vv v17, v10, v14
; RV32V-NEXT:    vmul.vv v14, v12, v14
; RV32V-NEXT:    vmul.vv v12, v12, v13
; RV32V-NEXT:    vmul.vv v11, v11, v15
; RV32V-NEXT:    vxor.vv v18, v18, v19
; RV32V-NEXT:    vxor.vv v8, v8, v20
; RV32V-NEXT:    vmul.vv v15, v10, v15
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vxor.vv v17, v18, v17
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vxor.vv v9, v11, v9
; RV32V-NEXT:    vmul.vv v10, v10, v13
; RV32V-NEXT:    vand.vx v11, v17, a1
; RV32V-NEXT:    vxor.vv v8, v8, v15
; RV32V-NEXT:    vxor.vv v9, v9, v14
; RV32V-NEXT:    vor.vv v11, v11, v16
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vxor.vv v9, v9, v10
; RV32V-NEXT:    vor.vv v8, v11, v8
; RV32V-NEXT:    vand.vx v9, v9, a2
; RV32V-NEXT:    vor.vv v8, v8, v9
; RV32V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i16_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV64V-NEXT:    vmv.v.x v9, a0
; RV64V-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    lui a1, 69905
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    addi a3, a0, 546
; RV64V-NEXT:    vzext.vf2 v8, v9
; RV64V-NEXT:    addi a1, a1, 273
; RV64V-NEXT:    vand.vx v9, v10, a3
; RV64V-NEXT:    addi a0, a2, 1092
; RV64V-NEXT:    vand.vx v11, v10, a1
; RV64V-NEXT:    vand.vx v12, v10, a0
; RV64V-NEXT:    lui a2, 559241
; RV64V-NEXT:    vand.vx v13, v8, a1
; RV64V-NEXT:    addi a2, a2, -1912
; RV64V-NEXT:    vand.vx v14, v8, a3
; RV64V-NEXT:    vand.vx v15, v8, a2
; RV64V-NEXT:    vand.vx v10, v10, a2
; RV64V-NEXT:    vmul.vv v16, v9, v13
; RV64V-NEXT:    vmul.vv v17, v11, v14
; RV64V-NEXT:    vmul.vv v18, v9, v15
; RV64V-NEXT:    vmul.vv v19, v11, v13
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vmul.vv v20, v12, v15
; RV64V-NEXT:    vxor.vv v16, v17, v16
; RV64V-NEXT:    vmul.vv v17, v10, v8
; RV64V-NEXT:    vxor.vv v18, v19, v18
; RV64V-NEXT:    vmul.vv v19, v12, v8
; RV64V-NEXT:    vxor.vv v16, v16, v20
; RV64V-NEXT:    vmul.vv v20, v9, v14
; RV64V-NEXT:    vmul.vv v9, v9, v8
; RV64V-NEXT:    vmul.vv v8, v11, v8
; RV64V-NEXT:    vxor.vv v16, v16, v17
; RV64V-NEXT:    vmul.vv v17, v10, v14
; RV64V-NEXT:    vmul.vv v14, v12, v14
; RV64V-NEXT:    vmul.vv v12, v12, v13
; RV64V-NEXT:    vmul.vv v11, v11, v15
; RV64V-NEXT:    vxor.vv v18, v18, v19
; RV64V-NEXT:    vxor.vv v8, v8, v20
; RV64V-NEXT:    vmul.vv v15, v10, v15
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vxor.vv v17, v18, v17
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    vxor.vv v9, v11, v9
; RV64V-NEXT:    vmul.vv v10, v10, v13
; RV64V-NEXT:    vand.vx v11, v17, a1
; RV64V-NEXT:    vxor.vv v8, v8, v15
; RV64V-NEXT:    vxor.vv v9, v9, v14
; RV64V-NEXT:    vor.vv v11, v11, v16
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vxor.vv v9, v9, v10
; RV64V-NEXT:    vor.vv v8, v11, v8
; RV64V-NEXT:    vand.vx v9, v9, a2
; RV64V-NEXT:    vor.vv v8, v8, v9
; RV64V-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i16_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v9, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v10, v8
; RV32ZVBC64-NEXT:    vzext.vf4 v8, v9
; RV32ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v8, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i16_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v9, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v10, v8
; RV64ZVBC64-NEXT:    vzext.vf4 v8, v9
; RV64ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v8, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i16_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i16_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
  %va.ext = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>
  %vb.ext = zext <vscale x 1 x i16> %vb to <vscale x 1 x i32>
  %clmul = call <vscale x 1 x i32> @llvm.clmul.nxv1i32(<vscale x 1 x i32> %va.ext, <vscale x 1 x i32> %vb.ext)
  %res.ext = lshr <vscale x 1 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 1 x i32> %res.ext to <vscale x 1 x i16>
  ret <vscale x 1 x i16> %res
}

define <vscale x 2 x i16> @clmulh_nxv2i16_vv(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv2i16_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v9
; RV32V-NEXT:    vzext.vf2 v9, v8
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    lui a1, 139810
; RV32V-NEXT:    vand.vx v8, v10, a0
; RV32V-NEXT:    addi a1, a1, 546
; RV32V-NEXT:    vand.vx v11, v9, a1
; RV32V-NEXT:    vand.vx v12, v10, a1
; RV32V-NEXT:    vand.vx v13, v9, a0
; RV32V-NEXT:    vmul.vv v14, v11, v8
; RV32V-NEXT:    vmul.vv v15, v13, v12
; RV32V-NEXT:    lui a2, 559241
; RV32V-NEXT:    addi a2, a2, -1912
; RV32V-NEXT:    lui a3, 279620
; RV32V-NEXT:    vand.vx v16, v10, a2
; RV32V-NEXT:    addi a3, a3, 1092
; RV32V-NEXT:    vand.vx v17, v9, a3
; RV32V-NEXT:    vxor.vv v14, v15, v14
; RV32V-NEXT:    vmul.vv v15, v17, v16
; RV32V-NEXT:    vand.vx v10, v10, a3
; RV32V-NEXT:    vand.vx v9, v9, a2
; RV32V-NEXT:    vmul.vv v18, v11, v16
; RV32V-NEXT:    vmul.vv v19, v13, v8
; RV32V-NEXT:    vxor.vv v14, v14, v15
; RV32V-NEXT:    vmul.vv v15, v9, v10
; RV32V-NEXT:    vmul.vv v20, v17, v10
; RV32V-NEXT:    vxor.vv v18, v19, v18
; RV32V-NEXT:    vmul.vv v19, v9, v12
; RV32V-NEXT:    vxor.vv v14, v14, v15
; RV32V-NEXT:    vxor.vv v15, v18, v20
; RV32V-NEXT:    vand.vx v14, v14, a1
; RV32V-NEXT:    vxor.vv v15, v15, v19
; RV32V-NEXT:    vmul.vv v18, v11, v12
; RV32V-NEXT:    vmul.vv v19, v13, v10
; RV32V-NEXT:    vand.vx v15, v15, a0
; RV32V-NEXT:    vmul.vv v20, v17, v8
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    vxor.vv v15, v19, v18
; RV32V-NEXT:    vmul.vv v10, v11, v10
; RV32V-NEXT:    vmul.vv v11, v13, v16
; RV32V-NEXT:    vxor.vv v13, v15, v20
; RV32V-NEXT:    vmul.vv v15, v9, v16
; RV32V-NEXT:    vmul.vv v12, v17, v12
; RV32V-NEXT:    vxor.vv v10, v11, v10
; RV32V-NEXT:    vmul.vv v8, v9, v8
; RV32V-NEXT:    vxor.vv v9, v13, v15
; RV32V-NEXT:    vxor.vv v10, v10, v12
; RV32V-NEXT:    vand.vx v9, v9, a3
; RV32V-NEXT:    vxor.vv v8, v10, v8
; RV32V-NEXT:    vor.vv v9, v14, v9
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vor.vv v8, v9, v8
; RV32V-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i16_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v9
; RV64V-NEXT:    vzext.vf2 v9, v8
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    lui a1, 139810
; RV64V-NEXT:    vand.vx v8, v10, a0
; RV64V-NEXT:    addi a1, a1, 546
; RV64V-NEXT:    vand.vx v11, v9, a1
; RV64V-NEXT:    vand.vx v12, v10, a1
; RV64V-NEXT:    vand.vx v13, v9, a0
; RV64V-NEXT:    vmul.vv v14, v11, v8
; RV64V-NEXT:    vmul.vv v15, v13, v12
; RV64V-NEXT:    lui a2, 559241
; RV64V-NEXT:    addi a2, a2, -1912
; RV64V-NEXT:    lui a3, 279620
; RV64V-NEXT:    vand.vx v16, v10, a2
; RV64V-NEXT:    addi a3, a3, 1092
; RV64V-NEXT:    vand.vx v17, v9, a3
; RV64V-NEXT:    vxor.vv v14, v15, v14
; RV64V-NEXT:    vmul.vv v15, v17, v16
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vand.vx v9, v9, a2
; RV64V-NEXT:    vmul.vv v18, v11, v16
; RV64V-NEXT:    vmul.vv v19, v13, v8
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vmul.vv v15, v9, v10
; RV64V-NEXT:    vmul.vv v20, v17, v10
; RV64V-NEXT:    vxor.vv v18, v19, v18
; RV64V-NEXT:    vmul.vv v19, v9, v12
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vxor.vv v15, v18, v20
; RV64V-NEXT:    vand.vx v14, v14, a1
; RV64V-NEXT:    vxor.vv v15, v15, v19
; RV64V-NEXT:    vmul.vv v18, v11, v12
; RV64V-NEXT:    vmul.vv v19, v13, v10
; RV64V-NEXT:    vand.vx v15, v15, a0
; RV64V-NEXT:    vmul.vv v20, v17, v8
; RV64V-NEXT:    vor.vv v14, v15, v14
; RV64V-NEXT:    vxor.vv v15, v19, v18
; RV64V-NEXT:    vmul.vv v10, v11, v10
; RV64V-NEXT:    vmul.vv v11, v13, v16
; RV64V-NEXT:    vxor.vv v13, v15, v20
; RV64V-NEXT:    vmul.vv v15, v9, v16
; RV64V-NEXT:    vmul.vv v12, v17, v12
; RV64V-NEXT:    vxor.vv v10, v11, v10
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vxor.vv v9, v13, v15
; RV64V-NEXT:    vxor.vv v10, v10, v12
; RV64V-NEXT:    vand.vx v9, v9, a3
; RV64V-NEXT:    vxor.vv v8, v10, v8
; RV64V-NEXT:    vor.vv v9, v14, v9
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i16_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v10, v9
; RV32ZVBC64-NEXT:    vzext.vf4 v12, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v12, v10
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v10, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i16_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v10, v9
; RV64ZVBC64-NEXT:    vzext.vf4 v12, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v12, v10
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v10, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i16_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i16_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>
  %vb.ext = zext <vscale x 2 x i16> %vb to <vscale x 2 x i32>
  %clmul = call <vscale x 2 x i32> @llvm.clmul.nxv2i32(<vscale x 2 x i32> %va.ext, <vscale x 2 x i32> %vb.ext)
  %res.ext = lshr <vscale x 2 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 2 x i32> %res.ext to <vscale x 2 x i16>
  ret <vscale x 2 x i16> %res
}

define <vscale x 2 x i16> @clmulh_nxv2i16_vx(<vscale x 2 x i16> %va, i16 %b) nounwind {
; RV32V-LABEL: clmulh_nxv2i16_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a0
; RV32V-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32V-NEXT:    vzext.vf2 v10, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    vzext.vf2 v8, v9
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    lui a1, 69905
; RV32V-NEXT:    vand.vx v9, v10, a0
; RV32V-NEXT:    addi a1, a1, 273
; RV32V-NEXT:    vand.vx v11, v8, a1
; RV32V-NEXT:    vand.vx v12, v10, a1
; RV32V-NEXT:    vand.vx v13, v8, a0
; RV32V-NEXT:    vmul.vv v14, v9, v11
; RV32V-NEXT:    vmul.vv v15, v12, v13
; RV32V-NEXT:    lui a2, 279620
; RV32V-NEXT:    addi a2, a2, 1092
; RV32V-NEXT:    lui a3, 559241
; RV32V-NEXT:    vand.vx v16, v10, a2
; RV32V-NEXT:    addi a3, a3, -1912
; RV32V-NEXT:    vand.vx v17, v8, a3
; RV32V-NEXT:    vxor.vv v14, v15, v14
; RV32V-NEXT:    vmul.vv v15, v16, v17
; RV32V-NEXT:    vand.vx v10, v10, a3
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vmul.vv v18, v9, v17
; RV32V-NEXT:    vmul.vv v19, v12, v11
; RV32V-NEXT:    vxor.vv v14, v14, v15
; RV32V-NEXT:    vmul.vv v15, v10, v8
; RV32V-NEXT:    vmul.vv v20, v16, v8
; RV32V-NEXT:    vxor.vv v18, v19, v18
; RV32V-NEXT:    vmul.vv v19, v10, v13
; RV32V-NEXT:    vxor.vv v14, v14, v15
; RV32V-NEXT:    vxor.vv v15, v18, v20
; RV32V-NEXT:    vand.vx v14, v14, a0
; RV32V-NEXT:    vxor.vv v15, v15, v19
; RV32V-NEXT:    vmul.vv v18, v9, v13
; RV32V-NEXT:    vmul.vv v19, v12, v8
; RV32V-NEXT:    vand.vx v15, v15, a1
; RV32V-NEXT:    vmul.vv v20, v16, v11
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    vxor.vv v15, v19, v18
; RV32V-NEXT:    vmul.vv v8, v9, v8
; RV32V-NEXT:    vmul.vv v9, v12, v17
; RV32V-NEXT:    vxor.vv v12, v15, v20
; RV32V-NEXT:    vmul.vv v15, v10, v17
; RV32V-NEXT:    vmul.vv v13, v16, v13
; RV32V-NEXT:    vxor.vv v8, v9, v8
; RV32V-NEXT:    vmul.vv v9, v10, v11
; RV32V-NEXT:    vxor.vv v10, v12, v15
; RV32V-NEXT:    vxor.vv v8, v8, v13
; RV32V-NEXT:    vand.vx v10, v10, a2
; RV32V-NEXT:    vxor.vv v8, v8, v9
; RV32V-NEXT:    vor.vv v9, v14, v10
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    vor.vv v8, v9, v8
; RV32V-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v8, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i16_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV64V-NEXT:    vmv.v.x v9, a0
; RV64V-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    vzext.vf2 v8, v9
; RV64V-NEXT:    addi a0, a0, 546
; RV64V-NEXT:    lui a1, 69905
; RV64V-NEXT:    vand.vx v9, v10, a0
; RV64V-NEXT:    addi a1, a1, 273
; RV64V-NEXT:    vand.vx v11, v8, a1
; RV64V-NEXT:    vand.vx v12, v10, a1
; RV64V-NEXT:    vand.vx v13, v8, a0
; RV64V-NEXT:    vmul.vv v14, v9, v11
; RV64V-NEXT:    vmul.vv v15, v12, v13
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    lui a3, 559241
; RV64V-NEXT:    vand.vx v16, v10, a2
; RV64V-NEXT:    addi a3, a3, -1912
; RV64V-NEXT:    vand.vx v17, v8, a3
; RV64V-NEXT:    vxor.vv v14, v15, v14
; RV64V-NEXT:    vmul.vv v15, v16, v17
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vmul.vv v18, v9, v17
; RV64V-NEXT:    vmul.vv v19, v12, v11
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vmul.vv v15, v10, v8
; RV64V-NEXT:    vmul.vv v20, v16, v8
; RV64V-NEXT:    vxor.vv v18, v19, v18
; RV64V-NEXT:    vmul.vv v19, v10, v13
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vxor.vv v15, v18, v20
; RV64V-NEXT:    vand.vx v14, v14, a0
; RV64V-NEXT:    vxor.vv v15, v15, v19
; RV64V-NEXT:    vmul.vv v18, v9, v13
; RV64V-NEXT:    vmul.vv v19, v12, v8
; RV64V-NEXT:    vand.vx v15, v15, a1
; RV64V-NEXT:    vmul.vv v20, v16, v11
; RV64V-NEXT:    vor.vv v14, v15, v14
; RV64V-NEXT:    vxor.vv v15, v19, v18
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vmul.vv v9, v12, v17
; RV64V-NEXT:    vxor.vv v12, v15, v20
; RV64V-NEXT:    vmul.vv v15, v10, v17
; RV64V-NEXT:    vmul.vv v13, v16, v13
; RV64V-NEXT:    vxor.vv v8, v9, v8
; RV64V-NEXT:    vmul.vv v9, v10, v11
; RV64V-NEXT:    vxor.vv v10, v12, v15
; RV64V-NEXT:    vxor.vv v8, v8, v13
; RV64V-NEXT:    vand.vx v10, v10, a2
; RV64V-NEXT:    vxor.vv v8, v8, v9
; RV64V-NEXT:    vor.vv v9, v14, v10
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v8, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i16_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v12, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v10, v8
; RV32ZVBC64-NEXT:    vzext.vf4 v8, v12
; RV32ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v10, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i16_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v12, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v10, v8
; RV64ZVBC64-NEXT:    vzext.vf4 v8, v12
; RV64ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v10, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v10, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i16_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i16_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
  %va.ext = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>
  %vb.ext = zext <vscale x 2 x i16> %vb to <vscale x 2 x i32>
  %clmul = call <vscale x 2 x i32> @llvm.clmul.nxv2i32(<vscale x 2 x i32> %va.ext, <vscale x 2 x i32> %vb.ext)
  %res.ext = lshr <vscale x 2 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 2 x i32> %res.ext to <vscale x 2 x i16>
  ret <vscale x 2 x i16> %res
}

define <vscale x 4 x i16> @clmulh_nxv4i16_vv(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv4i16_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vzext.vf2 v20, v9
; RV32V-NEXT:    vand.vx v10, v20, a0
; RV32V-NEXT:    vzext.vf2 v22, v8
; RV32V-NEXT:    lui a1, 139810
; RV32V-NEXT:    addi a1, a1, 546
; RV32V-NEXT:    vand.vx v12, v22, a1
; RV32V-NEXT:    vand.vx v8, v20, a1
; RV32V-NEXT:    vand.vx v14, v22, a0
; RV32V-NEXT:    vmul.vv v16, v12, v10
; RV32V-NEXT:    vmul.vv v18, v14, v8
; RV32V-NEXT:    vxor.vv v24, v18, v16
; RV32V-NEXT:    lui a2, 559241
; RV32V-NEXT:    addi a2, a2, -1912
; RV32V-NEXT:    vand.vx v16, v20, a2
; RV32V-NEXT:    lui a3, 279620
; RV32V-NEXT:    addi a3, a3, 1092
; RV32V-NEXT:    vand.vx v18, v22, a3
; RV32V-NEXT:    vand.vx v26, v20, a3
; RV32V-NEXT:    vmul.vv v28, v18, v16
; RV32V-NEXT:    vand.vx v20, v22, a2
; RV32V-NEXT:    vmul.vv v22, v20, v26
; RV32V-NEXT:    vxor.vv v24, v24, v28
; RV32V-NEXT:    vxor.vv v22, v24, v22
; RV32V-NEXT:    vmul.vv v24, v12, v16
; RV32V-NEXT:    vmul.vv v28, v14, v10
; RV32V-NEXT:    vand.vx v22, v22, a1
; RV32V-NEXT:    vxor.vv v24, v28, v24
; RV32V-NEXT:    vmul.vv v28, v18, v26
; RV32V-NEXT:    vmul.vv v30, v20, v8
; RV32V-NEXT:    vxor.vv v24, v24, v28
; RV32V-NEXT:    vxor.vv v24, v24, v30
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vmul.vv v28, v12, v8
; RV32V-NEXT:    vmul.vv v30, v14, v26
; RV32V-NEXT:    vor.vv v22, v24, v22
; RV32V-NEXT:    vxor.vv v24, v30, v28
; RV32V-NEXT:    vmul.vv v28, v18, v10
; RV32V-NEXT:    vmul.vv v30, v20, v16
; RV32V-NEXT:    vxor.vv v24, v24, v28
; RV32V-NEXT:    vxor.vv v24, v24, v30
; RV32V-NEXT:    vand.vx v24, v24, a3
; RV32V-NEXT:    vmul.vv v12, v12, v26
; RV32V-NEXT:    vmul.vv v14, v14, v16
; RV32V-NEXT:    vor.vv v16, v22, v24
; RV32V-NEXT:    vxor.vv v12, v14, v12
; RV32V-NEXT:    vmul.vv v8, v18, v8
; RV32V-NEXT:    vmul.vv v10, v20, v10
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    vxor.vv v8, v8, v10
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vor.vv v10, v16, v8
; RV32V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v10, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i16_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV64V-NEXT:    vzext.vf2 v20, v9
; RV64V-NEXT:    vand.vx v10, v20, a0
; RV64V-NEXT:    vzext.vf2 v22, v8
; RV64V-NEXT:    lui a1, 139810
; RV64V-NEXT:    addi a1, a1, 546
; RV64V-NEXT:    vand.vx v12, v22, a1
; RV64V-NEXT:    vand.vx v8, v20, a1
; RV64V-NEXT:    vand.vx v14, v22, a0
; RV64V-NEXT:    vmul.vv v16, v12, v10
; RV64V-NEXT:    vmul.vv v18, v14, v8
; RV64V-NEXT:    vxor.vv v24, v18, v16
; RV64V-NEXT:    lui a2, 559241
; RV64V-NEXT:    addi a2, a2, -1912
; RV64V-NEXT:    vand.vx v16, v20, a2
; RV64V-NEXT:    lui a3, 279620
; RV64V-NEXT:    addi a3, a3, 1092
; RV64V-NEXT:    vand.vx v18, v22, a3
; RV64V-NEXT:    vand.vx v26, v20, a3
; RV64V-NEXT:    vmul.vv v28, v18, v16
; RV64V-NEXT:    vand.vx v20, v22, a2
; RV64V-NEXT:    vmul.vv v22, v20, v26
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v22, v24, v22
; RV64V-NEXT:    vmul.vv v24, v12, v16
; RV64V-NEXT:    vmul.vv v28, v14, v10
; RV64V-NEXT:    vand.vx v22, v22, a1
; RV64V-NEXT:    vxor.vv v24, v28, v24
; RV64V-NEXT:    vmul.vv v28, v18, v26
; RV64V-NEXT:    vmul.vv v30, v20, v8
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v24, v24, v30
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vmul.vv v28, v12, v8
; RV64V-NEXT:    vmul.vv v30, v14, v26
; RV64V-NEXT:    vor.vv v22, v24, v22
; RV64V-NEXT:    vxor.vv v24, v30, v28
; RV64V-NEXT:    vmul.vv v28, v18, v10
; RV64V-NEXT:    vmul.vv v30, v20, v16
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v24, v24, v30
; RV64V-NEXT:    vand.vx v24, v24, a3
; RV64V-NEXT:    vmul.vv v12, v12, v26
; RV64V-NEXT:    vmul.vv v14, v14, v16
; RV64V-NEXT:    vor.vv v16, v22, v24
; RV64V-NEXT:    vxor.vv v12, v14, v12
; RV64V-NEXT:    vmul.vv v8, v18, v8
; RV64V-NEXT:    vmul.vv v10, v20, v10
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    vxor.vv v8, v8, v10
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v10, v16, v8
; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v10, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i16_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v12, v9
; RV32ZVBC64-NEXT:    vzext.vf4 v16, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v16, v12
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v12, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i16_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v12, v9
; RV64ZVBC64-NEXT:    vzext.vf4 v16, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v16, v12
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v12, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i16_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i16_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>
  %vb.ext = zext <vscale x 4 x i16> %vb to <vscale x 4 x i32>
  %clmul = call <vscale x 4 x i32> @llvm.clmul.nxv4i32(<vscale x 4 x i32> %va.ext, <vscale x 4 x i32> %vb.ext)
  %res.ext = lshr <vscale x 4 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 4 x i32> %res.ext to <vscale x 4 x i16>
  ret <vscale x 4 x i16> %res
}

define <vscale x 4 x i16> @clmulh_nxv4i16_vx(<vscale x 4 x i16> %va, i16 %b) nounwind {
; RV32V-LABEL: clmulh_nxv4i16_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vzext.vf2 v18, v8
; RV32V-NEXT:    lui a1, 139810
; RV32V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    addi a0, a1, 546
; RV32V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32V-NEXT:    vand.vx v10, v18, a0
; RV32V-NEXT:    vzext.vf2 v22, v8
; RV32V-NEXT:    lui a1, 69905
; RV32V-NEXT:    addi a1, a1, 273
; RV32V-NEXT:    vand.vx v8, v22, a1
; RV32V-NEXT:    vand.vx v14, v18, a1
; RV32V-NEXT:    vand.vx v12, v22, a0
; RV32V-NEXT:    vmul.vv v16, v10, v8
; RV32V-NEXT:    vmul.vv v20, v14, v12
; RV32V-NEXT:    vxor.vv v24, v20, v16
; RV32V-NEXT:    lui a2, 279620
; RV32V-NEXT:    addi a2, a2, 1092
; RV32V-NEXT:    vand.vx v16, v18, a2
; RV32V-NEXT:    lui a3, 559241
; RV32V-NEXT:    addi a3, a3, -1912
; RV32V-NEXT:    vand.vx v20, v22, a3
; RV32V-NEXT:    vand.vx v18, v18, a3
; RV32V-NEXT:    vmul.vv v26, v16, v20
; RV32V-NEXT:    vand.vx v22, v22, a2
; RV32V-NEXT:    vmul.vv v28, v18, v22
; RV32V-NEXT:    vxor.vv v24, v24, v26
; RV32V-NEXT:    vxor.vv v24, v24, v28
; RV32V-NEXT:    vmul.vv v26, v10, v20
; RV32V-NEXT:    vmul.vv v28, v14, v8
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vxor.vv v26, v28, v26
; RV32V-NEXT:    vmul.vv v28, v16, v22
; RV32V-NEXT:    vmul.vv v30, v18, v12
; RV32V-NEXT:    vxor.vv v26, v26, v28
; RV32V-NEXT:    vxor.vv v26, v26, v30
; RV32V-NEXT:    vand.vx v26, v26, a1
; RV32V-NEXT:    vmul.vv v28, v10, v12
; RV32V-NEXT:    vmul.vv v30, v14, v22
; RV32V-NEXT:    vor.vv v24, v26, v24
; RV32V-NEXT:    vxor.vv v26, v30, v28
; RV32V-NEXT:    vmul.vv v28, v16, v8
; RV32V-NEXT:    vmul.vv v30, v18, v20
; RV32V-NEXT:    vxor.vv v26, v26, v28
; RV32V-NEXT:    vxor.vv v26, v26, v30
; RV32V-NEXT:    vand.vx v26, v26, a2
; RV32V-NEXT:    vmul.vv v10, v10, v22
; RV32V-NEXT:    vmul.vv v14, v14, v20
; RV32V-NEXT:    vor.vv v20, v24, v26
; RV32V-NEXT:    vxor.vv v10, v14, v10
; RV32V-NEXT:    vmul.vv v12, v16, v12
; RV32V-NEXT:    vmul.vv v8, v18, v8
; RV32V-NEXT:    vxor.vv v10, v10, v12
; RV32V-NEXT:    vxor.vv v8, v10, v8
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    vor.vv v10, v20, v8
; RV32V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v10, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i16_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV64V-NEXT:    vzext.vf2 v18, v8
; RV64V-NEXT:    lui a1, 139810
; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64V-NEXT:    vmv.v.x v8, a0
; RV64V-NEXT:    addi a0, a1, 546
; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64V-NEXT:    vand.vx v10, v18, a0
; RV64V-NEXT:    vzext.vf2 v22, v8
; RV64V-NEXT:    lui a1, 69905
; RV64V-NEXT:    addi a1, a1, 273
; RV64V-NEXT:    vand.vx v8, v22, a1
; RV64V-NEXT:    vand.vx v14, v18, a1
; RV64V-NEXT:    vand.vx v12, v22, a0
; RV64V-NEXT:    vmul.vv v16, v10, v8
; RV64V-NEXT:    vmul.vv v20, v14, v12
; RV64V-NEXT:    vxor.vv v24, v20, v16
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    vand.vx v16, v18, a2
; RV64V-NEXT:    lui a3, 559241
; RV64V-NEXT:    addi a3, a3, -1912
; RV64V-NEXT:    vand.vx v20, v22, a3
; RV64V-NEXT:    vand.vx v18, v18, a3
; RV64V-NEXT:    vmul.vv v26, v16, v20
; RV64V-NEXT:    vand.vx v22, v22, a2
; RV64V-NEXT:    vmul.vv v28, v18, v22
; RV64V-NEXT:    vxor.vv v24, v24, v26
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vmul.vv v26, v10, v20
; RV64V-NEXT:    vmul.vv v28, v14, v8
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vxor.vv v26, v28, v26
; RV64V-NEXT:    vmul.vv v28, v16, v22
; RV64V-NEXT:    vmul.vv v30, v18, v12
; RV64V-NEXT:    vxor.vv v26, v26, v28
; RV64V-NEXT:    vxor.vv v26, v26, v30
; RV64V-NEXT:    vand.vx v26, v26, a1
; RV64V-NEXT:    vmul.vv v28, v10, v12
; RV64V-NEXT:    vmul.vv v30, v14, v22
; RV64V-NEXT:    vor.vv v24, v26, v24
; RV64V-NEXT:    vxor.vv v26, v30, v28
; RV64V-NEXT:    vmul.vv v28, v16, v8
; RV64V-NEXT:    vmul.vv v30, v18, v20
; RV64V-NEXT:    vxor.vv v26, v26, v28
; RV64V-NEXT:    vxor.vv v26, v26, v30
; RV64V-NEXT:    vand.vx v26, v26, a2
; RV64V-NEXT:    vmul.vv v10, v10, v22
; RV64V-NEXT:    vmul.vv v14, v14, v20
; RV64V-NEXT:    vor.vv v20, v24, v26
; RV64V-NEXT:    vxor.vv v10, v14, v10
; RV64V-NEXT:    vmul.vv v12, v16, v12
; RV64V-NEXT:    vmul.vv v8, v18, v8
; RV64V-NEXT:    vxor.vv v10, v10, v12
; RV64V-NEXT:    vxor.vv v8, v10, v8
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vor.vv v10, v20, v8
; RV64V-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v10, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i16_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v16, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v12, v8
; RV32ZVBC64-NEXT:    vzext.vf4 v8, v16
; RV32ZVBC64-NEXT:    vclmul.vv v8, v12, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v12, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i16_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v12, v8
; RV64ZVBC64-NEXT:    vzext.vf4 v8, v16
; RV64ZVBC64-NEXT:    vclmul.vv v8, v12, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v12, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v12, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i16_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i16_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
  %va.ext = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>
  %vb.ext = zext <vscale x 4 x i16> %vb to <vscale x 4 x i32>
  %clmul = call <vscale x 4 x i32> @llvm.clmul.nxv4i32(<vscale x 4 x i32> %va.ext, <vscale x 4 x i32> %vb.ext)
  %res.ext = lshr <vscale x 4 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 4 x i32> %res.ext to <vscale x 4 x i16>
  ret <vscale x 4 x i16> %res
}

define <vscale x 8 x i16> @clmulh_nxv8i16_vv(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv8i16_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    lui a1, 69905
; RV32V-NEXT:    addi a1, a1, 273
; RV32V-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; RV32V-NEXT:    vzext.vf2 v0, v10
; RV32V-NEXT:    vand.vx v12, v0, a1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a2, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vzext.vf2 v4, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a3, a0, 546
; RV32V-NEXT:    vand.vx v16, v4, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v8, v0, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a2, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v20, v4, a1
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vand.vx v24, v0, a0
; RV32V-NEXT:    vmul.vv v12, v16, v12
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v20, v8
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs4r.v v20, (a2) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs4r.v v8, (a2) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a2, 279620
; RV32V-NEXT:    addi a2, a2, 1092
; RV32V-NEXT:    vand.vx v28, v4, a2
; RV32V-NEXT:    vmul.vv v8, v28, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v12, v12, v16
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v0, a2
; RV32V-NEXT:    vand.vx v4, v4, a0
; RV32V-NEXT:    vmul.vv v8, v4, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v16, v24
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v20, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v12, v12, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v12, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v20, v8, v12
; RV32V-NEXT:    vmul.vv v12, v28, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v4, v8
; RV32V-NEXT:    vxor.vv v12, v20, v12
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vx v12, v12, a3
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 3
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vs4r.v v12, (a3) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v16, v8
; RV32V-NEXT:    addi a1, sp, 16
; RV32V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v20, v0
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v12, v12, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a1, sp, 16
; RV32V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v16, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v28, v8
; RV32V-NEXT:    vmul.vv v8, v4, v24
; RV32V-NEXT:    vxor.vv v12, v16, v12
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v12, v0
; RV32V-NEXT:    vmul.vv v16, v20, v24
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v20, v8
; RV32V-NEXT:    vxor.vv v12, v16, v12
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v28, v16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v4, v20
; RV32V-NEXT:    vxor.vv v12, v12, v16
; RV32V-NEXT:    vxor.vv v12, v12, v20
; RV32V-NEXT:    vand.vx v12, v12, a0
; RV32V-NEXT:    vor.vv v12, v8, v12
; RV32V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v12, 16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i16_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    lui a1, 69905
; RV64V-NEXT:    addi a1, a1, 273
; RV64V-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; RV64V-NEXT:    vzext.vf2 v0, v10
; RV64V-NEXT:    vand.vx v12, v0, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vzext.vf2 v4, v8
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    addi a3, a0, 546
; RV64V-NEXT:    vand.vx v16, v4, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v0, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v20, v4, a1
; RV64V-NEXT:    lui a0, 559241
; RV64V-NEXT:    addi a0, a0, -1912
; RV64V-NEXT:    vand.vx v24, v0, a0
; RV64V-NEXT:    vmul.vv v12, v16, v12
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v20, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v8, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    vand.vx v28, v4, a2
; RV64V-NEXT:    vmul.vv v8, v28, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v0, a2
; RV64V-NEXT:    vand.vx v4, v4, a0
; RV64V-NEXT:    vmul.vv v8, v4, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v16, v24
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v12, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v20, v8, v12
; RV64V-NEXT:    vmul.vv v12, v28, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v4, v8
; RV64V-NEXT:    vxor.vv v12, v20, v12
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 3
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs4r.v v12, (a3) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    addi a1, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v20, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v12, v12, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    addi a1, sp, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v16, v16, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v28, v8
; RV64V-NEXT:    vmul.vv v8, v4, v24
; RV64V-NEXT:    vxor.vv v12, v16, v12
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v12, v0
; RV64V-NEXT:    vmul.vv v16, v20, v24
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v20, v8
; RV64V-NEXT:    vxor.vv v12, v16, v12
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v28, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v20, v4, v20
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vand.vx v12, v12, a0
; RV64V-NEXT:    vor.vv v12, v8, v12
; RV64V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v12, 16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i16_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v16, v10
; RV32ZVBC64-NEXT:    vzext.vf4 v24, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v24, v16
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i16_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v16, v10
; RV64ZVBC64-NEXT:    vzext.vf4 v24, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v24, v16
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i16_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v10
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i16_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v10
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>
  %vb.ext = zext <vscale x 8 x i16> %vb to <vscale x 8 x i32>
  %clmul = call <vscale x 8 x i32> @llvm.clmul.nxv8i32(<vscale x 8 x i32> %va.ext, <vscale x 8 x i32> %vb.ext)
  %res.ext = lshr <vscale x 8 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 8 x i32> %res.ext to <vscale x 8 x i16>
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @clmulh_nxv8i16_vx(<vscale x 8 x i16> %va, i16 %b) nounwind {
; RV32V-LABEL: clmulh_nxv8i16_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 5
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vzext.vf2 v28, v8
; RV32V-NEXT:    lui a2, 139810
; RV32V-NEXT:    addi a2, a2, 546
; RV32V-NEXT:    vand.vx v12, v28, a2
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32V-NEXT:    vzext.vf2 v0, v8
; RV32V-NEXT:    lui a3, 69905
; RV32V-NEXT:    addi a3, a3, 273
; RV32V-NEXT:    vand.vx v8, v0, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v20, v28, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v16, v0, a2
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vand.vx v24, v28, a0
; RV32V-NEXT:    vmul.vv v8, v12, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a4, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v20, v16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a4, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a1, 559241
; RV32V-NEXT:    addi a1, a1, -1912
; RV32V-NEXT:    vand.vx v4, v0, a1
; RV32V-NEXT:    vmul.vv v8, v24, v4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v12, v12, v20
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v28, v28, a1
; RV32V-NEXT:    vand.vx v0, v0, a0
; RV32V-NEXT:    vmul.vv v8, v28, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v20, v8
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v12, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v12, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v28, v16
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v12, v12, v8
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs4r.v v8, (a2) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs4r.v v8, (a2) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v20, v0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl4r.v v16, (a2) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl4r.v v12, (a2) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v12, v16
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl4r.v v12, (a2) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v8, v12
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a3, a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v24, v8
; RV32V-NEXT:    vmul.vv v8, v28, v4
; RV32V-NEXT:    vxor.vv v12, v16, v12
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl4r.v v12, (a2) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v12, v0
; RV32V-NEXT:    vmul.vv v20, v20, v4
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a2, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vxor.vv v12, v20, v12
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a2, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a2, a2, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v28, v20
; RV32V-NEXT:    vxor.vv v12, v12, v16
; RV32V-NEXT:    vxor.vv v12, v12, v20
; RV32V-NEXT:    vand.vx v12, v12, a1
; RV32V-NEXT:    vor.vv v12, v8, v12
; RV32V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v12, 16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i16_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV64V-NEXT:    vzext.vf2 v28, v8
; RV64V-NEXT:    lui a2, 139810
; RV64V-NEXT:    addi a2, a2, 546
; RV64V-NEXT:    vand.vx v12, v28, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64V-NEXT:    vmv.v.x v8, a0
; RV64V-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64V-NEXT:    vzext.vf2 v0, v8
; RV64V-NEXT:    lui a3, 69905
; RV64V-NEXT:    addi a3, a3, 273
; RV64V-NEXT:    vand.vx v8, v0, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v20, v28, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v0, a2
; RV64V-NEXT:    lui a0, 279620
; RV64V-NEXT:    addi a0, a0, 1092
; RV64V-NEXT:    vand.vx v24, v28, a0
; RV64V-NEXT:    vmul.vv v8, v12, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a4, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v20, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a4, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui a1, 559241
; RV64V-NEXT:    addi a1, a1, -1912
; RV64V-NEXT:    vand.vx v4, v0, a1
; RV64V-NEXT:    vmul.vv v8, v24, v4
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v28, v28, a1
; RV64V-NEXT:    vand.vx v0, v0, a0
; RV64V-NEXT:    vmul.vv v8, v28, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v4
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v12, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v28, v16
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vand.vx v12, v12, a2
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v8, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v8, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v20, v0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl4r.v v16, (a2) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl4r.v v12, (a2) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v12, v16
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl4r.v v12, (a2) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v16, v8, v12
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a3, a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v24, v8
; RV64V-NEXT:    vmul.vv v8, v28, v4
; RV64V-NEXT:    vxor.vv v12, v16, v12
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl4r.v v12, (a2) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v12, v0
; RV64V-NEXT:    vmul.vv v20, v20, v4
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vxor.vv v12, v20, v12
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v24, v16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a2, a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v20, v28, v20
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vand.vx v12, v12, a1
; RV64V-NEXT:    vor.vv v12, v8, v12
; RV64V-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v12, 16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i16_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v24, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf4 v16, v8
; RV32ZVBC64-NEXT:    vzext.vf4 v8, v24
; RV32ZVBC64-NEXT:    vclmul.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i16_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v24, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf4 v16, v8
; RV64ZVBC64-NEXT:    vzext.vf4 v8, v24
; RV64ZVBC64-NEXT:    vclmul.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v16, v8, 0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i16_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i16_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
  %va.ext = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>
  %vb.ext = zext <vscale x 8 x i16> %vb to <vscale x 8 x i32>
  %clmul = call <vscale x 8 x i32> @llvm.clmul.nxv8i32(<vscale x 8 x i32> %va.ext, <vscale x 8 x i32> %vb.ext)
  %res.ext = lshr <vscale x 8 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 8 x i32> %res.ext to <vscale x 8 x i16>
  ret <vscale x 8 x i16> %res
}

define <vscale x 16 x i16> @clmulh_nxv16i16_vv(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv16i16_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv4r.v v24, v8
; RV32V-NEXT:    lui a1, 69905
; RV32V-NEXT:    addi a1, a1, 273
; RV32V-NEXT:    vzext.vf2 v16, v12
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v8, v16, a1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vzext.vf2 v8, v24
; RV32V-NEXT:    lui a3, 139810
; RV32V-NEXT:    addi a3, a3, 546
; RV32V-NEXT:    vand.vx v24, v8, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a2, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v24, v16, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a2, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v8, a1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a2, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vand.vx v24, v16, a0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 5
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 6
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v24
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a2, 279620
; RV32V-NEXT:    addi a2, a2, 1092
; RV32V-NEXT:    vand.vx v0, v8, a2
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v16, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vmul.vv v0, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 4
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v0, a1
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v0, v24
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v8, v0
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 6
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a3, a3, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v0
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 5
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v0, v0, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a3, a1
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, a1, a3
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v0, v8, a2
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v8, v0
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vxor.vv v16, v16, v24
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a2, a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v8
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 6
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v0
; RV32V-NEXT:    vxor.vv v16, v16, v24
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v8
; RV32V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v16, 16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv16i16_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; RV64V-NEXT:    vmv4r.v v24, v8
; RV64V-NEXT:    lui a1, 69905
; RV64V-NEXT:    addi a1, a1, 273
; RV64V-NEXT:    vzext.vf2 v16, v12
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v16, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 6
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vzext.vf2 v8, v24
; RV64V-NEXT:    lui a3, 139810
; RV64V-NEXT:    addi a3, a3, 546
; RV64V-NEXT:    vand.vx v24, v8, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v24, v16, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v8, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a0, 559241
; RV64V-NEXT:    addi a0, a0, -1912
; RV64V-NEXT:    vand.vx v24, v16, a0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 5
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 6
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    vand.vx v0, v8, a2
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v16, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vmul.vv v0, v8, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v0, a1
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v0, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v8, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 6
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a3, a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v8, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v8, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vxor.vv v16, v16, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 6
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v0
; RV64V-NEXT:    vxor.vv v16, v16, v24
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v16, 16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv16i16_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a1, a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    sub sp, sp, a0
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; RV32ZVBC64-NEXT:    vmv4r.v v24, v8
; RV32ZVBC64-NEXT:    lui a1, 69905
; RV32ZVBC64-NEXT:    addi a1, a1, 273
; RV32ZVBC64-NEXT:    vzext.vf2 v16, v12
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v8, v16, a1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 6
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v24
; RV32ZVBC64-NEXT:    lui a3, 139810
; RV32ZVBC64-NEXT:    addi a3, a3, 546
; RV32ZVBC64-NEXT:    vand.vx v24, v8, a3
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    mv a2, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a2
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a3
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    mv a2, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a2
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v8, a1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a2, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, a0, a2
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a0, 559241
; RV32ZVBC64-NEXT:    addi a0, a0, -1912
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a0
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 5
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    mv a4, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 2
; RV32ZVBC64-NEXT:    add a2, a2, a4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 6
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a4, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 2
; RV32ZVBC64-NEXT:    add a2, a2, a4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a4, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, a2, a4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    mv a4, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 1
; RV32ZVBC64-NEXT:    add a2, a2, a4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v24
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a4, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 1
; RV32ZVBC64-NEXT:    add a2, a2, a4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a2, 279620
; RV32ZVBC64-NEXT:    addi a2, a2, 1092
; RV32ZVBC64-NEXT:    vand.vx v0, v8, a2
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a5, a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v16, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v16
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 6
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a5, a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v24, v16
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 4
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v0, a1
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 2
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v8, v0, v24
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v0
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v8
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 6
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a3, a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v0
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 5
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 2
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v0, v0, v8
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 2
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a3, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, a1, a3
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v16, v8
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v0, v8, a2
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v0
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 2
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a2, a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 6
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 2
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v0
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a1, a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv16i16_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a1, a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    sub sp, sp, a0
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; RV64ZVBC64-NEXT:    vmv4r.v v24, v8
; RV64ZVBC64-NEXT:    lui a1, 69905
; RV64ZVBC64-NEXT:    addi a1, a1, 273
; RV64ZVBC64-NEXT:    vzext.vf2 v16, v12
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v8, v16, a1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 6
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v24
; RV64ZVBC64-NEXT:    lui a3, 139810
; RV64ZVBC64-NEXT:    addi a3, a3, 546
; RV64ZVBC64-NEXT:    vand.vx v24, v8, a3
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    mv a2, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a2
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a3
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    mv a2, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a2
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v8, a1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a2, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, a0, a2
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a0, 559241
; RV64ZVBC64-NEXT:    addi a0, a0, -1912
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a0
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 5
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    mv a4, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 2
; RV64ZVBC64-NEXT:    add a2, a2, a4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 6
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a4, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 2
; RV64ZVBC64-NEXT:    add a2, a2, a4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a4, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, a2, a4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    mv a4, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 1
; RV64ZVBC64-NEXT:    add a2, a2, a4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v24
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a4, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 1
; RV64ZVBC64-NEXT:    add a2, a2, a4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a2, 279620
; RV64ZVBC64-NEXT:    addi a2, a2, 1092
; RV64ZVBC64-NEXT:    vand.vx v0, v8, a2
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a5, a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v16, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v16
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a5, a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v24, v16
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v8
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 4
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v0, a1
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v0, v24
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v8
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 6
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a3, a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 5
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v0, v0, v8
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a3, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, a1, a3
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v8
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v0, v8, a2
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a2, a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 6
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v0
; RV64ZVBC64-NEXT:    vxor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a1, a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv16i16_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v12
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv16i16_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v12
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 16 x i16> %va to <vscale x 16 x i32>
  %vb.ext = zext <vscale x 16 x i16> %vb to <vscale x 16 x i32>
  %clmul = call <vscale x 16 x i32> @llvm.clmul.nxv16i32(<vscale x 16 x i32> %va.ext, <vscale x 16 x i32> %vb.ext)
  %res.ext = lshr <vscale x 16 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 16 x i32> %res.ext to <vscale x 16 x i16>
  ret <vscale x 16 x i16> %res
}

define <vscale x 16 x i16> @clmulh_nxv16i16_vx(<vscale x 16 x i16> %va, i16 %b) nounwind {
; RV32V-LABEL: clmulh_nxv16i16_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a2, a2, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vzext.vf2 v24, v8
; RV32V-NEXT:    lui a2, 139810
; RV32V-NEXT:    addi a2, a2, 546
; RV32V-NEXT:    vand.vx v8, v24, a2
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 6
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; RV32V-NEXT:    vzext.vf2 v8, v16
; RV32V-NEXT:    lui a3, 69905
; RV32V-NEXT:    addi a3, a3, 273
; RV32V-NEXT:    vand.vx v16, v8, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v24, a3
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v8, a2
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a1, 279620
; RV32V-NEXT:    addi a1, a1, 1092
; RV32V-NEXT:    vand.vx v0, v24, a1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a4, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a4, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a4, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a4, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vand.vx v16, v8, a0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v16, v24, a0
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vmul.vv v24, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v0, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v16, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a4, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v16, v0, a3
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 6
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v8
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v0, v16
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v0, v16
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a3, a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v0
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 5
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v16
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    addi a2, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 6
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v8
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    add a2, sp, a2
; RV32V-NEXT:    addi a2, a2, 16
; RV32V-NEXT:    vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v0, v8, a1
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v8, v0
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vxor.vv v8, v16, v24
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a2, a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 5
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v8
; RV32V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32V-NEXT:    vnsrl.wi v8, v16, 16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv16i16_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV64V-NEXT:    vzext.vf2 v24, v8
; RV64V-NEXT:    lui a2, 139810
; RV64V-NEXT:    addi a2, a2, 546
; RV64V-NEXT:    vand.vx v8, v24, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 6
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64V-NEXT:    vmv.v.x v16, a0
; RV64V-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; RV64V-NEXT:    vzext.vf2 v8, v16
; RV64V-NEXT:    lui a3, 69905
; RV64V-NEXT:    addi a3, a3, 273
; RV64V-NEXT:    vand.vx v16, v8, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v24, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v8, a2
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a1, 279620
; RV64V-NEXT:    addi a1, a1, 1092
; RV64V-NEXT:    vand.vx v0, v24, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a4, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 6
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a4, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a4, a0
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, a0, a4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a4, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a4
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a0, 559241
; RV64V-NEXT:    addi a0, a0, -1912
; RV64V-NEXT:    vand.vx v16, v8, a0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v16, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v24, a0
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vmul.vv v24, v16, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v0
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v24, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v16, v0
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v0, a3
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 6
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v8
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v0, v16
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v16, v0, v16
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a3, a3, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v24, v0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 5
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    addi a2, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 6
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a3, a2
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, a2, a3
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v16
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v8, a1
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v8, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vxor.vv v8, v16, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v24, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v0
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64V-NEXT:    vnsrl.wi v8, v16, 16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv16i16_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a2, a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 2
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    sub sp, sp, a1
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v24, v8
; RV32ZVBC64-NEXT:    lui a2, 139810
; RV32ZVBC64-NEXT:    addi a2, a2, 546
; RV32ZVBC64-NEXT:    vand.vx v8, v24, a2
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 6
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v16, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v16
; RV32ZVBC64-NEXT:    lui a3, 69905
; RV32ZVBC64-NEXT:    addi a3, a3, 273
; RV32ZVBC64-NEXT:    vand.vx v16, v8, a3
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a1, a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v24, a3
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v8, a2
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a1, 279620
; RV32ZVBC64-NEXT:    addi a1, a1, 1092
; RV32ZVBC64-NEXT:    vand.vx v0, v24, a1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    mv a4, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 6
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 5
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    mv a4, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a4, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, a0, a4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a4, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a4
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a0, 559241
; RV32ZVBC64-NEXT:    addi a0, a0, -1912
; RV32ZVBC64-NEXT:    vand.vx v16, v8, a0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v16, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vmul.vv v24, v16, v8
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 6
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a5, a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v0, v24, v8
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v16, v0
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v16, v0
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a4, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 1
; RV32ZVBC64-NEXT:    add a2, a2, a4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v16, v0, a3
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    mv a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 2
; RV32ZVBC64-NEXT:    add a2, a2, a3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 6
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v16, v0
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, a2, a3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v8
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 1
; RV32ZVBC64-NEXT:    add a2, a2, a3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 1
; RV32ZVBC64-NEXT:    add a2, a2, a3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 1
; RV32ZVBC64-NEXT:    add a3, a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 1
; RV32ZVBC64-NEXT:    add a2, a2, a3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v24, v0
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 2
; RV32ZVBC64-NEXT:    add a2, a2, a3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 5
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC64-NEXT:    addi a2, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 6
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    mv a3, a2
; RV32ZVBC64-NEXT:    slli a2, a2, 3
; RV32ZVBC64-NEXT:    add a2, a2, a3
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a2, vlenb
; RV32ZVBC64-NEXT:    slli a2, a2, 4
; RV32ZVBC64-NEXT:    add a2, sp, a2
; RV32ZVBC64-NEXT:    addi a2, a2, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v0, v8, a1
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v0
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v24
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 2
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v24, v16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 3
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a2, a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 5
; RV32ZVBC64-NEXT:    add a1, sp, a1
; RV32ZVBC64-NEXT:    addi a1, a1, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a1, a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv16i16_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a2, a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    sub sp, sp, a1
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v24, v8
; RV64ZVBC64-NEXT:    lui a2, 139810
; RV64ZVBC64-NEXT:    addi a2, a2, 546
; RV64ZVBC64-NEXT:    vand.vx v8, v24, a2
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 6
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v16
; RV64ZVBC64-NEXT:    lui a3, 69905
; RV64ZVBC64-NEXT:    addi a3, a3, 273
; RV64ZVBC64-NEXT:    vand.vx v16, v8, a3
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a1, a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v24, a3
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v8, a2
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a1, 279620
; RV64ZVBC64-NEXT:    addi a1, a1, 1092
; RV64ZVBC64-NEXT:    vand.vx v0, v24, a1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    mv a4, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 6
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 5
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 4
; RV64ZVBC64-NEXT:    mv a4, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a4, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, a0, a4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a4, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a0, a0, a4
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a0, 559241
; RV64ZVBC64-NEXT:    addi a0, a0, -1912
; RV64ZVBC64-NEXT:    vand.vx v16, v8, a0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v16, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vmul.vv v24, v16, v8
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v24, v0
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a5, a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v0, v24, v8
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v0
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v16, v0
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a4, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 1
; RV64ZVBC64-NEXT:    add a2, a2, a4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v16, v0, a3
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    mv a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 2
; RV64ZVBC64-NEXT:    add a2, a2, a3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 6
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v0
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, a2, a3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v8
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 1
; RV64ZVBC64-NEXT:    add a2, a2, a3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 1
; RV64ZVBC64-NEXT:    add a2, a2, a3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 1
; RV64ZVBC64-NEXT:    add a3, a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 1
; RV64ZVBC64-NEXT:    add a2, a2, a3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v24, v0
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 2
; RV64ZVBC64-NEXT:    add a2, a2, a3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 5
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV64ZVBC64-NEXT:    addi a2, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 6
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    mv a3, a2
; RV64ZVBC64-NEXT:    slli a2, a2, 3
; RV64ZVBC64-NEXT:    add a2, a2, a3
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a2, vlenb
; RV64ZVBC64-NEXT:    slli a2, a2, 4
; RV64ZVBC64-NEXT:    add a2, sp, a2
; RV64ZVBC64-NEXT:    addi a2, a2, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v0, v8, a1
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vxor.vv v8, v16, v24
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 4
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v24, v16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a2, a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 5
; RV64ZVBC64-NEXT:    add a1, sp, a1
; RV64ZVBC64-NEXT:    addi a1, a1, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v24, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add a0, sp, a0
; RV64ZVBC64-NEXT:    addi a0, a0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wi v8, v16, 16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a1, a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv16i16_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv16i16_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
  %va.ext = zext <vscale x 16 x i16> %va to <vscale x 16 x i32>
  %vb.ext = zext <vscale x 16 x i16> %vb to <vscale x 16 x i32>
  %clmul = call <vscale x 16 x i32> @llvm.clmul.nxv16i32(<vscale x 16 x i32> %va.ext, <vscale x 16 x i32> %vb.ext)
  %res.ext = lshr <vscale x 16 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 16 x i32> %res.ext to <vscale x 16 x i16>
  ret <vscale x 16 x i16> %res
}

define <vscale x 32 x i16> @clmulh_nxv32i16_vv(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv32i16_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    lui a3, 1
; RV32V-NEXT:    addi a0, a3, -241
; RV32V-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV32V-NEXT:    vsrl.vi v24, v8, 8
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vsrl.vi v24, v8, 4
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 2
; RV32V-NEXT:    lui a1, 3
; RV32V-NEXT:    addi a1, a1, 819
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 1
; RV32V-NEXT:    lui a2, 5
; RV32V-NEXT:    addi a2, a2, 1365
; RV32V-NEXT:    vand.vx v24, v24, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v16, 8
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsrl.vi v24, v16, 4
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vsll.vi v16, v16, 4
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 2
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 1
; RV32V-NEXT:    vand.vx v24, v24, a2
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vadd.vv v16, v16, v16
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vand.vi v24, v16, 2
; RV32V-NEXT:    vand.vi v0, v16, 1
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v0, v16, 4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v24, v16, 8
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 16
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 32
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 64
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 128
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 256
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 512
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 1024
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 1
; RV32V-NEXT:    slli a4, a4, 11
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v16, a3
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 3
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a3, 2
; RV32V-NEXT:    vand.vx v24, v16, a3
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    addi a3, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 4
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 3
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a3, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    lui a3, 4
; RV32V-NEXT:    vand.vx v0, v16, a3
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    lui a3, 8
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v16, v24, v0
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 3
; RV32V-NEXT:    mv a4, a3
; RV32V-NEXT:    slli a3, a3, 1
; RV32V-NEXT:    add a3, a3, a4
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vsrl.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv32i16_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    lui a3, 1
; RV64V-NEXT:    addi a0, a3, -241
; RV64V-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV64V-NEXT:    vsrl.vi v24, v8, 8
; RV64V-NEXT:    vsll.vi v8, v8, 8
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    vsrl.vi v24, v8, 4
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v8, 2
; RV64V-NEXT:    lui a1, 3
; RV64V-NEXT:    addi a1, a1, 819
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v8, 1
; RV64V-NEXT:    lui a2, 5
; RV64V-NEXT:    addi a2, a2, 1365
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v16, 8
; RV64V-NEXT:    vsll.vi v16, v16, 8
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsrl.vi v24, v16, 4
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsll.vi v16, v16, 4
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 2
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vsll.vi v16, v16, 2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 1
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vadd.vv v16, v16, v16
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vi v24, v16, 2
; RV64V-NEXT:    vand.vi v0, v16, 1
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v0, v16, 4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v24, v16, 8
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 16
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 32
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 64
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 128
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 256
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 512
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 1024
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 1
; RV64V-NEXT:    slli a4, a4, 11
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v16, a3
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 3
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a3, 2
; RV64V-NEXT:    vand.vx v24, v16, a3
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    addi a3, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 3
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a3, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    lui a3, 4
; RV64V-NEXT:    vand.vx v0, v16, a3
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    lui a3, 8
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    vxor.vv v16, v24, v0
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 3
; RV64V-NEXT:    mv a4, a3
; RV64V-NEXT:    slli a3, a3, 1
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vsll.vi v16, v16, 8
; RV64V-NEXT:    vsrl.vi v8, v8, 8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv32i16_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 5
; RV32ZVBC64-NEXT:    sub sp, sp, a0
; RV32ZVBC64-NEXT:    lui a3, 1
; RV32ZVBC64-NEXT:    addi a0, a3, -241
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 8
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 4
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV32ZVBC64-NEXT:    lui a1, 3
; RV32ZVBC64-NEXT:    addi a1, a1, 819
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV32ZVBC64-NEXT:    lui a2, 5
; RV32ZVBC64-NEXT:    addi a2, a2, 1365
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 4
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 16
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 32
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 64
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 128
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 256
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 512
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 1024
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 1
; RV32ZVBC64-NEXT:    slli a4, a4, 11
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 3
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a3, 2
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    addi a3, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 4
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 3
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a3, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    lui a3, 4
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    lui a3, 8
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 3
; RV32ZVBC64-NEXT:    mv a4, a3
; RV32ZVBC64-NEXT:    slli a3, a3, 1
; RV32ZVBC64-NEXT:    add a3, a3, a4
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 5
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv32i16_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 5
; RV64ZVBC64-NEXT:    sub sp, sp, a0
; RV64ZVBC64-NEXT:    lui a3, 1
; RV64ZVBC64-NEXT:    addi a0, a3, -241
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 8
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 4
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV64ZVBC64-NEXT:    lui a1, 3
; RV64ZVBC64-NEXT:    addi a1, a1, 819
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV64ZVBC64-NEXT:    lui a2, 5
; RV64ZVBC64-NEXT:    addi a2, a2, 1365
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 4
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 16
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 32
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 64
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 128
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 256
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 512
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 1024
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 1
; RV64ZVBC64-NEXT:    slli a4, a4, 11
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 3
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a3, 2
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    addi a3, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 4
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 3
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a3, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    lui a3, 4
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    lui a3, 8
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 3
; RV64ZVBC64-NEXT:    mv a4, a3
; RV64ZVBC64-NEXT:    slli a3, a3, 1
; RV64ZVBC64-NEXT:    add a3, a3, a4
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 5
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv32i16_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv32i16_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v16
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 32 x i16> %va to <vscale x 32 x i32>
  %vb.ext = zext <vscale x 32 x i16> %vb to <vscale x 32 x i32>
  %clmul = call <vscale x 32 x i32> @llvm.clmul.nxv32i32(<vscale x 32 x i32> %va.ext, <vscale x 32 x i32> %vb.ext)
  %res.ext = lshr <vscale x 32 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 32 x i32> %res.ext to <vscale x 32 x i16>
  ret <vscale x 32 x i16> %res
}

define <vscale x 32 x i16> @clmulh_nxv32i16_vx(<vscale x 32 x i16> %va, i16 %b) nounwind {
; RV32V-LABEL: clmulh_nxv32i16_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 5
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsrl.vi v24, v8, 8
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vsrl.vi v24, v8, 4
; RV32V-NEXT:    lui a3, 1
; RV32V-NEXT:    addi a0, a3, -241
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 2
; RV32V-NEXT:    lui a1, 3
; RV32V-NEXT:    addi a1, a1, 819
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 1
; RV32V-NEXT:    lui a2, 5
; RV32V-NEXT:    addi a2, a2, 1365
; RV32V-NEXT:    vand.vx v24, v24, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v16, 8
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsrl.vi v24, v16, 4
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vsll.vi v16, v16, 4
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 2
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 1
; RV32V-NEXT:    vand.vx v24, v24, a2
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vadd.vv v16, v16, v16
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vand.vi v24, v16, 2
; RV32V-NEXT:    vand.vi v0, v16, 1
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v0, v16, 4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vi v24, v16, 8
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 16
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 32
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 64
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 128
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 256
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 512
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 1024
; RV32V-NEXT:    vand.vx v24, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    li a4, 1
; RV32V-NEXT:    slli a4, a4, 11
; RV32V-NEXT:    vand.vx v0, v16, a4
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v16, a3
; RV32V-NEXT:    vmul.vv v24, v8, v0
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 3
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a3, 2
; RV32V-NEXT:    vand.vx v24, v16, a3
; RV32V-NEXT:    vmul.vv v24, v8, v24
; RV32V-NEXT:    addi a3, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 4
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 3
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    addi a3, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    lui a3, 4
; RV32V-NEXT:    vand.vx v0, v16, a3
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    lui a3, 8
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v16, v24, v0
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 3
; RV32V-NEXT:    mv a4, a3
; RV32V-NEXT:    slli a3, a3, 1
; RV32V-NEXT:    add a3, a3, a4
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vsrl.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv32i16_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV64V-NEXT:    vmv.v.x v16, a0
; RV64V-NEXT:    vsrl.vi v24, v8, 8
; RV64V-NEXT:    vsll.vi v8, v8, 8
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    vsrl.vi v24, v8, 4
; RV64V-NEXT:    lui a3, 1
; RV64V-NEXT:    addi a0, a3, -241
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v8, 2
; RV64V-NEXT:    lui a1, 3
; RV64V-NEXT:    addi a1, a1, 819
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v8, 1
; RV64V-NEXT:    lui a2, 5
; RV64V-NEXT:    addi a2, a2, 1365
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vi v24, v16, 8
; RV64V-NEXT:    vsll.vi v16, v16, 8
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsrl.vi v24, v16, 4
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsll.vi v16, v16, 4
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 2
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vsll.vi v16, v16, 2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 1
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vadd.vv v16, v16, v16
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vi v24, v16, 2
; RV64V-NEXT:    vand.vi v0, v16, 1
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v0, v16, 4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vi v24, v16, 8
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 16
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 32
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 64
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 128
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 256
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 512
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 1024
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    li a4, 1
; RV64V-NEXT:    slli a4, a4, 11
; RV64V-NEXT:    vand.vx v0, v16, a4
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v16, a3
; RV64V-NEXT:    vmul.vv v24, v8, v0
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 3
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a3, 2
; RV64V-NEXT:    vand.vx v24, v16, a3
; RV64V-NEXT:    vmul.vv v24, v8, v24
; RV64V-NEXT:    addi a3, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 3
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    addi a3, sp, 16
; RV64V-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v0, v24
; RV64V-NEXT:    lui a3, 4
; RV64V-NEXT:    vand.vx v0, v16, a3
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    lui a3, 8
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    vxor.vv v16, v24, v0
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 3
; RV64V-NEXT:    mv a4, a3
; RV64V-NEXT:    slli a3, a3, 1
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vsll.vi v16, v16, 8
; RV64V-NEXT:    vsrl.vi v8, v8, 8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv32i16_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 5
; RV32ZVBC64-NEXT:    sub sp, sp, a1
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v16, a0
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 8
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 4
; RV32ZVBC64-NEXT:    lui a3, 1
; RV32ZVBC64-NEXT:    addi a0, a3, -241
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV32ZVBC64-NEXT:    lui a1, 3
; RV32ZVBC64-NEXT:    addi a1, a1, 819
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV32ZVBC64-NEXT:    lui a2, 5
; RV32ZVBC64-NEXT:    addi a2, a2, 1365
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 4
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 16
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 32
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 64
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 128
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 256
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 512
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 1024
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    li a4, 1
; RV32ZVBC64-NEXT:    slli a4, a4, 11
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    addi a4, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 3
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a3, 2
; RV32ZVBC64-NEXT:    vand.vx v24, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV32ZVBC64-NEXT:    addi a3, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 4
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 3
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    addi a3, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC64-NEXT:    lui a3, 4
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    lui a3, 8
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr a3, vlenb
; RV32ZVBC64-NEXT:    slli a3, a3, 3
; RV32ZVBC64-NEXT:    mv a4, a3
; RV32ZVBC64-NEXT:    slli a3, a3, 1
; RV32ZVBC64-NEXT:    add a3, a3, a4
; RV32ZVBC64-NEXT:    add a3, sp, a3
; RV32ZVBC64-NEXT:    addi a3, a3, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 5
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv32i16_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 5
; RV64ZVBC64-NEXT:    sub sp, sp, a1
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 8
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 4
; RV64ZVBC64-NEXT:    lui a3, 1
; RV64ZVBC64-NEXT:    addi a0, a3, -241
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 2
; RV64ZVBC64-NEXT:    lui a1, 3
; RV64ZVBC64-NEXT:    addi a1, a1, 819
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 1
; RV64ZVBC64-NEXT:    lui a2, 5
; RV64ZVBC64-NEXT:    addi a2, a2, 1365
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 4
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 2
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 1
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v0, v16, 4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 16
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 32
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 64
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 128
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 256
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 512
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 1024
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    li a4, 1
; RV64ZVBC64-NEXT:    slli a4, a4, 11
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    addi a4, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v0
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 3
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a3, 2
; RV64ZVBC64-NEXT:    vand.vx v24, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v24, v8, v24
; RV64ZVBC64-NEXT:    addi a3, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 4
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 3
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    addi a3, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v0, v24
; RV64ZVBC64-NEXT:    lui a3, 4
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    lui a3, 8
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vxor.vv v16, v24, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    csrr a3, vlenb
; RV64ZVBC64-NEXT:    slli a3, a3, 3
; RV64ZVBC64-NEXT:    mv a4, a3
; RV64ZVBC64-NEXT:    slli a3, a3, 1
; RV64ZVBC64-NEXT:    add a3, a3, a4
; RV64ZVBC64-NEXT:    add a3, sp, a3
; RV64ZVBC64-NEXT:    addi a3, a3, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 5
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv32i16_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv32i16_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
  %va.ext = zext <vscale x 32 x i16> %va to <vscale x 32 x i32>
  %vb.ext = zext <vscale x 32 x i16> %vb to <vscale x 32 x i32>
  %clmul = call <vscale x 32 x i32> @llvm.clmul.nxv32i32(<vscale x 32 x i32> %va.ext, <vscale x 32 x i32> %vb.ext)
  %res.ext = lshr <vscale x 32 x i32> %clmul, splat(i32 16)
  %res = trunc <vscale x 32 x i32> %res.ext to <vscale x 32 x i16>
  ret <vscale x 32 x i16> %res
}

define <vscale x 1 x i32> @clmulh_nxv1i32_vv(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv1i32_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v10, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vzext.vf2 v11, v9
; RV32V-NEXT:    vzext.vf2 v9, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v12, v11, v10
; RV32V-NEXT:    vand.vv v13, v9, v8
; RV32V-NEXT:    vand.vv v14, v11, v8
; RV32V-NEXT:    vand.vv v15, v9, v10
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vmul.vv v17, v13, v12
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    vmul.vv v18, v15, v14
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v19, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v20, v11, v16
; RV32V-NEXT:    vand.vv v21, v9, v19
; RV32V-NEXT:    vxor.vv v17, v18, v17
; RV32V-NEXT:    vmul.vv v18, v21, v20
; RV32V-NEXT:    vand.vv v11, v11, v19
; RV32V-NEXT:    vand.vv v9, v9, v16
; RV32V-NEXT:    vmul.vv v22, v13, v20
; RV32V-NEXT:    vmul.vv v23, v15, v12
; RV32V-NEXT:    vxor.vv v17, v17, v18
; RV32V-NEXT:    vmul.vv v18, v9, v11
; RV32V-NEXT:    vmul.vv v24, v21, v11
; RV32V-NEXT:    vxor.vv v22, v23, v22
; RV32V-NEXT:    vmul.vv v23, v9, v14
; RV32V-NEXT:    vxor.vv v17, v17, v18
; RV32V-NEXT:    vxor.vv v18, v22, v24
; RV32V-NEXT:    vand.vv v8, v17, v8
; RV32V-NEXT:    vxor.vv v17, v18, v23
; RV32V-NEXT:    vmul.vv v18, v13, v14
; RV32V-NEXT:    vmul.vv v22, v15, v11
; RV32V-NEXT:    vand.vv v10, v17, v10
; RV32V-NEXT:    vmul.vv v17, v21, v12
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vxor.vv v10, v22, v18
; RV32V-NEXT:    vmul.vv v11, v13, v11
; RV32V-NEXT:    vmul.vv v13, v15, v20
; RV32V-NEXT:    vxor.vv v10, v10, v17
; RV32V-NEXT:    vmul.vv v15, v9, v20
; RV32V-NEXT:    vmul.vv v14, v21, v14
; RV32V-NEXT:    vxor.vv v11, v13, v11
; RV32V-NEXT:    vmul.vv v9, v9, v12
; RV32V-NEXT:    vxor.vv v10, v10, v15
; RV32V-NEXT:    vxor.vv v11, v11, v14
; RV32V-NEXT:    vand.vv v10, v10, v19
; RV32V-NEXT:    vxor.vv v9, v11, v9
; RV32V-NEXT:    vor.vv v8, v8, v10
; RV32V-NEXT:    vand.vv v9, v9, v16
; RV32V-NEXT:    vor.vv v8, v8, v9
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v8, a0
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i32_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v9
; RV64V-NEXT:    lui a1, 139810
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    slli a2, a0, 32
; RV64V-NEXT:    vzext.vf2 v9, v8
; RV64V-NEXT:    addi a1, a1, 546
; RV64V-NEXT:    add a2, a0, a2
; RV64V-NEXT:    slli a0, a1, 32
; RV64V-NEXT:    vand.vx v8, v10, a2
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    vand.vx v11, v9, a1
; RV64V-NEXT:    vand.vx v12, v10, a1
; RV64V-NEXT:    vand.vx v13, v9, a2
; RV64V-NEXT:    lui a0, %hi(.LCPI26_0)
; RV64V-NEXT:    ld a0, %lo(.LCPI26_0)(a0)
; RV64V-NEXT:    vmul.vv v14, v11, v8
; RV64V-NEXT:    vmul.vv v15, v13, v12
; RV64V-NEXT:    lui a3, 279620
; RV64V-NEXT:    addi a3, a3, 1092
; RV64V-NEXT:    slli a4, a3, 32
; RV64V-NEXT:    vand.vx v16, v10, a0
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    vand.vx v17, v9, a3
; RV64V-NEXT:    vxor.vv v14, v15, v14
; RV64V-NEXT:    vmul.vv v15, v17, v16
; RV64V-NEXT:    vand.vx v9, v9, a0
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vmul.vv v18, v11, v16
; RV64V-NEXT:    vmul.vv v19, v13, v8
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vmul.vv v15, v9, v10
; RV64V-NEXT:    vmul.vv v20, v17, v10
; RV64V-NEXT:    vxor.vv v18, v19, v18
; RV64V-NEXT:    vmul.vv v19, v9, v12
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vxor.vv v15, v18, v20
; RV64V-NEXT:    vand.vx v14, v14, a1
; RV64V-NEXT:    vxor.vv v15, v15, v19
; RV64V-NEXT:    vmul.vv v18, v11, v12
; RV64V-NEXT:    vmul.vv v19, v13, v10
; RV64V-NEXT:    vand.vx v15, v15, a2
; RV64V-NEXT:    vmul.vv v20, v17, v8
; RV64V-NEXT:    vor.vv v14, v15, v14
; RV64V-NEXT:    vxor.vv v15, v19, v18
; RV64V-NEXT:    vmul.vv v10, v11, v10
; RV64V-NEXT:    vmul.vv v11, v13, v16
; RV64V-NEXT:    vxor.vv v13, v15, v20
; RV64V-NEXT:    vmul.vv v15, v9, v16
; RV64V-NEXT:    vmul.vv v12, v17, v12
; RV64V-NEXT:    vxor.vv v10, v11, v10
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vxor.vv v9, v13, v15
; RV64V-NEXT:    vxor.vv v10, v10, v12
; RV64V-NEXT:    vand.vx v9, v9, a3
; RV64V-NEXT:    vxor.vv v8, v10, v8
; RV64V-NEXT:    vor.vv v9, v14, v9
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v8, a0
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i32_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v10, v9
; RV32ZVBC64-NEXT:    vzext.vf2 v9, v8
; RV32ZVBC64-NEXT:    vclmul.vv v8, v9, v10
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v8, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i32_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v10, v9
; RV64ZVBC64-NEXT:    vzext.vf2 v9, v8
; RV64ZVBC64-NEXT:    vclmul.vv v8, v9, v10
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v8, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i32_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i32_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
  %vb.ext = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
  %clmul = call <vscale x 1 x i64> @llvm.clmul.nxv1i64(<vscale x 1 x i64> %va.ext, <vscale x 1 x i64> %vb.ext)
  %res.ext = lshr <vscale x 1 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 1 x i64> %res.ext to <vscale x 1 x i32>
  ret <vscale x 1 x i32> %res
}

define <vscale x 1 x i32> @clmulh_nxv1i32_vx(<vscale x 1 x i32> %va, i32 %b) nounwind {
; RV32V-LABEL: clmulh_nxv1i32_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a0
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v10, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vzext.vf2 v11, v9
; RV32V-NEXT:    vzext.vf2 v9, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v12, v11, v10
; RV32V-NEXT:    vand.vv v13, v9, v8
; RV32V-NEXT:    vand.vv v14, v11, v8
; RV32V-NEXT:    vand.vv v15, v9, v10
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vmul.vv v17, v13, v12
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    vmul.vv v18, v15, v14
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v19, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v20, v11, v16
; RV32V-NEXT:    vand.vv v21, v9, v19
; RV32V-NEXT:    vxor.vv v17, v18, v17
; RV32V-NEXT:    vmul.vv v18, v21, v20
; RV32V-NEXT:    vand.vv v11, v11, v19
; RV32V-NEXT:    vand.vv v9, v9, v16
; RV32V-NEXT:    vmul.vv v22, v13, v20
; RV32V-NEXT:    vmul.vv v23, v15, v12
; RV32V-NEXT:    vxor.vv v17, v17, v18
; RV32V-NEXT:    vmul.vv v18, v9, v11
; RV32V-NEXT:    vmul.vv v24, v21, v11
; RV32V-NEXT:    vxor.vv v22, v23, v22
; RV32V-NEXT:    vmul.vv v23, v9, v14
; RV32V-NEXT:    vxor.vv v17, v17, v18
; RV32V-NEXT:    vxor.vv v18, v22, v24
; RV32V-NEXT:    vand.vv v8, v17, v8
; RV32V-NEXT:    vxor.vv v17, v18, v23
; RV32V-NEXT:    vmul.vv v18, v13, v14
; RV32V-NEXT:    vmul.vv v22, v15, v11
; RV32V-NEXT:    vand.vv v10, v17, v10
; RV32V-NEXT:    vmul.vv v17, v21, v12
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vxor.vv v10, v22, v18
; RV32V-NEXT:    vmul.vv v11, v13, v11
; RV32V-NEXT:    vmul.vv v13, v15, v20
; RV32V-NEXT:    vxor.vv v10, v10, v17
; RV32V-NEXT:    vmul.vv v15, v9, v20
; RV32V-NEXT:    vmul.vv v14, v21, v14
; RV32V-NEXT:    vxor.vv v11, v13, v11
; RV32V-NEXT:    vmul.vv v9, v9, v12
; RV32V-NEXT:    vxor.vv v10, v10, v15
; RV32V-NEXT:    vxor.vv v11, v11, v14
; RV32V-NEXT:    vand.vv v10, v10, v19
; RV32V-NEXT:    vxor.vv v9, v11, v9
; RV32V-NEXT:    vor.vv v8, v8, v10
; RV32V-NEXT:    vand.vv v9, v9, v16
; RV32V-NEXT:    vor.vv v8, v8, v9
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v8, a0
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i32_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
; RV64V-NEXT:    vmv.v.x v9, a0
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV64V-NEXT:    vzext.vf2 v10, v8
; RV64V-NEXT:    lui a1, 69905
; RV64V-NEXT:    addi a0, a0, 546
; RV64V-NEXT:    slli a2, a0, 32
; RV64V-NEXT:    vzext.vf2 v8, v9
; RV64V-NEXT:    addi a1, a1, 273
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    slli a2, a1, 32
; RV64V-NEXT:    vand.vx v9, v10, a0
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    vand.vx v11, v8, a1
; RV64V-NEXT:    vand.vx v12, v8, a0
; RV64V-NEXT:    vand.vx v13, v10, a1
; RV64V-NEXT:    vmul.vv v14, v9, v11
; RV64V-NEXT:    vmul.vv v15, v13, v12
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    lui a3, %hi(.LCPI27_0)
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    ld a3, %lo(.LCPI27_0)(a3)
; RV64V-NEXT:    slli a4, a2, 32
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    vand.vx v16, v10, a2
; RV64V-NEXT:    vand.vx v17, v8, a3
; RV64V-NEXT:    vxor.vv v14, v15, v14
; RV64V-NEXT:    vmul.vv v15, v16, v17
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vmul.vv v18, v9, v17
; RV64V-NEXT:    vmul.vv v19, v13, v11
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vmul.vv v15, v10, v8
; RV64V-NEXT:    vmul.vv v20, v16, v8
; RV64V-NEXT:    vxor.vv v18, v19, v18
; RV64V-NEXT:    vmul.vv v19, v10, v12
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vxor.vv v15, v18, v20
; RV64V-NEXT:    vand.vx v14, v14, a0
; RV64V-NEXT:    vxor.vv v15, v15, v19
; RV64V-NEXT:    vmul.vv v18, v9, v12
; RV64V-NEXT:    vmul.vv v19, v13, v8
; RV64V-NEXT:    vand.vx v15, v15, a1
; RV64V-NEXT:    vmul.vv v20, v16, v11
; RV64V-NEXT:    vor.vv v14, v15, v14
; RV64V-NEXT:    vxor.vv v15, v19, v18
; RV64V-NEXT:    vmul.vv v8, v9, v8
; RV64V-NEXT:    vmul.vv v9, v13, v17
; RV64V-NEXT:    vxor.vv v13, v15, v20
; RV64V-NEXT:    vmul.vv v15, v10, v17
; RV64V-NEXT:    vmul.vv v12, v16, v12
; RV64V-NEXT:    vxor.vv v8, v9, v8
; RV64V-NEXT:    vmul.vv v9, v10, v11
; RV64V-NEXT:    vxor.vv v10, v13, v15
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    vand.vx v10, v10, a2
; RV64V-NEXT:    vxor.vv v8, v8, v9
; RV64V-NEXT:    vor.vv v9, v14, v10
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v8, a0
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i32_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v9, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v10, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v9
; RV32ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v8, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i32_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v9, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v10, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v9
; RV64ZVBC64-NEXT:    vclmul.vv v8, v10, v8
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v8, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i32_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i32_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i64 0
  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
  %va.ext = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
  %vb.ext = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
  %clmul = call <vscale x 1 x i64> @llvm.clmul.nxv1i64(<vscale x 1 x i64> %va.ext, <vscale x 1 x i64> %vb.ext)
  %res.ext = lshr <vscale x 1 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 1 x i64> %res.ext to <vscale x 1 x i32>
  ret <vscale x 1 x i32> %res
}

define <vscale x 2 x i32> @clmulh_nxv2i32_vv(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv2i32_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v18, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vzext.vf2 v24, v9
; RV32V-NEXT:    vand.vv v10, v24, v18
; RV32V-NEXT:    vzext.vf2 v26, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v28, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v12, v26, v28
; RV32V-NEXT:    vand.vv v8, v24, v28
; RV32V-NEXT:    vand.vv v16, v26, v18
; RV32V-NEXT:    vmul.vv v14, v12, v10
; RV32V-NEXT:    vmul.vv v20, v16, v8
; RV32V-NEXT:    vxor.vv v30, v20, v14
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v14, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v20, v24, v14
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v6, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v22, v26, v6
; RV32V-NEXT:    vand.vv v4, v24, v6
; RV32V-NEXT:    vmul.vv v2, v22, v20
; RV32V-NEXT:    vand.vv v24, v26, v14
; RV32V-NEXT:    vmul.vv v26, v24, v4
; RV32V-NEXT:    vxor.vv v30, v30, v2
; RV32V-NEXT:    vxor.vv v26, v30, v26
; RV32V-NEXT:    vmul.vv v30, v12, v20
; RV32V-NEXT:    vmul.vv v2, v16, v10
; RV32V-NEXT:    vand.vv v26, v26, v28
; RV32V-NEXT:    vxor.vv v28, v2, v30
; RV32V-NEXT:    vmul.vv v30, v22, v4
; RV32V-NEXT:    vmul.vv v2, v24, v8
; RV32V-NEXT:    vxor.vv v28, v28, v30
; RV32V-NEXT:    vxor.vv v28, v28, v2
; RV32V-NEXT:    vand.vv v18, v28, v18
; RV32V-NEXT:    vmul.vv v28, v12, v8
; RV32V-NEXT:    vmul.vv v30, v16, v4
; RV32V-NEXT:    vor.vv v18, v18, v26
; RV32V-NEXT:    vxor.vv v26, v30, v28
; RV32V-NEXT:    vmul.vv v28, v22, v10
; RV32V-NEXT:    vmul.vv v30, v24, v20
; RV32V-NEXT:    vxor.vv v26, v26, v28
; RV32V-NEXT:    vxor.vv v26, v26, v30
; RV32V-NEXT:    vand.vv v26, v26, v6
; RV32V-NEXT:    vmul.vv v12, v12, v4
; RV32V-NEXT:    vmul.vv v16, v16, v20
; RV32V-NEXT:    vor.vv v18, v18, v26
; RV32V-NEXT:    vxor.vv v12, v16, v12
; RV32V-NEXT:    vmul.vv v8, v22, v8
; RV32V-NEXT:    vmul.vv v10, v24, v10
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    vxor.vv v8, v8, v10
; RV32V-NEXT:    vand.vv v8, v8, v14
; RV32V-NEXT:    vor.vv v10, v18, v8
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v10, a0
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i32_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    slli a1, a0, 32
; RV64V-NEXT:    vsetvli a2, zero, e64, m2, ta, ma
; RV64V-NEXT:    vzext.vf2 v22, v9
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    vand.vx v10, v22, a0
; RV64V-NEXT:    vzext.vf2 v20, v8
; RV64V-NEXT:    lui a1, 139810
; RV64V-NEXT:    addi a1, a1, 546
; RV64V-NEXT:    slli a2, a1, 32
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    vand.vx v12, v20, a1
; RV64V-NEXT:    vand.vx v8, v22, a1
; RV64V-NEXT:    vand.vx v14, v20, a0
; RV64V-NEXT:    vmul.vv v16, v12, v10
; RV64V-NEXT:    vmul.vv v18, v14, v8
; RV64V-NEXT:    lui a2, %hi(.LCPI28_0)
; RV64V-NEXT:    vxor.vv v24, v18, v16
; RV64V-NEXT:    ld a2, %lo(.LCPI28_0)(a2)
; RV64V-NEXT:    vand.vx v16, v22, a2
; RV64V-NEXT:    lui a3, 279620
; RV64V-NEXT:    addi a3, a3, 1092
; RV64V-NEXT:    slli a4, a3, 32
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    vand.vx v18, v20, a3
; RV64V-NEXT:    vand.vx v20, v20, a2
; RV64V-NEXT:    vmul.vv v26, v18, v16
; RV64V-NEXT:    vand.vx v22, v22, a3
; RV64V-NEXT:    vmul.vv v28, v20, v22
; RV64V-NEXT:    vxor.vv v24, v24, v26
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vmul.vv v26, v12, v16
; RV64V-NEXT:    vmul.vv v28, v14, v10
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vxor.vv v26, v28, v26
; RV64V-NEXT:    vmul.vv v28, v18, v22
; RV64V-NEXT:    vmul.vv v30, v20, v8
; RV64V-NEXT:    vxor.vv v26, v26, v28
; RV64V-NEXT:    vxor.vv v26, v26, v30
; RV64V-NEXT:    vand.vx v26, v26, a0
; RV64V-NEXT:    vmul.vv v28, v12, v8
; RV64V-NEXT:    vmul.vv v30, v14, v22
; RV64V-NEXT:    vor.vv v24, v26, v24
; RV64V-NEXT:    vxor.vv v26, v30, v28
; RV64V-NEXT:    vmul.vv v28, v18, v10
; RV64V-NEXT:    vmul.vv v30, v20, v16
; RV64V-NEXT:    vxor.vv v26, v26, v28
; RV64V-NEXT:    vxor.vv v26, v26, v30
; RV64V-NEXT:    vand.vx v26, v26, a3
; RV64V-NEXT:    vmul.vv v12, v12, v22
; RV64V-NEXT:    vmul.vv v14, v14, v16
; RV64V-NEXT:    vor.vv v16, v24, v26
; RV64V-NEXT:    vxor.vv v12, v14, v12
; RV64V-NEXT:    vmul.vv v8, v18, v8
; RV64V-NEXT:    vmul.vv v10, v20, v10
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    vxor.vv v8, v8, v10
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v10, v16, v8
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v10, a0
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i32_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v10, v9
; RV32ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV32ZVBC64-NEXT:    vclmul.vv v10, v12, v10
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v10, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i32_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v10, v9
; RV64ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV64ZVBC64-NEXT:    vclmul.vv v10, v12, v10
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v10, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i32_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i32_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
  %vb.ext = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
  %clmul = call <vscale x 2 x i64> @llvm.clmul.nxv2i64(<vscale x 2 x i64> %va.ext, <vscale x 2 x i64> %vb.ext)
  %res.ext = lshr <vscale x 2 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 2 x i64> %res.ext to <vscale x 2 x i32>
  ret <vscale x 2 x i32> %res
}

define <vscale x 2 x i32> @clmulh_nxv2i32_vx(<vscale x 2 x i32> %va, i32 %b) nounwind {
; RV32V-LABEL: clmulh_nxv2i32_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a0
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v18, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vzext.vf2 v24, v9
; RV32V-NEXT:    vand.vv v10, v24, v18
; RV32V-NEXT:    vzext.vf2 v26, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v28, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v12, v26, v28
; RV32V-NEXT:    vand.vv v8, v24, v28
; RV32V-NEXT:    vand.vv v16, v26, v18
; RV32V-NEXT:    vmul.vv v14, v12, v10
; RV32V-NEXT:    vmul.vv v20, v16, v8
; RV32V-NEXT:    vxor.vv v30, v20, v14
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v14, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v20, v24, v14
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v6, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v22, v26, v6
; RV32V-NEXT:    vand.vv v4, v24, v6
; RV32V-NEXT:    vmul.vv v2, v22, v20
; RV32V-NEXT:    vand.vv v24, v26, v14
; RV32V-NEXT:    vmul.vv v26, v24, v4
; RV32V-NEXT:    vxor.vv v30, v30, v2
; RV32V-NEXT:    vxor.vv v26, v30, v26
; RV32V-NEXT:    vmul.vv v30, v12, v20
; RV32V-NEXT:    vmul.vv v2, v16, v10
; RV32V-NEXT:    vand.vv v26, v26, v28
; RV32V-NEXT:    vxor.vv v28, v2, v30
; RV32V-NEXT:    vmul.vv v30, v22, v4
; RV32V-NEXT:    vmul.vv v2, v24, v8
; RV32V-NEXT:    vxor.vv v28, v28, v30
; RV32V-NEXT:    vxor.vv v28, v28, v2
; RV32V-NEXT:    vand.vv v18, v28, v18
; RV32V-NEXT:    vmul.vv v28, v12, v8
; RV32V-NEXT:    vmul.vv v30, v16, v4
; RV32V-NEXT:    vor.vv v18, v18, v26
; RV32V-NEXT:    vxor.vv v26, v30, v28
; RV32V-NEXT:    vmul.vv v28, v22, v10
; RV32V-NEXT:    vmul.vv v30, v24, v20
; RV32V-NEXT:    vxor.vv v26, v26, v28
; RV32V-NEXT:    vxor.vv v26, v26, v30
; RV32V-NEXT:    vand.vv v26, v26, v6
; RV32V-NEXT:    vmul.vv v12, v12, v4
; RV32V-NEXT:    vmul.vv v16, v16, v20
; RV32V-NEXT:    vor.vv v18, v18, v26
; RV32V-NEXT:    vxor.vv v12, v16, v12
; RV32V-NEXT:    vmul.vv v8, v22, v8
; RV32V-NEXT:    vmul.vv v10, v24, v10
; RV32V-NEXT:    vxor.vv v8, v12, v8
; RV32V-NEXT:    vxor.vv v8, v8, v10
; RV32V-NEXT:    vand.vv v8, v8, v14
; RV32V-NEXT:    vor.vv v10, v18, v8
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v10, a0
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i32_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV64V-NEXT:    vmv.v.x v9, a0
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV64V-NEXT:    vzext.vf2 v22, v9
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    slli a1, a0, 32
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    vand.vx v10, v22, a0
; RV64V-NEXT:    vzext.vf2 v20, v8
; RV64V-NEXT:    lui a1, 139810
; RV64V-NEXT:    addi a1, a1, 546
; RV64V-NEXT:    slli a2, a1, 32
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    vand.vx v12, v20, a1
; RV64V-NEXT:    vand.vx v8, v22, a1
; RV64V-NEXT:    vand.vx v14, v20, a0
; RV64V-NEXT:    vmul.vv v16, v12, v10
; RV64V-NEXT:    vmul.vv v18, v14, v8
; RV64V-NEXT:    lui a2, %hi(.LCPI29_0)
; RV64V-NEXT:    vxor.vv v24, v18, v16
; RV64V-NEXT:    ld a2, %lo(.LCPI29_0)(a2)
; RV64V-NEXT:    vand.vx v16, v22, a2
; RV64V-NEXT:    lui a3, 279620
; RV64V-NEXT:    addi a3, a3, 1092
; RV64V-NEXT:    slli a4, a3, 32
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    vand.vx v18, v20, a3
; RV64V-NEXT:    vand.vx v20, v20, a2
; RV64V-NEXT:    vmul.vv v26, v18, v16
; RV64V-NEXT:    vand.vx v22, v22, a3
; RV64V-NEXT:    vmul.vv v28, v20, v22
; RV64V-NEXT:    vxor.vv v24, v24, v26
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vmul.vv v26, v12, v16
; RV64V-NEXT:    vmul.vv v28, v14, v10
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vxor.vv v26, v28, v26
; RV64V-NEXT:    vmul.vv v28, v18, v22
; RV64V-NEXT:    vmul.vv v30, v20, v8
; RV64V-NEXT:    vxor.vv v26, v26, v28
; RV64V-NEXT:    vxor.vv v26, v26, v30
; RV64V-NEXT:    vand.vx v26, v26, a0
; RV64V-NEXT:    vmul.vv v28, v12, v8
; RV64V-NEXT:    vmul.vv v30, v14, v22
; RV64V-NEXT:    vor.vv v24, v26, v24
; RV64V-NEXT:    vxor.vv v26, v30, v28
; RV64V-NEXT:    vmul.vv v28, v18, v10
; RV64V-NEXT:    vmul.vv v30, v20, v16
; RV64V-NEXT:    vxor.vv v26, v26, v28
; RV64V-NEXT:    vxor.vv v26, v26, v30
; RV64V-NEXT:    vand.vx v26, v26, a3
; RV64V-NEXT:    vmul.vv v12, v12, v22
; RV64V-NEXT:    vmul.vv v14, v14, v16
; RV64V-NEXT:    vor.vv v16, v24, v26
; RV64V-NEXT:    vxor.vv v12, v14, v12
; RV64V-NEXT:    vmul.vv v8, v18, v8
; RV64V-NEXT:    vmul.vv v10, v20, v10
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    vxor.vv v8, v8, v10
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v10, v16, v8
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v10, a0
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i32_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v12, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v10, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v12
; RV32ZVBC64-NEXT:    vclmul.vv v10, v10, v8
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v10, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i32_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v12, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v10, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v12
; RV64ZVBC64-NEXT:    vclmul.vv v10, v10, v8
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v10, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i32_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i32_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i64 0
  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
  %va.ext = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
  %vb.ext = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
  %clmul = call <vscale x 2 x i64> @llvm.clmul.nxv2i64(<vscale x 2 x i64> %va.ext, <vscale x 2 x i64> %vb.ext)
  %res.ext = lshr <vscale x 2 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 2 x i64> %res.ext to <vscale x 2 x i32>
  ret <vscale x 2 x i32> %res
}

define <vscale x 4 x i32> @clmulh_nxv4i32_vv(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv4i32_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32V-NEXT:    vzext.vf2 v12, v10
; RV32V-NEXT:    vand.vv v20, v12, v16
; RV32V-NEXT:    vmv4r.v v28, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vzext.vf2 v0, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v8, v0, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v12, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v28, v0, v28
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v8, v20
; RV32V-NEXT:    vmul.vv v20, v28, v24
; RV32V-NEXT:    vxor.vv v8, v20, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v4, v12, v20
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v8, v12, v24
; RV32V-NEXT:    vand.vv v12, v0, v24
; RV32V-NEXT:    vand.vv v0, v0, v20
; RV32V-NEXT:    vmul.vv v20, v12, v4
; RV32V-NEXT:    vmul.vv v24, v0, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v20, v28, v20
; RV32V-NEXT:    vxor.vv v20, v20, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v20, v4
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v28, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v24, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v20, v20, v16
; RV32V-NEXT:    vmul.vv v24, v12, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    vxor.vv v20, v20, v24
; RV32V-NEXT:    vxor.vv v16, v20, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v20
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v24, v28, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v20, v24, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v12, v16
; RV32V-NEXT:    vmul.vv v16, v0, v4
; RV32V-NEXT:    vxor.vv v20, v20, v24
; RV32V-NEXT:    vxor.vv v16, v20, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v20, v8
; RV32V-NEXT:    vmul.vv v20, v28, v4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vxor.vv v8, v20, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v12, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v0, v20
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vxor.vv v8, v8, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v12, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vor.vv v12, v16, v8
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v12, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i32_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    slli a1, a0, 32
; RV64V-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
; RV64V-NEXT:    vzext.vf2 v0, v10
; RV64V-NEXT:    add a1, a0, a1
; RV64V-NEXT:    vand.vx v12, v0, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a2, a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vzext.vf2 v4, v8
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    addi a0, a0, 546
; RV64V-NEXT:    slli a3, a0, 32
; RV64V-NEXT:    add a3, a0, a3
; RV64V-NEXT:    vand.vx v16, v4, a3
; RV64V-NEXT:    vand.vx v8, v0, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v20, v4, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui a0, %hi(.LCPI30_0)
; RV64V-NEXT:    ld a0, %lo(.LCPI30_0)(a0)
; RV64V-NEXT:    vand.vx v24, v0, a0
; RV64V-NEXT:    vmul.vv v12, v16, v12
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    slli a4, a2, 32
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    vand.vx v28, v4, a2
; RV64V-NEXT:    vmul.vv v8, v28, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v4, v4, a0
; RV64V-NEXT:    vand.vx v0, v0, a2
; RV64V-NEXT:    vmul.vv v8, v4, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v16, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v12, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v28, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v4, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 2
; RV64V-NEXT:    mv a4, a3
; RV64V-NEXT:    slli a3, a3, 2
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs4r.v v12, (a3) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v20, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v12, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v16, v8, v12
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a3, a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v28, v8
; RV64V-NEXT:    vmul.vv v8, v4, v24
; RV64V-NEXT:    vxor.vv v12, v16, v12
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v12, v0
; RV64V-NEXT:    vmul.vv v16, v20, v24
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v20, v8
; RV64V-NEXT:    vxor.vv v12, v16, v12
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v28, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v20, v4, v20
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vand.vx v12, v12, a0
; RV64V-NEXT:    vor.vv v12, v8, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v12, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i32_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v12, v10
; RV32ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV32ZVBC64-NEXT:    vclmul.vv v12, v16, v12
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v12, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i32_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v12, v10
; RV64ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV64ZVBC64-NEXT:    vclmul.vv v12, v16, v12
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v12, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i32_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v10
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i32_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v10
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
  %vb.ext = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
  %clmul = call <vscale x 4 x i64> @llvm.clmul.nxv4i64(<vscale x 4 x i64> %va.ext, <vscale x 4 x i64> %vb.ext)
  %res.ext = lshr <vscale x 4 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 4 x i64> %res.ext to <vscale x 4 x i32>
  ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @clmulh_nxv4i32_vx(<vscale x 4 x i32> %va, i32 %b) nounwind {
; RV32V-LABEL: clmulh_nxv4i32_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    lui a1, 69905
; RV32V-NEXT:    addi a1, a1, 273
; RV32V-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v28, a1
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v10, a0
; RV32V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV32V-NEXT:    vzext.vf2 v12, v10
; RV32V-NEXT:    vand.vv v20, v12, v28
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vzext.vf2 v0, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a0
; RV32V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v8, v0, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v12, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v28, v0, v28
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v28, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v8, v20
; RV32V-NEXT:    vmul.vv v20, v28, v24
; RV32V-NEXT:    vxor.vv v8, v20, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v4, v12, v20
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v24, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v8, v12, v24
; RV32V-NEXT:    vand.vv v12, v0, v24
; RV32V-NEXT:    vand.vv v0, v0, v20
; RV32V-NEXT:    vmul.vv v20, v12, v4
; RV32V-NEXT:    vmul.vv v24, v0, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v20, v28, v20
; RV32V-NEXT:    vxor.vv v20, v20, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v20, v4
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v28, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v28, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v24, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v20, v20, v16
; RV32V-NEXT:    vmul.vv v24, v12, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    vxor.vv v20, v20, v24
; RV32V-NEXT:    vxor.vv v16, v20, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v20
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v24, v28, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v20, v24, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v12, v16
; RV32V-NEXT:    vmul.vv v16, v0, v4
; RV32V-NEXT:    vxor.vv v20, v20, v24
; RV32V-NEXT:    vxor.vv v16, v20, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v20, v8
; RV32V-NEXT:    vmul.vv v20, v28, v4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v24, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vxor.vv v8, v20, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v12, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v0, v20
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vxor.vv v8, v8, v20
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v12, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vor.vv v12, v16, v8
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v12, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i32_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV64V-NEXT:    vmv.v.x v10, a0
; RV64V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV64V-NEXT:    vzext.vf2 v0, v10
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    slli a1, a0, 32
; RV64V-NEXT:    add a1, a0, a1
; RV64V-NEXT:    vand.vx v12, v0, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a2, a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v12, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vzext.vf2 v4, v8
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    addi a0, a0, 546
; RV64V-NEXT:    slli a3, a0, 32
; RV64V-NEXT:    add a3, a0, a3
; RV64V-NEXT:    vand.vx v16, v4, a3
; RV64V-NEXT:    vand.vx v8, v0, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v8, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v20, v4, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui a0, %hi(.LCPI31_0)
; RV64V-NEXT:    ld a0, %lo(.LCPI31_0)(a0)
; RV64V-NEXT:    vand.vx v24, v0, a0
; RV64V-NEXT:    vmul.vv v12, v16, v12
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs4r.v v16, (a2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    slli a4, a2, 32
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    vand.vx v28, v4, a2
; RV64V-NEXT:    vmul.vv v8, v28, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v4, v4, a0
; RV64V-NEXT:    vand.vx v0, v0, a2
; RV64V-NEXT:    vmul.vv v8, v4, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v16, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v12, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v28, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v4, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v8
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl4r.v v8, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 2
; RV64V-NEXT:    mv a4, a3
; RV64V-NEXT:    slli a3, a3, 2
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs4r.v v12, (a3) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v20, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v12, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v16, v8, v12
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a3, a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v28, v8
; RV64V-NEXT:    vmul.vv v8, v4, v24
; RV64V-NEXT:    vxor.vv v12, v16, v12
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v12, v0
; RV64V-NEXT:    vmul.vv v16, v20, v24
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v20, v8
; RV64V-NEXT:    vxor.vv v12, v16, v12
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v28, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v20, v4, v20
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vand.vx v12, v12, a0
; RV64V-NEXT:    vor.vv v12, v8, v12
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v12, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 5
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i32_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v16, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v16
; RV32ZVBC64-NEXT:    vclmul.vv v12, v12, v8
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v12, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i32_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v12, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v16
; RV64ZVBC64-NEXT:    vclmul.vv v12, v12, v8
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v12, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i32_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i32_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i64 0
  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
  %va.ext = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
  %vb.ext = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
  %clmul = call <vscale x 4 x i64> @llvm.clmul.nxv4i64(<vscale x 4 x i64> %va.ext, <vscale x 4 x i64> %vb.ext)
  %res.ext = lshr <vscale x 4 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 4 x i64> %res.ext to <vscale x 4 x i32>
  ret <vscale x 4 x i32> %res
}

define <vscale x 8 x i32> @clmulh_nxv8i32_vv(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv8i32_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    lui a0, 69905
; RV32V-NEXT:    addi a0, a0, 273
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32V-NEXT:    vzext.vf2 v16, v12
; RV32V-NEXT:    vand.vv v0, v16, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vzext.vf2 v24, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v16, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v0, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v16, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v24, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vv v0, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vv v16, v0, v8
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v16, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v0, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v8
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v16, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i32_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV64V-NEXT:    vmv4r.v v16, v12
; RV64V-NEXT:    vmv4r.v v24, v8
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    slli a1, a0, 32
; RV64V-NEXT:    add a1, a0, a1
; RV64V-NEXT:    vzext.vf2 v0, v12
; RV64V-NEXT:    vand.vx v8, v0, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 6
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vzext.vf2 v16, v24
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    addi a0, a0, 546
; RV64V-NEXT:    slli a3, a0, 32
; RV64V-NEXT:    add a3, a0, a3
; RV64V-NEXT:    vand.vx v24, v16, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmv.v.v v8, v0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v24, v0, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v16, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a0, %hi(.LCPI32_0)
; RV64V-NEXT:    ld a0, %lo(.LCPI32_0)(a0)
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 5
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 6
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v0, v8
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    slli a4, a2, 32
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v0, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vmul.vv v0, v16, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v0, a1
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 6
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a3, a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 6
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v16, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i32_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v16, v12
; RV32ZVBC64-NEXT:    vzext.vf2 v24, v8
; RV32ZVBC64-NEXT:    vclmul.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v16, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i32_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v16, v12
; RV64ZVBC64-NEXT:    vzext.vf2 v24, v8
; RV64ZVBC64-NEXT:    vclmul.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v16, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i32_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v12
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i32_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v12
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
  %vb.ext = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
  %clmul = call <vscale x 8 x i64> @llvm.clmul.nxv8i64(<vscale x 8 x i64> %va.ext, <vscale x 8 x i64> %vb.ext)
  %res.ext = lshr <vscale x 8 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 8 x i64> %res.ext to <vscale x 8 x i32>
  ret <vscale x 8 x i32> %res
}

define <vscale x 8 x i32> @clmulh_nxv8i32_vx(<vscale x 8 x i32> %va, i32 %b) nounwind {
; RV32V-LABEL: clmulh_nxv8i32_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a2, a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    lui a1, 69905
; RV32V-NEXT:    addi a1, a1, 273
; RV32V-NEXT:    vsetvli a2, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a1
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 3
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 2
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    add a1, sp, a1
; RV32V-NEXT:    addi a1, a1, 16
; RV32V-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v12, a0
; RV32V-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV32V-NEXT:    vzext.vf2 v16, v12
; RV32V-NEXT:    vand.vv v0, v16, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vzext.vf2 v24, v8
; RV32V-NEXT:    lui a0, 139810
; RV32V-NEXT:    addi a0, a0, 546
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v16, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v0, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a0, 559241
; RV32V-NEXT:    addi a0, a0, -1912
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a0, 279620
; RV32V-NEXT:    addi a0, a0, 1092
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v16, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v24, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vv v0, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vv v16, v0, v8
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v16, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v0, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v8
; RV32V-NEXT:    li a0, 32
; RV32V-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32V-NEXT:    vnsrl.wx v8, v16, a0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i32_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV64V-NEXT:    vmv4r.v v24, v8
; RV64V-NEXT:    vmv.v.x v16, a0
; RV64V-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV64V-NEXT:    vzext.vf2 v0, v16
; RV64V-NEXT:    lui a0, 69905
; RV64V-NEXT:    addi a0, a0, 273
; RV64V-NEXT:    slli a1, a0, 32
; RV64V-NEXT:    add a1, a0, a1
; RV64V-NEXT:    vand.vx v8, v0, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 6
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vzext.vf2 v16, v24
; RV64V-NEXT:    lui a0, 139810
; RV64V-NEXT:    addi a0, a0, 546
; RV64V-NEXT:    slli a3, a0, 32
; RV64V-NEXT:    add a3, a0, a3
; RV64V-NEXT:    vand.vx v24, v16, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmv.v.v v8, v0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v24, v0, a3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v16, a1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a2, a0
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    add a0, a0, a2
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a0, %hi(.LCPI33_0)
; RV64V-NEXT:    ld a0, %lo(.LCPI33_0)(a0)
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 5
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 2
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 6
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v0, v8
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 3
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr a2, vlenb
; RV64V-NEXT:    slli a2, a2, 4
; RV64V-NEXT:    mv a4, a2
; RV64V-NEXT:    slli a2, a2, 1
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    add a2, sp, a2
; RV64V-NEXT:    addi a2, a2, 16
; RV64V-NEXT:    vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a2, 279620
; RV64V-NEXT:    addi a2, a2, 1092
; RV64V-NEXT:    slli a4, a2, 32
; RV64V-NEXT:    add a2, a2, a4
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v0, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vmul.vv v0, v16, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi a4, sp, 16
; RV64V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a5, a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v8
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v24
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v0, a1
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 6
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a3, a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a3, a1
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, a1, a3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v16, a2
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 6
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 16
; RV64V-NEXT:    vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 16
; RV64V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    li a0, 32
; RV64V-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64V-NEXT:    vnsrl.wx v8, v16, a0
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i32_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32ZVBC64-NEXT:    vmv.v.x v24, a0
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV32ZVBC64-NEXT:    vzext.vf2 v8, v24
; RV32ZVBC64-NEXT:    vclmul.vv v16, v16, v8
; RV32ZVBC64-NEXT:    li a0, 32
; RV32ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV32ZVBC64-NEXT:    vnsrl.wx v8, v16, a0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i32_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v24, a0
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vzext.vf2 v16, v8
; RV64ZVBC64-NEXT:    vzext.vf2 v8, v24
; RV64ZVBC64-NEXT:    vclmul.vv v16, v16, v8
; RV64ZVBC64-NEXT:    li a0, 32
; RV64ZVBC64-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; RV64ZVBC64-NEXT:    vnsrl.wx v8, v16, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i32_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i32_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i64 0
  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
  %va.ext = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
  %vb.ext = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
  %clmul = call <vscale x 8 x i64> @llvm.clmul.nxv8i64(<vscale x 8 x i64> %va.ext, <vscale x 8 x i64> %vb.ext)
  %res.ext = lshr <vscale x 8 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 8 x i64> %res.ext to <vscale x 8 x i32>
  ret <vscale x 8 x i32> %res
}

define <vscale x 16 x i32> @clmulh_nxv16i32_vv(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv16i32_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    lui a0, 16
; RV32V-NEXT:    addi a0, a0, -256
; RV32V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32V-NEXT:    vsrl.vi v24, v16, 8
; RV32V-NEXT:    vand.vx v24, v24, a0
; RV32V-NEXT:    vsrl.vi v0, v16, 24
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    vand.vx v0, v16, a0
; RV32V-NEXT:    vsll.vi v0, v0, 8
; RV32V-NEXT:    vsll.vi v16, v16, 24
; RV32V-NEXT:    vor.vv v16, v16, v0
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsrl.vi v24, v16, 4
; RV32V-NEXT:    lui a1, 61681
; RV32V-NEXT:    addi a1, a1, -241
; RV32V-NEXT:    vand.vx v24, v24, a1
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vsll.vi v16, v16, 4
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 2
; RV32V-NEXT:    lui a2, 209715
; RV32V-NEXT:    addi a2, a2, 819
; RV32V-NEXT:    vand.vx v24, v24, a2
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 1
; RV32V-NEXT:    lui a3, 349525
; RV32V-NEXT:    addi a3, a3, 1365
; RV32V-NEXT:    vand.vx v24, v24, a3
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vadd.vv v16, v16, v16
; RV32V-NEXT:    vor.vv v0, v24, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vand.vx v24, v8, a0
; RV32V-NEXT:    vsll.vi v24, v24, 8
; RV32V-NEXT:    vsll.vi v8, v8, 24
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    lui a5, 69905
; RV32V-NEXT:    addi a5, a5, 273
; RV32V-NEXT:    vand.vx v24, v0, a5
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v16, v16, v8
; RV32V-NEXT:    lui a7, 139810
; RV32V-NEXT:    addi a7, a7, 546
; RV32V-NEXT:    vand.vx v8, v16, a7
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a6, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmv.v.v v8, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a6, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v24, v0, a7
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v16, a5
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a6, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vand.vx v8, v8, a4
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv t0, a6
; RV32V-NEXT:    slli a6, a6, 2
; RV32V-NEXT:    add a6, a6, t0
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 4
; RV32V-NEXT:    mv t0, a6
; RV32V-NEXT:    slli a6, a6, 2
; RV32V-NEXT:    add a6, a6, t0
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 6
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v0, v8, v0
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv t0, a6
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    add a6, a6, t0
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v24
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv t0, a6
; RV32V-NEXT:    slli a6, a6, 1
; RV32V-NEXT:    add a6, a6, t0
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a6, 279620
; RV32V-NEXT:    addi a6, a6, 1092
; RV32V-NEXT:    vand.vx v8, v16, a6
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t1, t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 2
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v24
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v8, v0
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v8, v0
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v8, v8, a6
; RV32V-NEXT:    vand.vx v16, v16, a4
; RV32V-NEXT:    vmul.vv v0, v16, v8
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v0, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 2
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 6
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    addi t0, sp, 16
; RV32V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v0
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    addi t0, sp, 16
; RV32V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t1, t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v8
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 5
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v24
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    mv t1, t0
; RV32V-NEXT:    slli t0, t0, 1
; RV32V-NEXT:    add t0, t0, t1
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v16, v16, a7
; RV32V-NEXT:    csrr a7, vlenb
; RV32V-NEXT:    slli a7, a7, 4
; RV32V-NEXT:    add a7, sp, a7
; RV32V-NEXT:    addi a7, a7, 16
; RV32V-NEXT:    vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v16, v0, a5
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 2
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v24
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v8
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v0
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v16
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a7, a7, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 2
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v0, v0, v16
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 2
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v8
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v0, v16, a6
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v0
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    mv a6, a5
; RV32V-NEXT:    slli a5, a5, 2
; RV32V-NEXT:    add a5, a5, a6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a6, a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 5
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v16
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 4
; RV32V-NEXT:    mv a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v0
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vand.vx v8, v8, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v16, v16, a0
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsll.vi v24, v8, 24
; RV32V-NEXT:    vand.vx v8, v8, a0
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv16i32_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    lui a0, 16
; RV64V-NEXT:    addi a0, a0, -256
; RV64V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV64V-NEXT:    vsrl.vi v24, v16, 8
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vsrl.vi v0, v16, 24
; RV64V-NEXT:    vor.vv v24, v24, v0
; RV64V-NEXT:    vand.vx v0, v16, a0
; RV64V-NEXT:    vsll.vi v0, v0, 8
; RV64V-NEXT:    vsll.vi v16, v16, 24
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsrl.vi v24, v16, 4
; RV64V-NEXT:    lui a1, 61681
; RV64V-NEXT:    addi a1, a1, -241
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vsll.vi v16, v16, 4
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 2
; RV64V-NEXT:    lui a2, 209715
; RV64V-NEXT:    addi a2, a2, 819
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vsll.vi v16, v16, 2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 1
; RV64V-NEXT:    lui a3, 349525
; RV64V-NEXT:    addi a3, a3, 1365
; RV64V-NEXT:    vand.vx v24, v24, a3
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vadd.vv v16, v16, v16
; RV64V-NEXT:    vor.vv v0, v24, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 8
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vand.vx v24, v8, a0
; RV64V-NEXT:    vsll.vi v24, v24, 8
; RV64V-NEXT:    vsll.vi v8, v8, 24
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    lui a5, 69905
; RV64V-NEXT:    addi a5, a5, 273
; RV64V-NEXT:    vand.vx v24, v0, a5
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    lui a7, 139810
; RV64V-NEXT:    addi a7, a7, 546
; RV64V-NEXT:    vand.vx v8, v16, a7
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a6, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmv.v.v v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a6, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v24, v0, a7
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v16, a5
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a6, a4
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, a4, a6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a4, 559241
; RV64V-NEXT:    addi a4, a4, -1912
; RV64V-NEXT:    vand.vx v8, v8, a4
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 2
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 4
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 2
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 6
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v24
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 1
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a6, 279620
; RV64V-NEXT:    addi a6, a6, 1092
; RV64V-NEXT:    vand.vx v8, v16, a6
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t1, t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v8, v0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v8, v0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vand.vx v16, v16, a4
; RV64V-NEXT:    vmul.vv v0, v16, v8
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v0, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 6
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    addi t0, sp, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi t0, sp, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t1, t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v8
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 5
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    csrr a7, vlenb
; RV64V-NEXT:    slli a7, a7, 4
; RV64V-NEXT:    add a7, sp, a7
; RV64V-NEXT:    addi a7, a7, 16
; RV64V-NEXT:    vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v0, a5
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v24
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a7, a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v16, a6
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a6, a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 5
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vand.vx v8, v8, a4
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 8
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsll.vi v24, v8, 24
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 8
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv16i32_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a1, a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    sub sp, sp, a0
; RV32ZVBC64-NEXT:    lui a0, 16
; RV32ZVBC64-NEXT:    addi a0, a0, -256
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 8
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vsrl.vi v0, v16, 24
; RV32ZVBC64-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a0
; RV32ZVBC64-NEXT:    vsll.vi v0, v0, 8
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 24
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 4
; RV32ZVBC64-NEXT:    lui a1, 61681
; RV32ZVBC64-NEXT:    addi a1, a1, -241
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV32ZVBC64-NEXT:    lui a2, 209715
; RV32ZVBC64-NEXT:    addi a2, a2, 819
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV32ZVBC64-NEXT:    lui a3, 349525
; RV32ZVBC64-NEXT:    addi a3, a3, 1365
; RV32ZVBC64-NEXT:    vand.vx v24, v24, a3
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV32ZVBC64-NEXT:    vor.vv v0, v24, v16
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vand.vx v24, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v24, v24, 8
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 24
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    lui a5, 69905
; RV32ZVBC64-NEXT:    addi a5, a5, 273
; RV32ZVBC64-NEXT:    vand.vx v24, v0, a5
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 6
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    lui a7, 139810
; RV32ZVBC64-NEXT:    addi a7, a7, 546
; RV32ZVBC64-NEXT:    vand.vx v8, v16, a7
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a6, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a6
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vmv.v.v v8, v0
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a6, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 1
; RV32ZVBC64-NEXT:    add a4, a4, a6
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v24, v0, a7
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a5
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    mv a6, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 3
; RV32ZVBC64-NEXT:    add a4, a4, a6
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a4, 559241
; RV32ZVBC64-NEXT:    addi a4, a4, -1912
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv t0, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 2
; RV32ZVBC64-NEXT:    add a6, a6, t0
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 4
; RV32ZVBC64-NEXT:    mv t0, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 2
; RV32ZVBC64-NEXT:    add a6, a6, t0
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 6
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv t0, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    add a6, a6, t0
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv t0, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 1
; RV32ZVBC64-NEXT:    add a6, a6, t0
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a6, 279620
; RV32ZVBC64-NEXT:    addi a6, a6, 1092
; RV32ZVBC64-NEXT:    vand.vx v8, v16, a6
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t1, t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 2
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a6
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a4
; RV32ZVBC64-NEXT:    vmul.vv v0, v16, v8
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 2
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 6
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC64-NEXT:    addi t0, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    addi t0, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t1, t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v24, v8
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 5
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v16, v24
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    mv t1, t0
; RV32ZVBC64-NEXT:    slli t0, t0, 1
; RV32ZVBC64-NEXT:    add t0, t0, t1
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a7
; RV32ZVBC64-NEXT:    csrr a7, vlenb
; RV32ZVBC64-NEXT:    slli a7, a7, 4
; RV32ZVBC64-NEXT:    add a7, sp, a7
; RV32ZVBC64-NEXT:    addi a7, a7, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v16, v0, a5
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 2
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v24
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v24, v24, v16
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a7, a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 6
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 2
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v0, v0, v16
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 2
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v0, v16, a6
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a6, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a6
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    mv a6, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 2
; RV32ZVBC64-NEXT:    add a5, a5, a6
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a6, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a6, a6, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a6
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 5
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 6
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 4
; RV32ZVBC64-NEXT:    mv a6, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, a6
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vv v16, v16, v0
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV32ZVBC64-NEXT:    csrr a4, vlenb
; RV32ZVBC64-NEXT:    slli a4, a4, 4
; RV32ZVBC64-NEXT:    mv a5, a4
; RV32ZVBC64-NEXT:    slli a4, a4, 2
; RV32ZVBC64-NEXT:    add a4, a4, a5
; RV32ZVBC64-NEXT:    add a4, sp, a4
; RV32ZVBC64-NEXT:    addi a4, a4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vsll.vi v24, v8, 24
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a1, a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv16i32_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a1, a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    sub sp, sp, a0
; RV64ZVBC64-NEXT:    lui a0, 16
; RV64ZVBC64-NEXT:    addi a0, a0, -256
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 8
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vsrl.vi v0, v16, 24
; RV64ZVBC64-NEXT:    vor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a0
; RV64ZVBC64-NEXT:    vsll.vi v0, v0, 8
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 24
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 4
; RV64ZVBC64-NEXT:    lui a1, 61681
; RV64ZVBC64-NEXT:    addi a1, a1, -241
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV64ZVBC64-NEXT:    lui a2, 209715
; RV64ZVBC64-NEXT:    addi a2, a2, 819
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV64ZVBC64-NEXT:    lui a3, 349525
; RV64ZVBC64-NEXT:    addi a3, a3, 1365
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a3
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV64ZVBC64-NEXT:    vor.vv v0, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vand.vx v24, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v24, v24, 8
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 24
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    lui a5, 69905
; RV64ZVBC64-NEXT:    addi a5, a5, 273
; RV64ZVBC64-NEXT:    vand.vx v24, v0, a5
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV64ZVBC64-NEXT:    lui a7, 139810
; RV64ZVBC64-NEXT:    addi a7, a7, 546
; RV64ZVBC64-NEXT:    vand.vx v8, v16, a7
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a6, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vmv.v.v v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a6, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v24, v0, a7
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a5
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a6, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, a4, a6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a4, 559241
; RV64ZVBC64-NEXT:    addi a4, a4, -1912
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 2
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 4
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 2
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 6
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 1
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a6, 279620
; RV64ZVBC64-NEXT:    addi a6, a6, 1092
; RV64ZVBC64-NEXT:    vand.vx v8, v16, a6
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t1, t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 2
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v0, v16, v8
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 2
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 6
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    addi t0, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    addi t0, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t1, t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v24, v8
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 5
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC64-NEXT:    csrr a7, vlenb
; RV64ZVBC64-NEXT:    slli a7, a7, 4
; RV64ZVBC64-NEXT:    add a7, sp, a7
; RV64ZVBC64-NEXT:    addi a7, a7, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v16, v0, a5
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v24
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a7, a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a6
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a6, a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 5
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsll.vi v24, v8, 24
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a1, a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv16i32_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vv v8, v8, v16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv16i32_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vv v8, v8, v16
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 16 x i32> %va to <vscale x 16 x i64>
  %vb.ext = zext <vscale x 16 x i32> %vb to <vscale x 16 x i64>
  %clmul = call <vscale x 16 x i64> @llvm.clmul.nxv16i64(<vscale x 16 x i64> %va.ext, <vscale x 16 x i64> %vb.ext)
  %res.ext = lshr <vscale x 16 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 16 x i64> %res.ext to <vscale x 16 x i32>
  ret <vscale x 16 x i32> %res
}

define <vscale x 16 x i32> @clmulh_nxv16i32_vx(<vscale x 16 x i32> %va, i32 %b) nounwind {
; RV32V-LABEL: clmulh_nxv16i32_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a1, vlenb
; RV32V-NEXT:    slli a1, a1, 4
; RV32V-NEXT:    mv a2, a1
; RV32V-NEXT:    slli a1, a1, 1
; RV32V-NEXT:    add a1, a1, a2
; RV32V-NEXT:    sub sp, sp, a1
; RV32V-NEXT:    lui a1, 16
; RV32V-NEXT:    addi a1, a1, -256
; RV32V-NEXT:    vsetvli a2, zero, e32, m8, ta, ma
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vand.vx v24, v8, a1
; RV32V-NEXT:    vsll.vi v24, v24, 8
; RV32V-NEXT:    vsll.vi v8, v8, 24
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    lui a2, 61681
; RV32V-NEXT:    addi a2, a2, -241
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    lui a3, 209715
; RV32V-NEXT:    addi a3, a3, 819
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vand.vx v16, v16, a4
; RV32V-NEXT:    vand.vx v8, v8, a4
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v24, v16, v8
; RV32V-NEXT:    lui a6, 139810
; RV32V-NEXT:    addi a6, a6, 546
; RV32V-NEXT:    vand.vx v8, v24, a6
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a7, a5
; RV32V-NEXT:    slli a5, a5, 2
; RV32V-NEXT:    add a5, a5, a7
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a7, 69905
; RV32V-NEXT:    addi a7, a7, 273
; RV32V-NEXT:    srli a5, a0, 8
; RV32V-NEXT:    vand.vx v16, v24, a7
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 3
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 5
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    and a5, a5, a1
; RV32V-NEXT:    srli t0, a0, 24
; RV32V-NEXT:    and t1, a0, a1
; RV32V-NEXT:    slli t1, t1, 8
; RV32V-NEXT:    slli a0, a0, 24
; RV32V-NEXT:    or a5, a5, t0
; RV32V-NEXT:    or a0, a0, t1
; RV32V-NEXT:    or a0, a0, a5
; RV32V-NEXT:    srli a5, a0, 4
; RV32V-NEXT:    and a0, a0, a2
; RV32V-NEXT:    and a5, a5, a2
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    or a0, a5, a0
; RV32V-NEXT:    srli a5, a0, 2
; RV32V-NEXT:    and a0, a0, a3
; RV32V-NEXT:    and a5, a5, a3
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    or a0, a5, a0
; RV32V-NEXT:    srli a5, a0, 1
; RV32V-NEXT:    and a0, a0, a4
; RV32V-NEXT:    and a5, a5, a4
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    or t3, a5, a0
; RV32V-NEXT:    and a0, t3, a7
; RV32V-NEXT:    vmul.vx v8, v8, a0
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv t0, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, t0
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    and a5, t3, a6
; RV32V-NEXT:    vmul.vx v8, v16, a5
; RV32V-NEXT:    csrr t0, vlenb
; RV32V-NEXT:    slli t0, t0, 4
; RV32V-NEXT:    add t0, sp, t0
; RV32V-NEXT:    addi t0, t0, 16
; RV32V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui t2, 279620
; RV32V-NEXT:    addi t2, t2, 1092
; RV32V-NEXT:    vand.vx v0, v24, t2
; RV32V-NEXT:    lui t0, 559241
; RV32V-NEXT:    addi t0, t0, -1912
; RV32V-NEXT:    and t1, t3, t0
; RV32V-NEXT:    vmul.vx v8, v0, t1
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    mv t5, t4
; RV32V-NEXT:    slli t4, t4, 1
; RV32V-NEXT:    add t4, t4, t5
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 4
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v24, v16
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    mv t5, t4
; RV32V-NEXT:    slli t4, t4, 1
; RV32V-NEXT:    add t4, t4, t5
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v24, v8, t0
; RV32V-NEXT:    and t3, t3, t2
; RV32V-NEXT:    vmul.vx v8, v24, t3
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 4
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    mv t5, t4
; RV32V-NEXT:    slli t4, t4, 2
; RV32V-NEXT:    add t4, t4, t5
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vx v8, v8, t1
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 5
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vx v8, v8, a0
; RV32V-NEXT:    addi t4, sp, 16
; RV32V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    mv t5, t4
; RV32V-NEXT:    slli t4, t4, 1
; RV32V-NEXT:    add t4, t4, t5
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 4
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v16, v8
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    mv t5, t4
; RV32V-NEXT:    slli t4, t4, 1
; RV32V-NEXT:    add t4, t4, t5
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vs8r.v v16, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    addi t4, sp, 16
; RV32V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 4
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vx v8, v0, t3
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vx v8, v24, a5
; RV32V-NEXT:    addi t4, sp, 16
; RV32V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 4
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v16, v8
; RV32V-NEXT:    addi t4, sp, 16
; RV32V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr t4, vlenb
; RV32V-NEXT:    slli t4, t4, 3
; RV32V-NEXT:    mv t5, t4
; RV32V-NEXT:    slli t4, t4, 1
; RV32V-NEXT:    add t4, t4, t5
; RV32V-NEXT:    add t4, sp, t4
; RV32V-NEXT:    addi t4, t4, 16
; RV32V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vx v16, v16, a6
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 4
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v8, v8, a7
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv a7, a6
; RV32V-NEXT:    slli a6, a6, 1
; RV32V-NEXT:    add a6, a6, a7
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv a7, a6
; RV32V-NEXT:    slli a6, a6, 2
; RV32V-NEXT:    add a6, a6, a7
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vx v8, v8, a5
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 5
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vx v8, v8, t3
; RV32V-NEXT:    addi a6, sp, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv a7, a6
; RV32V-NEXT:    slli a6, a6, 1
; RV32V-NEXT:    add a6, a6, a7
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 4
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v8
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv a7, a6
; RV32V-NEXT:    slli a6, a6, 1
; RV32V-NEXT:    add a6, a6, a7
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    addi a6, sp, 16
; RV32V-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 4
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vx v8, v0, a0
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vx v8, v24, t1
; RV32V-NEXT:    addi a6, sp, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 4
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v16, v16, v8
; RV32V-NEXT:    addi a6, sp, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    vand.vx v8, v8, t2
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 4
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv a7, a6
; RV32V-NEXT:    slli a6, a6, 2
; RV32V-NEXT:    add a6, a6, a7
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vx v8, v8, t3
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 5
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vx v8, v8, t1
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 5
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv a7, a6
; RV32V-NEXT:    slli a6, a6, 1
; RV32V-NEXT:    add a6, a6, a7
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 4
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v8
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    mv a7, a6
; RV32V-NEXT:    slli a6, a6, 2
; RV32V-NEXT:    add a6, a6, a7
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 3
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a6, vlenb
; RV32V-NEXT:    slli a6, a6, 5
; RV32V-NEXT:    add a6, sp, a6
; RV32V-NEXT:    addi a6, a6, 16
; RV32V-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    vmul.vx v16, v0, a5
; RV32V-NEXT:    vmul.vx v24, v24, a0
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    vand.vx v8, v8, t0
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a5, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, a0, a5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v16, v16, a1
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsll.vi v24, v8, 24
; RV32V-NEXT:    vand.vx v8, v8, a1
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vand.vx v8, v8, a3
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    vand.vx v16, v16, a4
; RV32V-NEXT:    vand.vx v8, v8, a4
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv16i32_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a2, a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV64V-NEXT:    vmv.v.x v16, a0
; RV64V-NEXT:    vsrl.vi v24, v16, 8
; RV64V-NEXT:    lui a0, 16
; RV64V-NEXT:    addi a0, a0, -256
; RV64V-NEXT:    vand.vx v24, v24, a0
; RV64V-NEXT:    vsrl.vi v0, v16, 24
; RV64V-NEXT:    vor.vv v24, v24, v0
; RV64V-NEXT:    vand.vx v0, v16, a0
; RV64V-NEXT:    vsll.vi v0, v0, 8
; RV64V-NEXT:    vsll.vi v16, v16, 24
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsrl.vi v24, v16, 4
; RV64V-NEXT:    lui a1, 61681
; RV64V-NEXT:    addi a1, a1, -241
; RV64V-NEXT:    vand.vx v24, v24, a1
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vsll.vi v16, v16, 4
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 2
; RV64V-NEXT:    lui a2, 209715
; RV64V-NEXT:    addi a2, a2, 819
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vsll.vi v16, v16, 2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 1
; RV64V-NEXT:    lui a3, 349525
; RV64V-NEXT:    addi a3, a3, 1365
; RV64V-NEXT:    vand.vx v24, v24, a3
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vadd.vv v16, v16, v16
; RV64V-NEXT:    vor.vv v0, v24, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 8
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vand.vx v24, v8, a0
; RV64V-NEXT:    vsll.vi v24, v24, 8
; RV64V-NEXT:    vsll.vi v8, v8, 24
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    lui a5, 69905
; RV64V-NEXT:    addi a5, a5, 273
; RV64V-NEXT:    vand.vx v24, v0, a5
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    lui a7, 139810
; RV64V-NEXT:    addi a7, a7, 546
; RV64V-NEXT:    vand.vx v8, v16, a7
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a6, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmv.v.v v8, v0
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a6, a4
; RV64V-NEXT:    slli a4, a4, 1
; RV64V-NEXT:    add a4, a4, a6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v24, v0, a7
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v16, a5
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    mv a6, a4
; RV64V-NEXT:    slli a4, a4, 3
; RV64V-NEXT:    add a4, a4, a6
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a4, 559241
; RV64V-NEXT:    addi a4, a4, -1912
; RV64V-NEXT:    vand.vx v8, v8, a4
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 2
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 4
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 2
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 6
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v8, v0
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v24
; RV64V-NEXT:    csrr a6, vlenb
; RV64V-NEXT:    slli a6, a6, 3
; RV64V-NEXT:    mv t0, a6
; RV64V-NEXT:    slli a6, a6, 1
; RV64V-NEXT:    add a6, a6, t0
; RV64V-NEXT:    add a6, sp, a6
; RV64V-NEXT:    addi a6, a6, 16
; RV64V-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui a6, 279620
; RV64V-NEXT:    addi a6, a6, 1092
; RV64V-NEXT:    vand.vx v8, v16, a6
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t1, t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v8, v0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v8, v0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vand.vx v16, v16, a4
; RV64V-NEXT:    vmul.vv v0, v16, v8
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v0, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 6
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    addi t0, sp, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi t0, sp, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t1, t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v8
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 5
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v24
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    csrr a7, vlenb
; RV64V-NEXT:    slli a7, a7, 4
; RV64V-NEXT:    add a7, sp, a7
; RV64V-NEXT:    addi a7, a7, 16
; RV64V-NEXT:    vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v0, a5
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v24
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a7, a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a7, a5
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    add a5, a5, a7
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v16, a6
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 3
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a6, a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 5
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 1
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vand.vx v8, v8, a4
; RV64V-NEXT:    csrr a4, vlenb
; RV64V-NEXT:    slli a4, a4, 4
; RV64V-NEXT:    mv a5, a4
; RV64V-NEXT:    slli a4, a4, 2
; RV64V-NEXT:    add a4, a4, a5
; RV64V-NEXT:    add a4, sp, a4
; RV64V-NEXT:    addi a4, a4, 16
; RV64V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 8
; RV64V-NEXT:    vand.vx v16, v16, a0
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsll.vi v24, v8, 24
; RV64V-NEXT:    vand.vx v8, v8, a0
; RV64V-NEXT:    vsll.vi v8, v8, 8
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a1
; RV64V-NEXT:    vand.vx v8, v8, a1
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv16i32_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    csrr a1, vlenb
; RV32ZVBC64-NEXT:    slli a1, a1, 4
; RV32ZVBC64-NEXT:    mv a2, a1
; RV32ZVBC64-NEXT:    slli a1, a1, 1
; RV32ZVBC64-NEXT:    add a1, a1, a2
; RV32ZVBC64-NEXT:    sub sp, sp, a1
; RV32ZVBC64-NEXT:    lui a1, 16
; RV32ZVBC64-NEXT:    addi a1, a1, -256
; RV32ZVBC64-NEXT:    vsetvli a2, zero, e32, m8, ta, ma
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vand.vx v24, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v24, v24, 8
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 24
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC64-NEXT:    lui a2, 61681
; RV32ZVBC64-NEXT:    addi a2, a2, -241
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    lui a3, 209715
; RV32ZVBC64-NEXT:    addi a3, a3, 819
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    lui a4, 349525
; RV32ZVBC64-NEXT:    addi a4, a4, 1365
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a4
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v24, v16, v8
; RV32ZVBC64-NEXT:    lui a6, 139810
; RV32ZVBC64-NEXT:    addi a6, a6, 546
; RV32ZVBC64-NEXT:    vand.vx v8, v24, a6
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv a7, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 2
; RV32ZVBC64-NEXT:    add a5, a5, a7
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui a7, 69905
; RV32ZVBC64-NEXT:    addi a7, a7, 273
; RV32ZVBC64-NEXT:    srli a5, a0, 8
; RV32ZVBC64-NEXT:    vand.vx v16, v24, a7
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 3
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 5
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    and a5, a5, a1
; RV32ZVBC64-NEXT:    srli t0, a0, 24
; RV32ZVBC64-NEXT:    and t1, a0, a1
; RV32ZVBC64-NEXT:    slli t1, t1, 8
; RV32ZVBC64-NEXT:    slli a0, a0, 24
; RV32ZVBC64-NEXT:    or a5, a5, t0
; RV32ZVBC64-NEXT:    or a0, a0, t1
; RV32ZVBC64-NEXT:    or a0, a0, a5
; RV32ZVBC64-NEXT:    srli a5, a0, 4
; RV32ZVBC64-NEXT:    and a0, a0, a2
; RV32ZVBC64-NEXT:    and a5, a5, a2
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    or a0, a5, a0
; RV32ZVBC64-NEXT:    srli a5, a0, 2
; RV32ZVBC64-NEXT:    and a0, a0, a3
; RV32ZVBC64-NEXT:    and a5, a5, a3
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    or a0, a5, a0
; RV32ZVBC64-NEXT:    srli a5, a0, 1
; RV32ZVBC64-NEXT:    and a0, a0, a4
; RV32ZVBC64-NEXT:    and a5, a5, a4
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    or t3, a5, a0
; RV32ZVBC64-NEXT:    and a0, t3, a7
; RV32ZVBC64-NEXT:    vmul.vx v8, v8, a0
; RV32ZVBC64-NEXT:    csrr a5, vlenb
; RV32ZVBC64-NEXT:    slli a5, a5, 3
; RV32ZVBC64-NEXT:    mv t0, a5
; RV32ZVBC64-NEXT:    slli a5, a5, 1
; RV32ZVBC64-NEXT:    add a5, a5, t0
; RV32ZVBC64-NEXT:    add a5, sp, a5
; RV32ZVBC64-NEXT:    addi a5, a5, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    and a5, t3, a6
; RV32ZVBC64-NEXT:    vmul.vx v8, v16, a5
; RV32ZVBC64-NEXT:    csrr t0, vlenb
; RV32ZVBC64-NEXT:    slli t0, t0, 4
; RV32ZVBC64-NEXT:    add t0, sp, t0
; RV32ZVBC64-NEXT:    addi t0, t0, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    lui t2, 279620
; RV32ZVBC64-NEXT:    addi t2, t2, 1092
; RV32ZVBC64-NEXT:    vand.vx v0, v24, t2
; RV32ZVBC64-NEXT:    lui t0, 559241
; RV32ZVBC64-NEXT:    addi t0, t0, -1912
; RV32ZVBC64-NEXT:    and t1, t3, t0
; RV32ZVBC64-NEXT:    vmul.vx v8, v0, t1
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    mv t5, t4
; RV32ZVBC64-NEXT:    slli t4, t4, 1
; RV32ZVBC64-NEXT:    add t4, t4, t5
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 4
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v16, v24, v16
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    mv t5, t4
; RV32ZVBC64-NEXT:    slli t4, t4, 1
; RV32ZVBC64-NEXT:    add t4, t4, t5
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v24, v8, t0
; RV32ZVBC64-NEXT:    and t3, t3, t2
; RV32ZVBC64-NEXT:    vmul.vx v8, v24, t3
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 4
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    mv t5, t4
; RV32ZVBC64-NEXT:    slli t4, t4, 2
; RV32ZVBC64-NEXT:    add t4, t4, t5
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vx v8, v8, t1
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 5
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vx v8, v8, a0
; RV32ZVBC64-NEXT:    addi t4, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    mv t5, t4
; RV32ZVBC64-NEXT:    slli t4, t4, 1
; RV32ZVBC64-NEXT:    add t4, t4, t5
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 4
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    mv t5, t4
; RV32ZVBC64-NEXT:    slli t4, t4, 1
; RV32ZVBC64-NEXT:    add t4, t4, t5
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    addi t4, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 4
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vmul.vx v8, v0, t3
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vmul.vx v8, v24, a5
; RV32ZVBC64-NEXT:    addi t4, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 4
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    addi t4, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr t4, vlenb
; RV32ZVBC64-NEXT:    slli t4, t4, 3
; RV32ZVBC64-NEXT:    mv t5, t4
; RV32ZVBC64-NEXT:    slli t4, t4, 1
; RV32ZVBC64-NEXT:    add t4, t4, t5
; RV32ZVBC64-NEXT:    add t4, sp, t4
; RV32ZVBC64-NEXT:    addi t4, t4, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a6
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 4
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a7
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv a7, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 1
; RV32ZVBC64-NEXT:    add a6, a6, a7
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv a7, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 2
; RV32ZVBC64-NEXT:    add a6, a6, a7
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vx v8, v8, a5
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 5
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vx v8, v8, t3
; RV32ZVBC64-NEXT:    addi a6, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv a7, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 1
; RV32ZVBC64-NEXT:    add a6, a6, a7
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 4
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv a7, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 1
; RV32ZVBC64-NEXT:    add a6, a6, a7
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    addi a6, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 4
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vmul.vx v8, v0, a0
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    vmul.vx v8, v24, t1
; RV32ZVBC64-NEXT:    addi a6, sp, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 4
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    addi a6, sp, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vand.vx v8, v8, t2
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 4
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv a7, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 2
; RV32ZVBC64-NEXT:    add a6, a6, a7
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vx v8, v8, t3
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 5
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vmul.vx v8, v8, t1
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 5
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv a7, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 1
; RV32ZVBC64-NEXT:    add a6, a6, a7
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 4
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    mv a7, a6
; RV32ZVBC64-NEXT:    slli a6, a6, 2
; RV32ZVBC64-NEXT:    add a6, a6, a7
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 3
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    csrr a6, vlenb
; RV32ZVBC64-NEXT:    slli a6, a6, 5
; RV32ZVBC64-NEXT:    add a6, sp, a6
; RV32ZVBC64-NEXT:    addi a6, a6, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vmul.vx v16, v0, a5
; RV32ZVBC64-NEXT:    vmul.vx v24, v24, a0
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC64-NEXT:    vand.vx v8, v8, t0
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 3
; RV32ZVBC64-NEXT:    mv a5, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 2
; RV32ZVBC64-NEXT:    add a0, a0, a5
; RV32ZVBC64-NEXT:    add a0, sp, a0
; RV32ZVBC64-NEXT:    addi a0, a0, 16
; RV32ZVBC64-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV32ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC64-NEXT:    vsll.vi v24, v8, 24
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV32ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC64-NEXT:    vand.vx v16, v16, a4
; RV32ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV32ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC64-NEXT:    csrr a0, vlenb
; RV32ZVBC64-NEXT:    slli a0, a0, 4
; RV32ZVBC64-NEXT:    mv a1, a0
; RV32ZVBC64-NEXT:    slli a0, a0, 1
; RV32ZVBC64-NEXT:    add a0, a0, a1
; RV32ZVBC64-NEXT:    add sp, sp, a0
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv16i32_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    addi sp, sp, -16
; RV64ZVBC64-NEXT:    csrr a1, vlenb
; RV64ZVBC64-NEXT:    slli a1, a1, 3
; RV64ZVBC64-NEXT:    mv a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 1
; RV64ZVBC64-NEXT:    add a2, a2, a1
; RV64ZVBC64-NEXT:    slli a1, a1, 2
; RV64ZVBC64-NEXT:    add a1, a1, a2
; RV64ZVBC64-NEXT:    sub sp, sp, a1
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV64ZVBC64-NEXT:    vmv.v.x v16, a0
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 8
; RV64ZVBC64-NEXT:    lui a0, 16
; RV64ZVBC64-NEXT:    addi a0, a0, -256
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a0
; RV64ZVBC64-NEXT:    vsrl.vi v0, v16, 24
; RV64ZVBC64-NEXT:    vor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a0
; RV64ZVBC64-NEXT:    vsll.vi v0, v0, 8
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 24
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 4
; RV64ZVBC64-NEXT:    lui a1, 61681
; RV64ZVBC64-NEXT:    addi a1, a1, -241
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 4
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 2
; RV64ZVBC64-NEXT:    lui a2, 209715
; RV64ZVBC64-NEXT:    addi a2, a2, 819
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vsll.vi v16, v16, 2
; RV64ZVBC64-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v24, v16, 1
; RV64ZVBC64-NEXT:    lui a3, 349525
; RV64ZVBC64-NEXT:    addi a3, a3, 1365
; RV64ZVBC64-NEXT:    vand.vx v24, v24, a3
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vadd.vv v16, v16, v16
; RV64ZVBC64-NEXT:    vor.vv v0, v24, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vand.vx v24, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v24, v24, 8
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 24
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    lui a5, 69905
; RV64ZVBC64-NEXT:    addi a5, a5, 273
; RV64ZVBC64-NEXT:    vand.vx v24, v0, a5
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v8
; RV64ZVBC64-NEXT:    lui a7, 139810
; RV64ZVBC64-NEXT:    addi a7, a7, 546
; RV64ZVBC64-NEXT:    vand.vx v8, v16, a7
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a6, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vmv.v.v v8, v0
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a6, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 1
; RV64ZVBC64-NEXT:    add a4, a4, a6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v24, v0, a7
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a5
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    mv a6, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 3
; RV64ZVBC64-NEXT:    add a4, a4, a6
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a4, 559241
; RV64ZVBC64-NEXT:    addi a4, a4, -1912
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 2
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 4
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 2
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 6
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a6) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v0, v8, v0
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV64ZVBC64-NEXT:    csrr a6, vlenb
; RV64ZVBC64-NEXT:    slli a6, a6, 3
; RV64ZVBC64-NEXT:    mv t0, a6
; RV64ZVBC64-NEXT:    slli a6, a6, 1
; RV64ZVBC64-NEXT:    add a6, a6, t0
; RV64ZVBC64-NEXT:    add a6, sp, a6
; RV64ZVBC64-NEXT:    addi a6, a6, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    lui a6, 279620
; RV64ZVBC64-NEXT:    addi a6, a6, 1092
; RV64ZVBC64-NEXT:    vand.vx v8, v16, a6
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t1, t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 2
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v0
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a4
; RV64ZVBC64-NEXT:    vmul.vv v0, v16, v8
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 2
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 6
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC64-NEXT:    addi t0, sp, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    addi t0, sp, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t1, t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v24, v8
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 5
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v24
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 4
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr t0, vlenb
; RV64ZVBC64-NEXT:    slli t0, t0, 3
; RV64ZVBC64-NEXT:    mv t1, t0
; RV64ZVBC64-NEXT:    slli t0, t0, 1
; RV64ZVBC64-NEXT:    add t0, t0, t1
; RV64ZVBC64-NEXT:    add t0, sp, t0
; RV64ZVBC64-NEXT:    addi t0, t0, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC64-NEXT:    csrr a7, vlenb
; RV64ZVBC64-NEXT:    slli a7, a7, 4
; RV64ZVBC64-NEXT:    add a7, sp, a7
; RV64ZVBC64-NEXT:    addi a7, a7, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vand.vx v16, v0, a5
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v24
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v24, v24, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a7, a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v0, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v0, v0, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v24, v0
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v0, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a7, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    add a5, a5, a7
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v8, v8, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vand.vx v0, v16, a6
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 2
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 3
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a6, a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 5
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v24, v0, v16
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    csrr a5, vlenb
; RV64ZVBC64-NEXT:    slli a5, a5, 4
; RV64ZVBC64-NEXT:    mv a6, a5
; RV64ZVBC64-NEXT:    slli a5, a5, 1
; RV64ZVBC64-NEXT:    add a5, a5, a6
; RV64ZVBC64-NEXT:    add a5, sp, a5
; RV64ZVBC64-NEXT:    addi a5, a5, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vmul.vv v16, v16, v0
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC64-NEXT:    vxor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a4
; RV64ZVBC64-NEXT:    csrr a4, vlenb
; RV64ZVBC64-NEXT:    slli a4, a4, 4
; RV64ZVBC64-NEXT:    mv a5, a4
; RV64ZVBC64-NEXT:    slli a4, a4, 2
; RV64ZVBC64-NEXT:    add a4, a4, a5
; RV64ZVBC64-NEXT:    add a4, sp, a4
; RV64ZVBC64-NEXT:    addi a4, a4, 16
; RV64ZVBC64-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 8
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a0
; RV64ZVBC64-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC64-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC64-NEXT:    vsll.vi v24, v8, 24
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a0
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 8
; RV64ZVBC64-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a1
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a1
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC64-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC64-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC64-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC64-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC64-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC64-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC64-NEXT:    csrr a0, vlenb
; RV64ZVBC64-NEXT:    slli a0, a0, 3
; RV64ZVBC64-NEXT:    mv a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 1
; RV64ZVBC64-NEXT:    add a1, a1, a0
; RV64ZVBC64-NEXT:    slli a0, a0, 2
; RV64ZVBC64-NEXT:    add a0, a0, a1
; RV64ZVBC64-NEXT:    add sp, sp, a0
; RV64ZVBC64-NEXT:    addi sp, sp, 16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv16i32_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv16i32_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
; RV64ZVBC32-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i64 0
  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
  %va.ext = zext <vscale x 16 x i32> %va to <vscale x 16 x i64>
  %vb.ext = zext <vscale x 16 x i32> %vb to <vscale x 16 x i64>
  %clmul = call <vscale x 16 x i64> @llvm.clmul.nxv16i64(<vscale x 16 x i64> %va.ext, <vscale x 16 x i64> %vb.ext)
  %res.ext = lshr <vscale x 16 x i64> %clmul, splat(i64 32)
  %res = trunc <vscale x 16 x i64> %res.ext to <vscale x 16 x i32>
  ret <vscale x 16 x i32> %res
}

define <vscale x 1 x i64> @clmulh_nxv1i64_vv(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv1i64_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vx v11, v9, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v10, v9, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    vsrl.vi v12, v9, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    addi a4, sp, 8
; RV32V-NEXT:    vand.vx v13, v10, a2
; RV32V-NEXT:    sw a3, 8(sp)
; RV32V-NEXT:    sw zero, 12(sp)
; RV32V-NEXT:    vsrl.vi v14, v9, 8
; RV32V-NEXT:    vlse64.v v10, (a4), zero
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    vand.vx v12, v12, a3
; RV32V-NEXT:    vand.vv v14, v14, v10
; RV32V-NEXT:    vor.vv v11, v13, v11
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vand.vx v13, v9, a2
; RV32V-NEXT:    vsll.vx v14, v9, a0
; RV32V-NEXT:    vsll.vx v13, v13, a1
; RV32V-NEXT:    vand.vx v15, v9, a3
; RV32V-NEXT:    vand.vv v9, v9, v10
; RV32V-NEXT:    vsll.vi v15, v15, 24
; RV32V-NEXT:    vsll.vi v9, v9, 8
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v9, v15, v9
; RV32V-NEXT:    vor.vv v11, v12, v11
; RV32V-NEXT:    vor.vv v9, v13, v9
; RV32V-NEXT:    vor.vv v11, v9, v11
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v12, v11, 4
; RV32V-NEXT:    vand.vv v11, v11, v9
; RV32V-NEXT:    vand.vv v12, v12, v9
; RV32V-NEXT:    vsll.vi v11, v11, 4
; RV32V-NEXT:    vor.vv v12, v12, v11
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v11, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v13, v12, 2
; RV32V-NEXT:    vand.vv v12, v12, v11
; RV32V-NEXT:    vand.vv v13, v13, v11
; RV32V-NEXT:    vsll.vi v12, v12, 2
; RV32V-NEXT:    vor.vv v12, v13, v12
; RV32V-NEXT:    vsrl.vx v13, v8, a1
; RV32V-NEXT:    vsrl.vx v14, v8, a0
; RV32V-NEXT:    vand.vx v13, v13, a2
; RV32V-NEXT:    vsrl.vi v15, v8, 24
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v15, v15, a3
; RV32V-NEXT:    vand.vv v16, v16, v10
; RV32V-NEXT:    vor.vv v13, v13, v14
; RV32V-NEXT:    vor.vv v14, v16, v15
; RV32V-NEXT:    vand.vx v15, v8, a2
; RV32V-NEXT:    vsll.vx v16, v8, a0
; RV32V-NEXT:    vsll.vx v15, v15, a1
; RV32V-NEXT:    vand.vx v17, v8, a3
; RV32V-NEXT:    vand.vv v8, v8, v10
; RV32V-NEXT:    vsll.vi v17, v17, 24
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v15, v16, v15
; RV32V-NEXT:    vor.vv v8, v17, v8
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v8, v15, v8
; RV32V-NEXT:    vsrl.vi v14, v12, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    vor.vv v13, v8, v13
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v15, v13, 4
; RV32V-NEXT:    vand.vv v13, v13, v9
; RV32V-NEXT:    vand.vv v15, v15, v9
; RV32V-NEXT:    vsll.vi v13, v13, 4
; RV32V-NEXT:    vand.vv v14, v14, v8
; RV32V-NEXT:    vor.vv v13, v15, v13
; RV32V-NEXT:    vand.vv v12, v12, v8
; RV32V-NEXT:    vsrl.vi v15, v13, 2
; RV32V-NEXT:    vand.vv v13, v13, v11
; RV32V-NEXT:    vand.vv v15, v15, v11
; RV32V-NEXT:    vsll.vi v13, v13, 2
; RV32V-NEXT:    vadd.vv v12, v12, v12
; RV32V-NEXT:    vor.vv v13, v15, v13
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vsrl.vi v14, v13, 1
; RV32V-NEXT:    vand.vv v13, v13, v8
; RV32V-NEXT:    vand.vv v14, v14, v8
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    vadd.vv v13, v13, v13
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v15, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v14, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v16, v12, v15
; RV32V-NEXT:    vand.vv v17, v13, v14
; RV32V-NEXT:    vand.vv v18, v12, v14
; RV32V-NEXT:    vand.vv v19, v13, v15
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vmul.vv v21, v17, v16
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    vmul.vv v22, v19, v18
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v23, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v24, v12, v20
; RV32V-NEXT:    vand.vv v25, v13, v23
; RV32V-NEXT:    vxor.vv v21, v22, v21
; RV32V-NEXT:    vmul.vv v22, v25, v24
; RV32V-NEXT:    vand.vv v12, v12, v23
; RV32V-NEXT:    vand.vv v13, v13, v20
; RV32V-NEXT:    vmul.vv v26, v17, v24
; RV32V-NEXT:    vmul.vv v27, v19, v16
; RV32V-NEXT:    vxor.vv v21, v21, v22
; RV32V-NEXT:    vmul.vv v22, v13, v12
; RV32V-NEXT:    vmul.vv v28, v25, v12
; RV32V-NEXT:    vxor.vv v26, v27, v26
; RV32V-NEXT:    vmul.vv v27, v13, v18
; RV32V-NEXT:    vxor.vv v21, v21, v22
; RV32V-NEXT:    vxor.vv v22, v26, v28
; RV32V-NEXT:    vand.vv v14, v21, v14
; RV32V-NEXT:    vxor.vv v21, v22, v27
; RV32V-NEXT:    vmul.vv v22, v17, v18
; RV32V-NEXT:    vmul.vv v26, v19, v12
; RV32V-NEXT:    vand.vv v15, v21, v15
; RV32V-NEXT:    vmul.vv v21, v25, v16
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    vxor.vv v15, v26, v22
; RV32V-NEXT:    vmul.vv v12, v17, v12
; RV32V-NEXT:    vmul.vv v17, v19, v24
; RV32V-NEXT:    vxor.vv v15, v15, v21
; RV32V-NEXT:    vmul.vv v19, v13, v24
; RV32V-NEXT:    vmul.vv v18, v25, v18
; RV32V-NEXT:    vxor.vv v12, v17, v12
; RV32V-NEXT:    vmul.vv v13, v13, v16
; RV32V-NEXT:    vxor.vv v15, v15, v19
; RV32V-NEXT:    vxor.vv v12, v12, v18
; RV32V-NEXT:    vand.vv v15, v15, v23
; RV32V-NEXT:    vxor.vv v12, v12, v13
; RV32V-NEXT:    vor.vv v13, v14, v15
; RV32V-NEXT:    vand.vv v12, v12, v20
; RV32V-NEXT:    vor.vv v12, v13, v12
; RV32V-NEXT:    vsrl.vx v13, v12, a1
; RV32V-NEXT:    vsrl.vx v14, v12, a0
; RV32V-NEXT:    vand.vx v13, v13, a2
; RV32V-NEXT:    vsrl.vi v15, v12, 24
; RV32V-NEXT:    vsrl.vi v16, v12, 8
; RV32V-NEXT:    vand.vx v15, v15, a3
; RV32V-NEXT:    vand.vv v16, v16, v10
; RV32V-NEXT:    vor.vv v13, v13, v14
; RV32V-NEXT:    vor.vv v14, v16, v15
; RV32V-NEXT:    vand.vv v10, v12, v10
; RV32V-NEXT:    vand.vx v15, v12, a3
; RV32V-NEXT:    vsll.vi v10, v10, 8
; RV32V-NEXT:    vsll.vi v15, v15, 24
; RV32V-NEXT:    vand.vx v16, v12, a2
; RV32V-NEXT:    vsll.vx v12, v12, a0
; RV32V-NEXT:    vsll.vx v16, v16, a1
; RV32V-NEXT:    vor.vv v10, v15, v10
; RV32V-NEXT:    vor.vv v12, v12, v16
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v10, v12, v10
; RV32V-NEXT:    vor.vv v10, v10, v13
; RV32V-NEXT:    vsrl.vi v12, v10, 4
; RV32V-NEXT:    vand.vv v10, v10, v9
; RV32V-NEXT:    vand.vv v9, v12, v9
; RV32V-NEXT:    vsll.vi v10, v10, 4
; RV32V-NEXT:    vor.vv v9, v9, v10
; RV32V-NEXT:    vsrl.vi v10, v9, 2
; RV32V-NEXT:    vand.vv v9, v9, v11
; RV32V-NEXT:    vand.vv v10, v10, v11
; RV32V-NEXT:    vsll.vi v9, v9, 2
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v10, v9, 1
; RV32V-NEXT:    vand.vv v9, v9, v8
; RV32V-NEXT:    vand.vv v8, v10, v8
; RV32V-NEXT:    vadd.vv v9, v9, v9
; RV32V-NEXT:    vor.vv v8, v8, v9
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i64_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 56
; RV64V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV64V-NEXT:    vsrl.vx v10, v9, a0
; RV64V-NEXT:    li a1, 40
; RV64V-NEXT:    vsrl.vx v11, v9, a1
; RV64V-NEXT:    lui a2, 16
; RV64V-NEXT:    vsrl.vi v12, v9, 24
; RV64V-NEXT:    addi a2, a2, -256
; RV64V-NEXT:    vand.vx v11, v11, a2
; RV64V-NEXT:    vsrl.vi v13, v9, 8
; RV64V-NEXT:    lui a3, 4080
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    li a4, 255
; RV64V-NEXT:    slli a4, a4, 24
; RV64V-NEXT:    vand.vx v13, v13, a4
; RV64V-NEXT:    vor.vv v10, v11, v10
; RV64V-NEXT:    vor.vv v11, v13, v12
; RV64V-NEXT:    vand.vx v12, v9, a3
; RV64V-NEXT:    vand.vx v13, v9, a4
; RV64V-NEXT:    vsll.vi v12, v12, 24
; RV64V-NEXT:    vsll.vi v13, v13, 8
; RV64V-NEXT:    vand.vx v14, v9, a2
; RV64V-NEXT:    vsll.vx v9, v9, a0
; RV64V-NEXT:    vsll.vx v14, v14, a1
; RV64V-NEXT:    vor.vv v12, v12, v13
; RV64V-NEXT:    vor.vv v9, v9, v14
; RV64V-NEXT:    vor.vv v10, v11, v10
; RV64V-NEXT:    vor.vv v9, v9, v12
; RV64V-NEXT:    vor.vv v9, v9, v10
; RV64V-NEXT:    lui a5, 61681
; RV64V-NEXT:    addi a5, a5, -241
; RV64V-NEXT:    vsrl.vi v10, v9, 4
; RV64V-NEXT:    slli a6, a5, 32
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    vand.vx v9, v9, a5
; RV64V-NEXT:    vand.vx v10, v10, a5
; RV64V-NEXT:    vsll.vi v9, v9, 4
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v9, 2
; RV64V-NEXT:    lui a6, 209715
; RV64V-NEXT:    addi a6, a6, 819
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vsrl.vx v11, v8, a1
; RV64V-NEXT:    vsrl.vx v12, v8, a0
; RV64V-NEXT:    vand.vx v11, v11, a2
; RV64V-NEXT:    vsrl.vi v13, v8, 24
; RV64V-NEXT:    vsrl.vi v14, v8, 8
; RV64V-NEXT:    vand.vx v13, v13, a3
; RV64V-NEXT:    vand.vx v14, v14, a4
; RV64V-NEXT:    vor.vv v11, v11, v12
; RV64V-NEXT:    vor.vv v12, v14, v13
; RV64V-NEXT:    vand.vx v13, v8, a3
; RV64V-NEXT:    vand.vx v14, v8, a4
; RV64V-NEXT:    vsll.vi v13, v13, 24
; RV64V-NEXT:    vsll.vi v14, v14, 8
; RV64V-NEXT:    vand.vx v15, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a0
; RV64V-NEXT:    vsll.vx v15, v15, a1
; RV64V-NEXT:    vor.vv v13, v13, v14
; RV64V-NEXT:    vor.vv v8, v8, v15
; RV64V-NEXT:    vor.vv v11, v12, v11
; RV64V-NEXT:    vor.vv v8, v8, v13
; RV64V-NEXT:    vsll.vi v9, v9, 2
; RV64V-NEXT:    vor.vv v8, v8, v11
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v8, 4
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vand.vx v10, v10, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vsrl.vi v11, v9, 1
; RV64V-NEXT:    lui a7, 349525
; RV64V-NEXT:    addi a7, a7, 1365
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v10, v11, a7
; RV64V-NEXT:    vsrl.vi v11, v8, 2
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vand.vx v11, v11, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vor.vv v8, v11, v8
; RV64V-NEXT:    vadd.vv v9, v9, v9
; RV64V-NEXT:    vsrl.vi v11, v8, 1
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vand.vx v11, v11, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    lui t0, 69905
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    addi t0, t0, 273
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    vor.vv v8, v11, v8
; RV64V-NEXT:    lui t2, 139810
; RV64V-NEXT:    add t1, t0, t1
; RV64V-NEXT:    addi t0, t2, 546
; RV64V-NEXT:    vand.vx v10, v9, t1
; RV64V-NEXT:    slli t2, t0, 32
; RV64V-NEXT:    add t2, t0, t2
; RV64V-NEXT:    vand.vx v11, v8, t2
; RV64V-NEXT:    vand.vx v12, v9, t2
; RV64V-NEXT:    vand.vx v13, v8, t1
; RV64V-NEXT:    lui t0, %hi(.LCPI36_0)
; RV64V-NEXT:    vmul.vv v14, v11, v10
; RV64V-NEXT:    ld t0, %lo(.LCPI36_0)(t0)
; RV64V-NEXT:    vmul.vv v15, v13, v12
; RV64V-NEXT:    lui t3, 279620
; RV64V-NEXT:    addi t3, t3, 1092
; RV64V-NEXT:    vand.vx v16, v9, t0
; RV64V-NEXT:    slli t4, t3, 32
; RV64V-NEXT:    add t3, t3, t4
; RV64V-NEXT:    vand.vx v17, v8, t3
; RV64V-NEXT:    vxor.vv v14, v15, v14
; RV64V-NEXT:    vmul.vv v15, v17, v16
; RV64V-NEXT:    vand.vx v9, v9, t3
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vmul.vv v18, v11, v16
; RV64V-NEXT:    vmul.vv v19, v13, v10
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vmul.vv v15, v8, v9
; RV64V-NEXT:    vmul.vv v20, v17, v9
; RV64V-NEXT:    vxor.vv v18, v19, v18
; RV64V-NEXT:    vmul.vv v19, v8, v12
; RV64V-NEXT:    vxor.vv v14, v14, v15
; RV64V-NEXT:    vxor.vv v15, v18, v20
; RV64V-NEXT:    vand.vx v14, v14, t2
; RV64V-NEXT:    vxor.vv v15, v15, v19
; RV64V-NEXT:    vmul.vv v18, v11, v12
; RV64V-NEXT:    vmul.vv v19, v13, v9
; RV64V-NEXT:    vand.vx v15, v15, t1
; RV64V-NEXT:    vmul.vv v20, v17, v10
; RV64V-NEXT:    vor.vv v14, v15, v14
; RV64V-NEXT:    vxor.vv v15, v19, v18
; RV64V-NEXT:    vmul.vv v9, v11, v9
; RV64V-NEXT:    vmul.vv v11, v13, v16
; RV64V-NEXT:    vxor.vv v13, v15, v20
; RV64V-NEXT:    vmul.vv v15, v8, v16
; RV64V-NEXT:    vmul.vv v12, v17, v12
; RV64V-NEXT:    vxor.vv v9, v11, v9
; RV64V-NEXT:    vmul.vv v8, v8, v10
; RV64V-NEXT:    vxor.vv v10, v13, v15
; RV64V-NEXT:    vxor.vv v9, v9, v12
; RV64V-NEXT:    vand.vx v10, v10, t3
; RV64V-NEXT:    vxor.vv v8, v9, v8
; RV64V-NEXT:    vor.vv v9, v14, v10
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vx v9, v8, a1
; RV64V-NEXT:    vsrl.vx v10, v8, a0
; RV64V-NEXT:    vand.vx v9, v9, a2
; RV64V-NEXT:    vsrl.vi v11, v8, 24
; RV64V-NEXT:    vsrl.vi v12, v8, 8
; RV64V-NEXT:    vand.vx v11, v11, a3
; RV64V-NEXT:    vand.vx v12, v12, a4
; RV64V-NEXT:    vor.vv v9, v9, v10
; RV64V-NEXT:    vor.vv v10, v12, v11
; RV64V-NEXT:    vand.vx v11, v8, a4
; RV64V-NEXT:    vand.vx v12, v8, a3
; RV64V-NEXT:    vsll.vi v11, v11, 8
; RV64V-NEXT:    vsll.vi v12, v12, 24
; RV64V-NEXT:    vand.vx v13, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a0
; RV64V-NEXT:    vsll.vx v13, v13, a1
; RV64V-NEXT:    vor.vv v11, v12, v11
; RV64V-NEXT:    vor.vv v8, v8, v13
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vor.vv v8, v8, v11
; RV64V-NEXT:    vor.vv v8, v8, v9
; RV64V-NEXT:    vsrl.vi v9, v8, 4
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vand.vx v9, v9, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vi v9, v8, 2
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vi v9, v8, 1
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i64_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i64_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vv v8, v8, v9
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i64_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -16
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vx v11, v9, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v10, v9, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    vsrl.vi v12, v9, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    addi a4, sp, 8
; RV32ZVBC32-NEXT:    vand.vx v13, v10, a2
; RV32ZVBC32-NEXT:    sw a3, 8(sp)
; RV32ZVBC32-NEXT:    sw zero, 12(sp)
; RV32ZVBC32-NEXT:    vsrl.vi v14, v9, 8
; RV32ZVBC32-NEXT:    vlse64.v v10, (a4), zero
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v10
; RV32ZVBC32-NEXT:    vor.vv v11, v13, v11
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vand.vx v13, v9, a2
; RV32ZVBC32-NEXT:    vsll.vx v14, v9, a0
; RV32ZVBC32-NEXT:    vsll.vx v13, v13, a1
; RV32ZVBC32-NEXT:    vand.vx v15, v9, a3
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v10
; RV32ZVBC32-NEXT:    vsll.vi v15, v15, 24
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 8
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v9, v15, v9
; RV32ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV32ZVBC32-NEXT:    vor.vv v9, v13, v9
; RV32ZVBC32-NEXT:    vor.vv v11, v9, v11
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v9, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v12, v11, 4
; RV32ZVBC32-NEXT:    vand.vv v11, v11, v9
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v9
; RV32ZVBC32-NEXT:    vsll.vi v11, v11, 4
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v11
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v11, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v13, v12, 2
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v11
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v11
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 2
; RV32ZVBC32-NEXT:    vor.vv v12, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vx v13, v8, a1
; RV32ZVBC32-NEXT:    vsrl.vx v14, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v13, v13, a2
; RV32ZVBC32-NEXT:    vsrl.vi v15, v8, 24
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC32-NEXT:    vand.vx v15, v15, a3
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v10
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v15
; RV32ZVBC32-NEXT:    vand.vx v15, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v16, v8, a0
; RV32ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV32ZVBC32-NEXT:    vand.vx v17, v8, a3
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v10
; RV32ZVBC32-NEXT:    vsll.vi v17, v17, 24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v15, v16, v15
; RV32ZVBC32-NEXT:    vor.vv v8, v17, v8
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v8, v15, v8
; RV32ZVBC32-NEXT:    vsrl.vi v14, v12, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    vor.vv v13, v8, v13
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v15, v13, 4
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v9
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v9
; RV32ZVBC32-NEXT:    vsll.vi v13, v13, 4
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v8
; RV32ZVBC32-NEXT:    vor.vv v13, v15, v13
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v15, v13, 2
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v11
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v11
; RV32ZVBC32-NEXT:    vsll.vi v13, v13, 2
; RV32ZVBC32-NEXT:    vadd.vv v12, v12, v12
; RV32ZVBC32-NEXT:    vor.vv v13, v15, v13
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vsrl.vi v14, v13, 1
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v8
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v8
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    vadd.vv v13, v13, v13
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v15, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v14, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v12, v15
; RV32ZVBC32-NEXT:    vand.vv v17, v13, v14
; RV32ZVBC32-NEXT:    vand.vv v18, v12, v14
; RV32ZVBC32-NEXT:    vand.vv v19, v13, v15
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vmul.vv v21, v17, v16
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    vmul.vv v22, v19, v18
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v23, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v12, v20
; RV32ZVBC32-NEXT:    vand.vv v25, v13, v23
; RV32ZVBC32-NEXT:    vxor.vv v21, v22, v21
; RV32ZVBC32-NEXT:    vmul.vv v22, v25, v24
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v23
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v20
; RV32ZVBC32-NEXT:    vmul.vv v26, v17, v24
; RV32ZVBC32-NEXT:    vmul.vv v27, v19, v16
; RV32ZVBC32-NEXT:    vxor.vv v21, v21, v22
; RV32ZVBC32-NEXT:    vmul.vv v22, v13, v12
; RV32ZVBC32-NEXT:    vmul.vv v28, v25, v12
; RV32ZVBC32-NEXT:    vxor.vv v26, v27, v26
; RV32ZVBC32-NEXT:    vmul.vv v27, v13, v18
; RV32ZVBC32-NEXT:    vxor.vv v21, v21, v22
; RV32ZVBC32-NEXT:    vxor.vv v22, v26, v28
; RV32ZVBC32-NEXT:    vand.vv v14, v21, v14
; RV32ZVBC32-NEXT:    vxor.vv v21, v22, v27
; RV32ZVBC32-NEXT:    vmul.vv v22, v17, v18
; RV32ZVBC32-NEXT:    vmul.vv v26, v19, v12
; RV32ZVBC32-NEXT:    vand.vv v15, v21, v15
; RV32ZVBC32-NEXT:    vmul.vv v21, v25, v16
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v14
; RV32ZVBC32-NEXT:    vxor.vv v15, v26, v22
; RV32ZVBC32-NEXT:    vmul.vv v12, v17, v12
; RV32ZVBC32-NEXT:    vmul.vv v17, v19, v24
; RV32ZVBC32-NEXT:    vxor.vv v15, v15, v21
; RV32ZVBC32-NEXT:    vmul.vv v19, v13, v24
; RV32ZVBC32-NEXT:    vmul.vv v18, v25, v18
; RV32ZVBC32-NEXT:    vxor.vv v12, v17, v12
; RV32ZVBC32-NEXT:    vmul.vv v13, v13, v16
; RV32ZVBC32-NEXT:    vxor.vv v15, v15, v19
; RV32ZVBC32-NEXT:    vxor.vv v12, v12, v18
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v23
; RV32ZVBC32-NEXT:    vxor.vv v12, v12, v13
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v15
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vor.vv v12, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vx v13, v12, a1
; RV32ZVBC32-NEXT:    vsrl.vx v14, v12, a0
; RV32ZVBC32-NEXT:    vand.vx v13, v13, a2
; RV32ZVBC32-NEXT:    vsrl.vi v15, v12, 24
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 8
; RV32ZVBC32-NEXT:    vand.vx v15, v15, a3
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v10
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v15
; RV32ZVBC32-NEXT:    vand.vv v10, v12, v10
; RV32ZVBC32-NEXT:    vand.vx v15, v12, a3
; RV32ZVBC32-NEXT:    vsll.vi v10, v10, 8
; RV32ZVBC32-NEXT:    vsll.vi v15, v15, 24
; RV32ZVBC32-NEXT:    vand.vx v16, v12, a2
; RV32ZVBC32-NEXT:    vsll.vx v12, v12, a0
; RV32ZVBC32-NEXT:    vsll.vx v16, v16, a1
; RV32ZVBC32-NEXT:    vor.vv v10, v15, v10
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v13
; RV32ZVBC32-NEXT:    vsrl.vi v12, v10, 4
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v9
; RV32ZVBC32-NEXT:    vand.vv v9, v12, v9
; RV32ZVBC32-NEXT:    vsll.vi v10, v10, 4
; RV32ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v11
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v11
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 1
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v8
; RV32ZVBC32-NEXT:    vand.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v9
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    addi sp, sp, 16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i64_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    li a0, 56
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v10, v9, a0
; RV64ZVBC32-NEXT:    li a1, 40
; RV64ZVBC32-NEXT:    vsrl.vx v11, v9, a1
; RV64ZVBC32-NEXT:    lui a2, 16
; RV64ZVBC32-NEXT:    vsrl.vi v12, v9, 24
; RV64ZVBC32-NEXT:    addi a2, a2, -256
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a2
; RV64ZVBC32-NEXT:    vsrl.vi v13, v9, 8
; RV64ZVBC32-NEXT:    lui a3, 4080
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV64ZVBC32-NEXT:    li a4, 255
; RV64ZVBC32-NEXT:    slli a4, a4, 24
; RV64ZVBC32-NEXT:    vand.vx v13, v13, a4
; RV64ZVBC32-NEXT:    vor.vv v10, v11, v10
; RV64ZVBC32-NEXT:    vor.vv v11, v13, v12
; RV64ZVBC32-NEXT:    vand.vx v12, v9, a3
; RV64ZVBC32-NEXT:    vand.vx v13, v9, a4
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 24
; RV64ZVBC32-NEXT:    vsll.vi v13, v13, 8
; RV64ZVBC32-NEXT:    vand.vx v14, v9, a2
; RV64ZVBC32-NEXT:    vsll.vx v9, v9, a0
; RV64ZVBC32-NEXT:    vsll.vx v14, v14, a1
; RV64ZVBC32-NEXT:    vor.vv v12, v12, v13
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v14
; RV64ZVBC32-NEXT:    vor.vv v10, v11, v10
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v12
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV64ZVBC32-NEXT:    lui a5, 61681
; RV64ZVBC32-NEXT:    addi a5, a5, -241
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 4
; RV64ZVBC32-NEXT:    slli a6, a5, 32
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a5
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a5
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 4
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV64ZVBC32-NEXT:    lui a6, 209715
; RV64ZVBC32-NEXT:    addi a6, a6, 819
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vsrl.vx v11, v8, a1
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a2
; RV64ZVBC32-NEXT:    vsrl.vi v13, v8, 24
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v13, v13, a3
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a4
; RV64ZVBC32-NEXT:    vor.vv v11, v11, v12
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v13
; RV64ZVBC32-NEXT:    vand.vx v13, v8, a3
; RV64ZVBC32-NEXT:    vand.vx v14, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v13, v13, 24
; RV64ZVBC32-NEXT:    vsll.vi v14, v14, 8
; RV64ZVBC32-NEXT:    vand.vx v15, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a0
; RV64ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV64ZVBC32-NEXT:    vor.vv v13, v13, v14
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v15
; RV64ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v13
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v11
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vsrl.vi v11, v9, 1
; RV64ZVBC32-NEXT:    lui a7, 349525
; RV64ZVBC32-NEXT:    addi a7, a7, 1365
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v10, v11, a7
; RV64ZVBC32-NEXT:    vsrl.vi v11, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vor.vv v8, v11, v8
; RV64ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV64ZVBC32-NEXT:    vsrl.vi v11, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    lui t0, 69905
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    addi t0, t0, 273
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    vor.vv v8, v11, v8
; RV64ZVBC32-NEXT:    lui t2, 139810
; RV64ZVBC32-NEXT:    add t1, t0, t1
; RV64ZVBC32-NEXT:    addi t0, t2, 546
; RV64ZVBC32-NEXT:    vand.vx v10, v9, t1
; RV64ZVBC32-NEXT:    slli t2, t0, 32
; RV64ZVBC32-NEXT:    add t2, t0, t2
; RV64ZVBC32-NEXT:    vand.vx v11, v8, t2
; RV64ZVBC32-NEXT:    vand.vx v12, v9, t2
; RV64ZVBC32-NEXT:    vand.vx v13, v8, t1
; RV64ZVBC32-NEXT:    lui t0, %hi(.LCPI36_0)
; RV64ZVBC32-NEXT:    vmul.vv v14, v11, v10
; RV64ZVBC32-NEXT:    ld t0, %lo(.LCPI36_0)(t0)
; RV64ZVBC32-NEXT:    vmul.vv v15, v13, v12
; RV64ZVBC32-NEXT:    lui t3, 279620
; RV64ZVBC32-NEXT:    addi t3, t3, 1092
; RV64ZVBC32-NEXT:    vand.vx v16, v9, t0
; RV64ZVBC32-NEXT:    slli t4, t3, 32
; RV64ZVBC32-NEXT:    add t3, t3, t4
; RV64ZVBC32-NEXT:    vand.vx v17, v8, t3
; RV64ZVBC32-NEXT:    vxor.vv v14, v15, v14
; RV64ZVBC32-NEXT:    vmul.vv v15, v17, v16
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t3
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vmul.vv v18, v11, v16
; RV64ZVBC32-NEXT:    vmul.vv v19, v13, v10
; RV64ZVBC32-NEXT:    vxor.vv v14, v14, v15
; RV64ZVBC32-NEXT:    vmul.vv v15, v8, v9
; RV64ZVBC32-NEXT:    vmul.vv v20, v17, v9
; RV64ZVBC32-NEXT:    vxor.vv v18, v19, v18
; RV64ZVBC32-NEXT:    vmul.vv v19, v8, v12
; RV64ZVBC32-NEXT:    vxor.vv v14, v14, v15
; RV64ZVBC32-NEXT:    vxor.vv v15, v18, v20
; RV64ZVBC32-NEXT:    vand.vx v14, v14, t2
; RV64ZVBC32-NEXT:    vxor.vv v15, v15, v19
; RV64ZVBC32-NEXT:    vmul.vv v18, v11, v12
; RV64ZVBC32-NEXT:    vmul.vv v19, v13, v9
; RV64ZVBC32-NEXT:    vand.vx v15, v15, t1
; RV64ZVBC32-NEXT:    vmul.vv v20, v17, v10
; RV64ZVBC32-NEXT:    vor.vv v14, v15, v14
; RV64ZVBC32-NEXT:    vxor.vv v15, v19, v18
; RV64ZVBC32-NEXT:    vmul.vv v9, v11, v9
; RV64ZVBC32-NEXT:    vmul.vv v11, v13, v16
; RV64ZVBC32-NEXT:    vxor.vv v13, v15, v20
; RV64ZVBC32-NEXT:    vmul.vv v15, v8, v16
; RV64ZVBC32-NEXT:    vmul.vv v12, v17, v12
; RV64ZVBC32-NEXT:    vxor.vv v9, v11, v9
; RV64ZVBC32-NEXT:    vmul.vv v8, v8, v10
; RV64ZVBC32-NEXT:    vxor.vv v10, v13, v15
; RV64ZVBC32-NEXT:    vxor.vv v9, v9, v12
; RV64ZVBC32-NEXT:    vand.vx v10, v10, t3
; RV64ZVBC32-NEXT:    vxor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vor.vv v9, v14, v10
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vx v9, v8, a1
; RV64ZVBC32-NEXT:    vsrl.vx v10, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a2
; RV64ZVBC32-NEXT:    vsrl.vi v11, v8, 24
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a3
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a4
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v11
; RV64ZVBC32-NEXT:    vand.vx v11, v8, a4
; RV64ZVBC32-NEXT:    vand.vx v12, v8, a3
; RV64ZVBC32-NEXT:    vsll.vi v11, v11, 8
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 24
; RV64ZVBC32-NEXT:    vand.vx v13, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a0
; RV64ZVBC32-NEXT:    vsll.vx v13, v13, a1
; RV64ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v13
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v11
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v9
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 1 x i64> %va to <vscale x 1 x i128>
  %vb.ext = zext <vscale x 1 x i64> %vb to <vscale x 1 x i128>
  %clmul = call <vscale x 1 x i128> @llvm.clmul.nxv1i128(<vscale x 1 x i128> %va.ext, <vscale x 1 x i128> %vb.ext)
  %res.ext = lshr <vscale x 1 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 1 x i128> %res.ext to <vscale x 1 x i64>
  ret <vscale x 1 x i64> %res
}

define <vscale x 1 x i64> @clmulh_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) nounwind {
; RV32V-LABEL: clmulh_nxv1i64_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    sw a0, 0(sp)
; RV32V-NEXT:    sw a1, 4(sp)
; RV32V-NEXT:    mv a0, sp
; RV32V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32V-NEXT:    vlse64.v v10, (a0), zero
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsrl.vx v11, v10, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v12, v10, a1
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    vsrl.vi v13, v10, 24
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a4, sp, 8
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vsrl.vi v14, v10, 8
; RV32V-NEXT:    sw a3, 8(sp)
; RV32V-NEXT:    sw zero, 12(sp)
; RV32V-NEXT:    vlse64.v v9, (a4), zero
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    vand.vx v13, v13, a3
; RV32V-NEXT:    vand.vv v14, v14, v9
; RV32V-NEXT:    vor.vv v11, v12, v11
; RV32V-NEXT:    vor.vv v12, v14, v13
; RV32V-NEXT:    vand.vv v13, v10, v9
; RV32V-NEXT:    vand.vx v14, v10, a3
; RV32V-NEXT:    vsll.vi v13, v13, 8
; RV32V-NEXT:    vsll.vi v14, v14, 24
; RV32V-NEXT:    vand.vx v15, v10, a2
; RV32V-NEXT:    vsll.vx v10, v10, a0
; RV32V-NEXT:    vsll.vx v15, v15, a1
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v10, v10, v15
; RV32V-NEXT:    vor.vv v11, v12, v11
; RV32V-NEXT:    vor.vv v10, v10, v13
; RV32V-NEXT:    vor.vv v11, v10, v11
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v10, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v12, v11, 4
; RV32V-NEXT:    vand.vv v11, v11, v10
; RV32V-NEXT:    vand.vv v12, v12, v10
; RV32V-NEXT:    vsll.vi v11, v11, 4
; RV32V-NEXT:    vor.vv v12, v12, v11
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v11, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v13, v12, 2
; RV32V-NEXT:    vand.vv v12, v12, v11
; RV32V-NEXT:    vand.vv v13, v13, v11
; RV32V-NEXT:    vsll.vi v12, v12, 2
; RV32V-NEXT:    vor.vv v12, v13, v12
; RV32V-NEXT:    vsrl.vx v13, v8, a1
; RV32V-NEXT:    vsrl.vx v14, v8, a0
; RV32V-NEXT:    vand.vx v13, v13, a2
; RV32V-NEXT:    vsrl.vi v15, v8, 24
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v15, v15, a3
; RV32V-NEXT:    vand.vv v16, v16, v9
; RV32V-NEXT:    vor.vv v13, v13, v14
; RV32V-NEXT:    vor.vv v14, v16, v15
; RV32V-NEXT:    vand.vx v15, v8, a2
; RV32V-NEXT:    vsll.vx v16, v8, a0
; RV32V-NEXT:    vsll.vx v15, v15, a1
; RV32V-NEXT:    vand.vx v17, v8, a3
; RV32V-NEXT:    vand.vv v8, v8, v9
; RV32V-NEXT:    vsll.vi v17, v17, 24
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v15, v16, v15
; RV32V-NEXT:    vor.vv v8, v17, v8
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v8, v15, v8
; RV32V-NEXT:    vsrl.vi v14, v12, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    vor.vv v13, v8, v13
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v15, v13, 4
; RV32V-NEXT:    vand.vv v13, v13, v10
; RV32V-NEXT:    vand.vv v15, v15, v10
; RV32V-NEXT:    vsll.vi v13, v13, 4
; RV32V-NEXT:    vand.vv v14, v14, v8
; RV32V-NEXT:    vor.vv v13, v15, v13
; RV32V-NEXT:    vand.vv v12, v12, v8
; RV32V-NEXT:    vsrl.vi v15, v13, 2
; RV32V-NEXT:    vand.vv v13, v13, v11
; RV32V-NEXT:    vand.vv v15, v15, v11
; RV32V-NEXT:    vsll.vi v13, v13, 2
; RV32V-NEXT:    vadd.vv v12, v12, v12
; RV32V-NEXT:    vor.vv v13, v15, v13
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vsrl.vi v14, v13, 1
; RV32V-NEXT:    vand.vv v13, v13, v8
; RV32V-NEXT:    vand.vv v14, v14, v8
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    vadd.vv v13, v13, v13
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v15, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v14, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v16, v12, v15
; RV32V-NEXT:    vand.vv v17, v13, v14
; RV32V-NEXT:    vand.vv v18, v12, v14
; RV32V-NEXT:    vand.vv v19, v13, v15
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vmul.vv v21, v17, v16
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    vmul.vv v22, v19, v18
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v23, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v24, v12, v20
; RV32V-NEXT:    vand.vv v25, v13, v23
; RV32V-NEXT:    vxor.vv v21, v22, v21
; RV32V-NEXT:    vmul.vv v22, v25, v24
; RV32V-NEXT:    vand.vv v12, v12, v23
; RV32V-NEXT:    vand.vv v13, v13, v20
; RV32V-NEXT:    vmul.vv v26, v17, v24
; RV32V-NEXT:    vmul.vv v27, v19, v16
; RV32V-NEXT:    vxor.vv v21, v21, v22
; RV32V-NEXT:    vmul.vv v22, v13, v12
; RV32V-NEXT:    vmul.vv v28, v25, v12
; RV32V-NEXT:    vxor.vv v26, v27, v26
; RV32V-NEXT:    vmul.vv v27, v13, v18
; RV32V-NEXT:    vxor.vv v21, v21, v22
; RV32V-NEXT:    vxor.vv v22, v26, v28
; RV32V-NEXT:    vand.vv v14, v21, v14
; RV32V-NEXT:    vxor.vv v21, v22, v27
; RV32V-NEXT:    vmul.vv v22, v17, v18
; RV32V-NEXT:    vmul.vv v26, v19, v12
; RV32V-NEXT:    vand.vv v15, v21, v15
; RV32V-NEXT:    vmul.vv v21, v25, v16
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    vxor.vv v15, v26, v22
; RV32V-NEXT:    vmul.vv v12, v17, v12
; RV32V-NEXT:    vmul.vv v17, v19, v24
; RV32V-NEXT:    vxor.vv v15, v15, v21
; RV32V-NEXT:    vmul.vv v19, v13, v24
; RV32V-NEXT:    vmul.vv v18, v25, v18
; RV32V-NEXT:    vxor.vv v12, v17, v12
; RV32V-NEXT:    vmul.vv v13, v13, v16
; RV32V-NEXT:    vxor.vv v15, v15, v19
; RV32V-NEXT:    vxor.vv v12, v12, v18
; RV32V-NEXT:    vand.vv v15, v15, v23
; RV32V-NEXT:    vxor.vv v12, v12, v13
; RV32V-NEXT:    vor.vv v13, v14, v15
; RV32V-NEXT:    vand.vv v12, v12, v20
; RV32V-NEXT:    vor.vv v12, v13, v12
; RV32V-NEXT:    vsrl.vx v13, v12, a1
; RV32V-NEXT:    vsrl.vx v14, v12, a0
; RV32V-NEXT:    vand.vx v13, v13, a2
; RV32V-NEXT:    vsrl.vi v15, v12, 24
; RV32V-NEXT:    vsrl.vi v16, v12, 8
; RV32V-NEXT:    vand.vx v15, v15, a3
; RV32V-NEXT:    vand.vv v16, v16, v9
; RV32V-NEXT:    vor.vv v13, v13, v14
; RV32V-NEXT:    vor.vv v14, v16, v15
; RV32V-NEXT:    vand.vv v9, v12, v9
; RV32V-NEXT:    vand.vx v15, v12, a3
; RV32V-NEXT:    vsll.vi v9, v9, 8
; RV32V-NEXT:    vsll.vi v15, v15, 24
; RV32V-NEXT:    vand.vx v16, v12, a2
; RV32V-NEXT:    vsll.vx v12, v12, a0
; RV32V-NEXT:    vsll.vx v16, v16, a1
; RV32V-NEXT:    vor.vv v9, v15, v9
; RV32V-NEXT:    vor.vv v12, v12, v16
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v9, v12, v9
; RV32V-NEXT:    vor.vv v9, v9, v13
; RV32V-NEXT:    vsrl.vi v12, v9, 4
; RV32V-NEXT:    vand.vv v9, v9, v10
; RV32V-NEXT:    vand.vv v10, v12, v10
; RV32V-NEXT:    vsll.vi v9, v9, 4
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v10, v9, 2
; RV32V-NEXT:    vand.vv v9, v9, v11
; RV32V-NEXT:    vand.vv v10, v10, v11
; RV32V-NEXT:    vsll.vi v9, v9, 2
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v10, v9, 1
; RV32V-NEXT:    vand.vv v9, v9, v8
; RV32V-NEXT:    vand.vv v8, v10, v8
; RV32V-NEXT:    vadd.vv v9, v9, v9
; RV32V-NEXT:    vor.vv v8, v8, v9
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i64_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64V-NEXT:    li a1, 56
; RV64V-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
; RV64V-NEXT:    vsrl.vx v9, v8, a1
; RV64V-NEXT:    li a2, 40
; RV64V-NEXT:    vsrl.vx v10, v8, a2
; RV64V-NEXT:    lui a3, 16
; RV64V-NEXT:    vsrl.vi v11, v8, 24
; RV64V-NEXT:    addi a3, a3, -256
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vsrl.vi v12, v8, 8
; RV64V-NEXT:    lui a4, 4080
; RV64V-NEXT:    vand.vx v11, v11, a4
; RV64V-NEXT:    li a5, 255
; RV64V-NEXT:    slli a5, a5, 24
; RV64V-NEXT:    vand.vx v12, v12, a5
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vor.vv v10, v12, v11
; RV64V-NEXT:    vand.vx v11, v8, a4
; RV64V-NEXT:    vand.vx v12, v8, a5
; RV64V-NEXT:    vsll.vi v11, v11, 24
; RV64V-NEXT:    vsll.vi v12, v12, 8
; RV64V-NEXT:    vand.vx v13, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vsll.vx v13, v13, a2
; RV64V-NEXT:    vor.vv v11, v11, v12
; RV64V-NEXT:    vor.vv v8, v8, v13
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vor.vv v8, v8, v11
; RV64V-NEXT:    vor.vv v8, v8, v9
; RV64V-NEXT:    lui a6, 61681
; RV64V-NEXT:    addi a6, a6, -241
; RV64V-NEXT:    vsrl.vi v9, v8, 4
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    lui a7, 209715
; RV64V-NEXT:    addi a7, a7, 819
; RV64V-NEXT:    vsrl.vi v9, v8, 2
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    lui t0, 349525
; RV64V-NEXT:    addi t0, t0, 1365
; RV64V-NEXT:    vsrl.vi v9, v8, 1
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vand.vx v9, v9, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    lui t1, 139810
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    addi t1, t1, 546
; RV64V-NEXT:    srli t2, a0, 24
; RV64V-NEXT:    srli t3, a0, 8
; RV64V-NEXT:    and t2, t2, a4
; RV64V-NEXT:    and t3, t3, a5
; RV64V-NEXT:    or t2, t3, t2
; RV64V-NEXT:    srli t3, a0, 40
; RV64V-NEXT:    and t3, t3, a3
; RV64V-NEXT:    srli t4, a0, 56
; RV64V-NEXT:    or t3, t3, t4
; RV64V-NEXT:    and t4, a0, a4
; RV64V-NEXT:    slli t4, t4, 24
; RV64V-NEXT:    srliw t5, a0, 24
; RV64V-NEXT:    slli t5, t5, 32
; RV64V-NEXT:    and t6, a0, a3
; RV64V-NEXT:    slli t6, t6, 40
; RV64V-NEXT:    slli a0, a0, 56
; RV64V-NEXT:    or t4, t4, t5
; RV64V-NEXT:    or a0, a0, t6
; RV64V-NEXT:    or t2, t2, t3
; RV64V-NEXT:    or a0, a0, t4
; RV64V-NEXT:    slli t3, t1, 32
; RV64V-NEXT:    or a0, a0, t2
; RV64V-NEXT:    srli t2, a0, 4
; RV64V-NEXT:    and a0, a0, a6
; RV64V-NEXT:    and t2, t2, a6
; RV64V-NEXT:    slli t4, a0, 4
; RV64V-NEXT:    add a0, t1, t3
; RV64V-NEXT:    or t1, t2, t4
; RV64V-NEXT:    srli t2, t1, 2
; RV64V-NEXT:    and t1, t1, a7
; RV64V-NEXT:    and t2, t2, a7
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    vand.vx v9, v8, a0
; RV64V-NEXT:    or t1, t2, t1
; RV64V-NEXT:    srli t2, t1, 1
; RV64V-NEXT:    lui t3, 69905
; RV64V-NEXT:    and t2, t2, t0
; RV64V-NEXT:    addi t3, t3, 273
; RV64V-NEXT:    and t1, t1, t0
; RV64V-NEXT:    slli t4, t3, 32
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t3, t3, t4
; RV64V-NEXT:    or t2, t2, t1
; RV64V-NEXT:    vand.vx v10, v8, t3
; RV64V-NEXT:    and t1, t2, t3
; RV64V-NEXT:    vmul.vx v11, v9, t1
; RV64V-NEXT:    and t4, t2, a0
; RV64V-NEXT:    lui t5, 279620
; RV64V-NEXT:    vmul.vx v12, v10, t4
; RV64V-NEXT:    addi t5, t5, 1092
; RV64V-NEXT:    slli t6, t5, 32
; RV64V-NEXT:    lui s0, %hi(.LCPI37_0)
; RV64V-NEXT:    add t5, t5, t6
; RV64V-NEXT:    ld t6, %lo(.LCPI37_0)(s0)
; RV64V-NEXT:    vand.vx v13, v8, t5
; RV64V-NEXT:    and s0, t2, t6
; RV64V-NEXT:    vmul.vx v14, v13, s0
; RV64V-NEXT:    vxor.vv v11, v12, v11
; RV64V-NEXT:    vand.vx v8, v8, t6
; RV64V-NEXT:    vmul.vx v12, v9, s0
; RV64V-NEXT:    vmul.vx v15, v10, t1
; RV64V-NEXT:    vxor.vv v11, v11, v14
; RV64V-NEXT:    and t2, t2, t5
; RV64V-NEXT:    vmul.vx v14, v8, t2
; RV64V-NEXT:    vmul.vx v16, v13, t2
; RV64V-NEXT:    vxor.vv v12, v15, v12
; RV64V-NEXT:    vmul.vx v15, v8, t4
; RV64V-NEXT:    vxor.vv v11, v11, v14
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vand.vx v11, v11, a0
; RV64V-NEXT:    vxor.vv v12, v12, v15
; RV64V-NEXT:    vmul.vx v14, v9, t4
; RV64V-NEXT:    vmul.vx v15, v10, t2
; RV64V-NEXT:    vand.vx v12, v12, t3
; RV64V-NEXT:    vmul.vx v16, v13, t1
; RV64V-NEXT:    vor.vv v11, v12, v11
; RV64V-NEXT:    vxor.vv v12, v15, v14
; RV64V-NEXT:    vmul.vx v9, v9, t2
; RV64V-NEXT:    vmul.vx v10, v10, s0
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vmul.vx v14, v8, s0
; RV64V-NEXT:    vmul.vx v13, v13, t4
; RV64V-NEXT:    vxor.vv v9, v10, v9
; RV64V-NEXT:    vmul.vx v8, v8, t1
; RV64V-NEXT:    vxor.vv v10, v12, v14
; RV64V-NEXT:    vxor.vv v9, v9, v13
; RV64V-NEXT:    vand.vx v10, v10, t5
; RV64V-NEXT:    vxor.vv v8, v9, v8
; RV64V-NEXT:    vor.vv v9, v11, v10
; RV64V-NEXT:    vand.vx v8, v8, t6
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vx v9, v8, a2
; RV64V-NEXT:    vsrl.vx v10, v8, a1
; RV64V-NEXT:    vand.vx v9, v9, a3
; RV64V-NEXT:    vsrl.vi v11, v8, 24
; RV64V-NEXT:    vsrl.vi v12, v8, 8
; RV64V-NEXT:    vand.vx v11, v11, a4
; RV64V-NEXT:    vand.vx v12, v12, a5
; RV64V-NEXT:    vor.vv v9, v9, v10
; RV64V-NEXT:    vor.vv v10, v12, v11
; RV64V-NEXT:    vand.vx v11, v8, a5
; RV64V-NEXT:    vand.vx v12, v8, a4
; RV64V-NEXT:    vsll.vi v11, v11, 8
; RV64V-NEXT:    vsll.vi v12, v12, 24
; RV64V-NEXT:    vand.vx v13, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vsll.vx v13, v13, a2
; RV64V-NEXT:    vor.vv v11, v12, v11
; RV64V-NEXT:    vor.vv v8, v8, v13
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vor.vv v8, v8, v11
; RV64V-NEXT:    vor.vv v8, v8, v9
; RV64V-NEXT:    vsrl.vi v9, v8, 4
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vi v9, v8, 2
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vi v9, v8, 1
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vand.vx v9, v9, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v9, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i64_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    sw a0, 8(sp)
; RV32ZVBC64-NEXT:    sw a1, 12(sp)
; RV32ZVBC64-NEXT:    addi a0, sp, 8
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32ZVBC64-NEXT:    vlse64.v v9, (a0), zero
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v9
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i64_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i64_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -16
; RV32ZVBC32-NEXT:    sw a0, 0(sp)
; RV32ZVBC32-NEXT:    sw a1, 4(sp)
; RV32ZVBC32-NEXT:    mv a0, sp
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vlse64.v v10, (a0), zero
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsrl.vx v11, v10, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v12, v10, a1
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    vsrl.vi v13, v10, 24
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a4, sp, 8
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vsrl.vi v14, v10, 8
; RV32ZVBC32-NEXT:    sw a3, 8(sp)
; RV32ZVBC32-NEXT:    sw zero, 12(sp)
; RV32ZVBC32-NEXT:    vlse64.v v9, (a4), zero
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    vand.vx v13, v13, a3
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v9
; RV32ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v13
; RV32ZVBC32-NEXT:    vand.vv v13, v10, v9
; RV32ZVBC32-NEXT:    vand.vx v14, v10, a3
; RV32ZVBC32-NEXT:    vsll.vi v13, v13, 8
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 24
; RV32ZVBC32-NEXT:    vand.vx v15, v10, a2
; RV32ZVBC32-NEXT:    vsll.vx v10, v10, a0
; RV32ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v15
; RV32ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v13
; RV32ZVBC32-NEXT:    vor.vv v11, v10, v11
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v10, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v12, v11, 4
; RV32ZVBC32-NEXT:    vand.vv v11, v11, v10
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v10
; RV32ZVBC32-NEXT:    vsll.vi v11, v11, 4
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v11
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v11, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v13, v12, 2
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v11
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v11
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 2
; RV32ZVBC32-NEXT:    vor.vv v12, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vx v13, v8, a1
; RV32ZVBC32-NEXT:    vsrl.vx v14, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v13, v13, a2
; RV32ZVBC32-NEXT:    vsrl.vi v15, v8, 24
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC32-NEXT:    vand.vx v15, v15, a3
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v9
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v15
; RV32ZVBC32-NEXT:    vand.vx v15, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v16, v8, a0
; RV32ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV32ZVBC32-NEXT:    vand.vx v17, v8, a3
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v9
; RV32ZVBC32-NEXT:    vsll.vi v17, v17, 24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v15, v16, v15
; RV32ZVBC32-NEXT:    vor.vv v8, v17, v8
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v8, v15, v8
; RV32ZVBC32-NEXT:    vsrl.vi v14, v12, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    vor.vv v13, v8, v13
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v15, v13, 4
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v10
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v10
; RV32ZVBC32-NEXT:    vsll.vi v13, v13, 4
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v8
; RV32ZVBC32-NEXT:    vor.vv v13, v15, v13
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v15, v13, 2
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v11
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v11
; RV32ZVBC32-NEXT:    vsll.vi v13, v13, 2
; RV32ZVBC32-NEXT:    vadd.vv v12, v12, v12
; RV32ZVBC32-NEXT:    vor.vv v13, v15, v13
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vsrl.vi v14, v13, 1
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v8
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v8
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    vadd.vv v13, v13, v13
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v15, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v14, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v12, v15
; RV32ZVBC32-NEXT:    vand.vv v17, v13, v14
; RV32ZVBC32-NEXT:    vand.vv v18, v12, v14
; RV32ZVBC32-NEXT:    vand.vv v19, v13, v15
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vmul.vv v21, v17, v16
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    vmul.vv v22, v19, v18
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v23, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v12, v20
; RV32ZVBC32-NEXT:    vand.vv v25, v13, v23
; RV32ZVBC32-NEXT:    vxor.vv v21, v22, v21
; RV32ZVBC32-NEXT:    vmul.vv v22, v25, v24
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v23
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v20
; RV32ZVBC32-NEXT:    vmul.vv v26, v17, v24
; RV32ZVBC32-NEXT:    vmul.vv v27, v19, v16
; RV32ZVBC32-NEXT:    vxor.vv v21, v21, v22
; RV32ZVBC32-NEXT:    vmul.vv v22, v13, v12
; RV32ZVBC32-NEXT:    vmul.vv v28, v25, v12
; RV32ZVBC32-NEXT:    vxor.vv v26, v27, v26
; RV32ZVBC32-NEXT:    vmul.vv v27, v13, v18
; RV32ZVBC32-NEXT:    vxor.vv v21, v21, v22
; RV32ZVBC32-NEXT:    vxor.vv v22, v26, v28
; RV32ZVBC32-NEXT:    vand.vv v14, v21, v14
; RV32ZVBC32-NEXT:    vxor.vv v21, v22, v27
; RV32ZVBC32-NEXT:    vmul.vv v22, v17, v18
; RV32ZVBC32-NEXT:    vmul.vv v26, v19, v12
; RV32ZVBC32-NEXT:    vand.vv v15, v21, v15
; RV32ZVBC32-NEXT:    vmul.vv v21, v25, v16
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v14
; RV32ZVBC32-NEXT:    vxor.vv v15, v26, v22
; RV32ZVBC32-NEXT:    vmul.vv v12, v17, v12
; RV32ZVBC32-NEXT:    vmul.vv v17, v19, v24
; RV32ZVBC32-NEXT:    vxor.vv v15, v15, v21
; RV32ZVBC32-NEXT:    vmul.vv v19, v13, v24
; RV32ZVBC32-NEXT:    vmul.vv v18, v25, v18
; RV32ZVBC32-NEXT:    vxor.vv v12, v17, v12
; RV32ZVBC32-NEXT:    vmul.vv v13, v13, v16
; RV32ZVBC32-NEXT:    vxor.vv v15, v15, v19
; RV32ZVBC32-NEXT:    vxor.vv v12, v12, v18
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v23
; RV32ZVBC32-NEXT:    vxor.vv v12, v12, v13
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v15
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vor.vv v12, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vx v13, v12, a1
; RV32ZVBC32-NEXT:    vsrl.vx v14, v12, a0
; RV32ZVBC32-NEXT:    vand.vx v13, v13, a2
; RV32ZVBC32-NEXT:    vsrl.vi v15, v12, 24
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 8
; RV32ZVBC32-NEXT:    vand.vx v15, v15, a3
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v9
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v15
; RV32ZVBC32-NEXT:    vand.vv v9, v12, v9
; RV32ZVBC32-NEXT:    vand.vx v15, v12, a3
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 8
; RV32ZVBC32-NEXT:    vsll.vi v15, v15, 24
; RV32ZVBC32-NEXT:    vand.vx v16, v12, a2
; RV32ZVBC32-NEXT:    vsll.vx v12, v12, a0
; RV32ZVBC32-NEXT:    vsll.vx v16, v16, a1
; RV32ZVBC32-NEXT:    vor.vv v9, v15, v9
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v9, v12, v9
; RV32ZVBC32-NEXT:    vor.vv v9, v9, v13
; RV32ZVBC32-NEXT:    vsrl.vi v12, v9, 4
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v10
; RV32ZVBC32-NEXT:    vand.vv v10, v12, v10
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 4
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v11
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v11
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 1
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v8
; RV32ZVBC32-NEXT:    vand.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v9
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    addi sp, sp, 16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i64_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    addi sp, sp, -16
; RV64ZVBC32-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64ZVBC32-NEXT:    li a1, 56
; RV64ZVBC32-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v9, v8, a1
; RV64ZVBC32-NEXT:    li a2, 40
; RV64ZVBC32-NEXT:    vsrl.vx v10, v8, a2
; RV64ZVBC32-NEXT:    lui a3, 16
; RV64ZVBC32-NEXT:    vsrl.vi v11, v8, 24
; RV64ZVBC32-NEXT:    addi a3, a3, -256
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a3
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 8
; RV64ZVBC32-NEXT:    lui a4, 4080
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a4
; RV64ZVBC32-NEXT:    li a5, 255
; RV64ZVBC32-NEXT:    slli a5, a5, 24
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a5
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v11
; RV64ZVBC32-NEXT:    vand.vx v11, v8, a4
; RV64ZVBC32-NEXT:    vand.vx v12, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v11, v11, 24
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV64ZVBC32-NEXT:    vand.vx v13, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vsll.vx v13, v13, a2
; RV64ZVBC32-NEXT:    vor.vv v11, v11, v12
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v13
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v11
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v9
; RV64ZVBC32-NEXT:    lui a6, 61681
; RV64ZVBC32-NEXT:    addi a6, a6, -241
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 4
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    lui a7, 209715
; RV64ZVBC32-NEXT:    addi a7, a7, 819
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 2
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    lui t0, 349525
; RV64ZVBC32-NEXT:    addi t0, t0, 1365
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 1
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    lui t1, 139810
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    addi t1, t1, 546
; RV64ZVBC32-NEXT:    srli t2, a0, 24
; RV64ZVBC32-NEXT:    srli t3, a0, 8
; RV64ZVBC32-NEXT:    and t2, t2, a4
; RV64ZVBC32-NEXT:    and t3, t3, a5
; RV64ZVBC32-NEXT:    or t2, t3, t2
; RV64ZVBC32-NEXT:    srli t3, a0, 40
; RV64ZVBC32-NEXT:    and t3, t3, a3
; RV64ZVBC32-NEXT:    srli t4, a0, 56
; RV64ZVBC32-NEXT:    or t3, t3, t4
; RV64ZVBC32-NEXT:    and t4, a0, a4
; RV64ZVBC32-NEXT:    slli t4, t4, 24
; RV64ZVBC32-NEXT:    srliw t5, a0, 24
; RV64ZVBC32-NEXT:    slli t5, t5, 32
; RV64ZVBC32-NEXT:    and t6, a0, a3
; RV64ZVBC32-NEXT:    slli t6, t6, 40
; RV64ZVBC32-NEXT:    slli a0, a0, 56
; RV64ZVBC32-NEXT:    or t4, t4, t5
; RV64ZVBC32-NEXT:    or a0, a0, t6
; RV64ZVBC32-NEXT:    or t2, t2, t3
; RV64ZVBC32-NEXT:    or a0, a0, t4
; RV64ZVBC32-NEXT:    slli t3, t1, 32
; RV64ZVBC32-NEXT:    or a0, a0, t2
; RV64ZVBC32-NEXT:    srli t2, a0, 4
; RV64ZVBC32-NEXT:    and a0, a0, a6
; RV64ZVBC32-NEXT:    and t2, t2, a6
; RV64ZVBC32-NEXT:    slli t4, a0, 4
; RV64ZVBC32-NEXT:    add a0, t1, t3
; RV64ZVBC32-NEXT:    or t1, t2, t4
; RV64ZVBC32-NEXT:    srli t2, t1, 2
; RV64ZVBC32-NEXT:    and t1, t1, a7
; RV64ZVBC32-NEXT:    and t2, t2, a7
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    vand.vx v9, v8, a0
; RV64ZVBC32-NEXT:    or t1, t2, t1
; RV64ZVBC32-NEXT:    srli t2, t1, 1
; RV64ZVBC32-NEXT:    lui t3, 69905
; RV64ZVBC32-NEXT:    and t2, t2, t0
; RV64ZVBC32-NEXT:    addi t3, t3, 273
; RV64ZVBC32-NEXT:    and t1, t1, t0
; RV64ZVBC32-NEXT:    slli t4, t3, 32
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t3, t3, t4
; RV64ZVBC32-NEXT:    or t2, t2, t1
; RV64ZVBC32-NEXT:    vand.vx v10, v8, t3
; RV64ZVBC32-NEXT:    and t1, t2, t3
; RV64ZVBC32-NEXT:    vmul.vx v11, v9, t1
; RV64ZVBC32-NEXT:    and t4, t2, a0
; RV64ZVBC32-NEXT:    lui t5, 279620
; RV64ZVBC32-NEXT:    vmul.vx v12, v10, t4
; RV64ZVBC32-NEXT:    addi t5, t5, 1092
; RV64ZVBC32-NEXT:    slli t6, t5, 32
; RV64ZVBC32-NEXT:    lui s0, %hi(.LCPI37_0)
; RV64ZVBC32-NEXT:    add t5, t5, t6
; RV64ZVBC32-NEXT:    ld t6, %lo(.LCPI37_0)(s0)
; RV64ZVBC32-NEXT:    vand.vx v13, v8, t5
; RV64ZVBC32-NEXT:    and s0, t2, t6
; RV64ZVBC32-NEXT:    vmul.vx v14, v13, s0
; RV64ZVBC32-NEXT:    vxor.vv v11, v12, v11
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t6
; RV64ZVBC32-NEXT:    vmul.vx v12, v9, s0
; RV64ZVBC32-NEXT:    vmul.vx v15, v10, t1
; RV64ZVBC32-NEXT:    vxor.vv v11, v11, v14
; RV64ZVBC32-NEXT:    and t2, t2, t5
; RV64ZVBC32-NEXT:    vmul.vx v14, v8, t2
; RV64ZVBC32-NEXT:    vmul.vx v16, v13, t2
; RV64ZVBC32-NEXT:    vxor.vv v12, v15, v12
; RV64ZVBC32-NEXT:    vmul.vx v15, v8, t4
; RV64ZVBC32-NEXT:    vxor.vv v11, v11, v14
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v16
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a0
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v15
; RV64ZVBC32-NEXT:    vmul.vx v14, v9, t4
; RV64ZVBC32-NEXT:    vmul.vx v15, v10, t2
; RV64ZVBC32-NEXT:    vand.vx v12, v12, t3
; RV64ZVBC32-NEXT:    vmul.vx v16, v13, t1
; RV64ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV64ZVBC32-NEXT:    vxor.vv v12, v15, v14
; RV64ZVBC32-NEXT:    vmul.vx v9, v9, t2
; RV64ZVBC32-NEXT:    vmul.vx v10, v10, s0
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v16
; RV64ZVBC32-NEXT:    vmul.vx v14, v8, s0
; RV64ZVBC32-NEXT:    vmul.vx v13, v13, t4
; RV64ZVBC32-NEXT:    vxor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, t1
; RV64ZVBC32-NEXT:    vxor.vv v10, v12, v14
; RV64ZVBC32-NEXT:    vxor.vv v9, v9, v13
; RV64ZVBC32-NEXT:    vand.vx v10, v10, t5
; RV64ZVBC32-NEXT:    vxor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vor.vv v9, v11, v10
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t6
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vx v9, v8, a2
; RV64ZVBC32-NEXT:    vsrl.vx v10, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a3
; RV64ZVBC32-NEXT:    vsrl.vi v11, v8, 24
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a4
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a5
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v11
; RV64ZVBC32-NEXT:    vand.vx v11, v8, a5
; RV64ZVBC32-NEXT:    vand.vx v12, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v11, v11, 8
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 24
; RV64ZVBC32-NEXT:    vand.vx v13, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vsll.vx v13, v13, a2
; RV64ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v13
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v11
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v9
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vi v9, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v9, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64ZVBC32-NEXT:    addi sp, sp, 16
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i128 0
  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
  %va.ext = zext <vscale x 1 x i64> %va to <vscale x 1 x i128>
  %vb.ext = zext <vscale x 1 x i64> %vb to <vscale x 1 x i128>
  %clmul = call <vscale x 1 x i128> @llvm.clmul.nxv1i128(<vscale x 1 x i128> %va.ext, <vscale x 1 x i128> %vb.ext)
  %res.ext = lshr <vscale x 1 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 1 x i128> %res.ext to <vscale x 1 x i64>
  ret <vscale x 1 x i64> %res
}

define <vscale x 2 x i64> @clmulh_nxv2i64_vv(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv2i64_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV32V-NEXT:    vsrl.vx v12, v10, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v14, v10, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vand.vx v14, v14, a2
; RV32V-NEXT:    vor.vv v14, v14, v12
; RV32V-NEXT:    vsrl.vi v12, v10, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    sw a3, 8(sp)
; RV32V-NEXT:    sw zero, 12(sp)
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    addi a4, sp, 8
; RV32V-NEXT:    vand.vx v16, v12, a3
; RV32V-NEXT:    vlse64.v v12, (a4), zero
; RV32V-NEXT:    vsrl.vi v18, v10, 8
; RV32V-NEXT:    vand.vv v18, v18, v12
; RV32V-NEXT:    vor.vv v16, v18, v16
; RV32V-NEXT:    vor.vv v14, v16, v14
; RV32V-NEXT:    vsll.vx v16, v10, a0
; RV32V-NEXT:    vand.vx v18, v10, a2
; RV32V-NEXT:    vsll.vx v18, v18, a1
; RV32V-NEXT:    vor.vv v16, v16, v18
; RV32V-NEXT:    vand.vx v18, v10, a3
; RV32V-NEXT:    vsll.vi v18, v18, 24
; RV32V-NEXT:    vand.vv v10, v10, v12
; RV32V-NEXT:    vsll.vi v10, v10, 8
; RV32V-NEXT:    vor.vv v10, v18, v10
; RV32V-NEXT:    vor.vv v10, v16, v10
; RV32V-NEXT:    vor.vv v14, v10, v14
; RV32V-NEXT:    vsrl.vi v16, v14, 4
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v10, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v10
; RV32V-NEXT:    vand.vv v14, v14, v10
; RV32V-NEXT:    vsll.vi v14, v14, 4
; RV32V-NEXT:    vor.vv v16, v16, v14
; RV32V-NEXT:    vsrl.vi v18, v16, 2
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v14, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v18, v18, v14
; RV32V-NEXT:    vand.vv v16, v16, v14
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v18, v18, v16
; RV32V-NEXT:    vsrl.vi v20, v18, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v20, v20, v16
; RV32V-NEXT:    vand.vv v18, v18, v16
; RV32V-NEXT:    vadd.vv v18, v18, v18
; RV32V-NEXT:    vor.vv v22, v20, v18
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v18, v22, v20
; RV32V-NEXT:    vsrl.vx v24, v8, a0
; RV32V-NEXT:    vsrl.vx v26, v8, a1
; RV32V-NEXT:    vand.vx v26, v26, a2
; RV32V-NEXT:    vor.vv v24, v26, v24
; RV32V-NEXT:    vsrl.vi v26, v8, 24
; RV32V-NEXT:    vand.vx v26, v26, a3
; RV32V-NEXT:    vsrl.vi v28, v8, 8
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs2r.v v12, (a4) # vscale x 16-byte Folded Spill
; RV32V-NEXT:    vand.vv v28, v28, v12
; RV32V-NEXT:    vor.vv v26, v28, v26
; RV32V-NEXT:    vor.vv v24, v26, v24
; RV32V-NEXT:    vsll.vx v26, v8, a0
; RV32V-NEXT:    vand.vx v28, v8, a2
; RV32V-NEXT:    vsll.vx v28, v28, a1
; RV32V-NEXT:    vor.vv v26, v26, v28
; RV32V-NEXT:    vand.vx v28, v8, a3
; RV32V-NEXT:    vsll.vi v28, v28, 24
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v28, v8
; RV32V-NEXT:    vor.vv v8, v26, v8
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vsrl.vi v24, v8, 4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs2r.v v10, (a4) # vscale x 16-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v24, v10
; RV32V-NEXT:    vand.vv v8, v8, v10
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 2
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs2r.v v14, (a4) # vscale x 16-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v24, v14
; RV32V-NEXT:    vand.vv v8, v8, v14
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 1
; RV32V-NEXT:    vand.vv v24, v24, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v4, v24, v8
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v2, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v24, v4, v2
; RV32V-NEXT:    vand.vv v14, v22, v2
; RV32V-NEXT:    vand.vv v28, v4, v20
; RV32V-NEXT:    vmul.vv v26, v24, v18
; RV32V-NEXT:    vmul.vv v30, v28, v14
; RV32V-NEXT:    vxor.vv v0, v30, v26
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v26, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v30, v22, v26
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v12, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v8, v22, v12
; RV32V-NEXT:    vand.vv v6, v4, v12
; RV32V-NEXT:    vand.vv v22, v4, v26
; RV32V-NEXT:    vmul.vv v4, v6, v30
; RV32V-NEXT:    vmul.vv v10, v22, v8
; RV32V-NEXT:    vxor.vv v4, v0, v4
; RV32V-NEXT:    vxor.vv v10, v4, v10
; RV32V-NEXT:    vmul.vv v4, v24, v30
; RV32V-NEXT:    vmul.vv v0, v28, v18
; RV32V-NEXT:    vand.vv v10, v10, v2
; RV32V-NEXT:    vxor.vv v4, v0, v4
; RV32V-NEXT:    vmul.vv v2, v6, v8
; RV32V-NEXT:    vmul.vv v0, v22, v14
; RV32V-NEXT:    vxor.vv v4, v4, v2
; RV32V-NEXT:    vxor.vv v4, v4, v0
; RV32V-NEXT:    vand.vv v20, v4, v20
; RV32V-NEXT:    vmul.vv v4, v24, v14
; RV32V-NEXT:    vmul.vv v2, v28, v8
; RV32V-NEXT:    vor.vv v10, v20, v10
; RV32V-NEXT:    vxor.vv v20, v2, v4
; RV32V-NEXT:    vmul.vv v4, v6, v18
; RV32V-NEXT:    vmul.vv v2, v22, v30
; RV32V-NEXT:    vxor.vv v20, v20, v4
; RV32V-NEXT:    vxor.vv v20, v20, v2
; RV32V-NEXT:    vand.vv v12, v20, v12
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    vmul.vv v20, v28, v30
; RV32V-NEXT:    vor.vv v10, v10, v12
; RV32V-NEXT:    vxor.vv v8, v20, v8
; RV32V-NEXT:    vmul.vv v12, v6, v14
; RV32V-NEXT:    vmul.vv v14, v22, v18
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vxor.vv v8, v8, v14
; RV32V-NEXT:    vand.vv v8, v8, v26
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vx v10, v8, a0
; RV32V-NEXT:    vsrl.vx v12, v8, a1
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    vor.vv v10, v12, v10
; RV32V-NEXT:    vsrl.vi v12, v8, 24
; RV32V-NEXT:    vand.vx v12, v12, a3
; RV32V-NEXT:    vsrl.vi v14, v8, 8
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl2r.v v18, (a4) # vscale x 16-byte Folded Reload
; RV32V-NEXT:    vand.vv v14, v14, v18
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vor.vv v10, v12, v10
; RV32V-NEXT:    vand.vv v12, v8, v18
; RV32V-NEXT:    vsll.vi v12, v12, 8
; RV32V-NEXT:    vand.vx v14, v8, a3
; RV32V-NEXT:    vsll.vi v14, v14, 24
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vsll.vx v14, v8, a0
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vx v8, v8, a1
; RV32V-NEXT:    vor.vv v8, v14, v8
; RV32V-NEXT:    vor.vv v8, v8, v12
; RV32V-NEXT:    vor.vv v8, v8, v10
; RV32V-NEXT:    vsrl.vi v10, v8, 4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32V-NEXT:    vand.vv v10, v10, v12
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vi v10, v8, 2
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32V-NEXT:    vand.vv v10, v10, v12
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vi v10, v8, 1
; RV32V-NEXT:    vand.vv v10, v10, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i64_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 56
; RV64V-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV64V-NEXT:    vsrl.vx v12, v10, a0
; RV64V-NEXT:    li a1, 40
; RV64V-NEXT:    vsrl.vx v14, v10, a1
; RV64V-NEXT:    lui a2, 16
; RV64V-NEXT:    addi a2, a2, -256
; RV64V-NEXT:    vand.vx v14, v14, a2
; RV64V-NEXT:    vor.vv v12, v14, v12
; RV64V-NEXT:    vsrl.vi v14, v10, 24
; RV64V-NEXT:    lui a3, 4080
; RV64V-NEXT:    vand.vx v14, v14, a3
; RV64V-NEXT:    vsrl.vi v16, v10, 8
; RV64V-NEXT:    li a4, 255
; RV64V-NEXT:    slli a4, a4, 24
; RV64V-NEXT:    vand.vx v16, v16, a4
; RV64V-NEXT:    vor.vv v14, v16, v14
; RV64V-NEXT:    vor.vv v12, v14, v12
; RV64V-NEXT:    vand.vx v14, v10, a3
; RV64V-NEXT:    vsll.vi v14, v14, 24
; RV64V-NEXT:    vand.vx v16, v10, a4
; RV64V-NEXT:    vsll.vi v16, v16, 8
; RV64V-NEXT:    vor.vv v14, v14, v16
; RV64V-NEXT:    vsll.vx v16, v10, a0
; RV64V-NEXT:    vand.vx v10, v10, a2
; RV64V-NEXT:    vsll.vx v10, v10, a1
; RV64V-NEXT:    vor.vv v10, v16, v10
; RV64V-NEXT:    vor.vv v10, v10, v14
; RV64V-NEXT:    vor.vv v10, v10, v12
; RV64V-NEXT:    vsrl.vi v12, v10, 4
; RV64V-NEXT:    lui a5, 61681
; RV64V-NEXT:    addi a5, a5, -241
; RV64V-NEXT:    slli a6, a5, 32
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    vand.vx v12, v12, a5
; RV64V-NEXT:    vand.vx v10, v10, a5
; RV64V-NEXT:    vsll.vi v10, v10, 4
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vsrl.vi v12, v10, 2
; RV64V-NEXT:    lui a6, 209715
; RV64V-NEXT:    addi a6, a6, 819
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v12, v12, a6
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vsll.vi v10, v10, 2
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vsrl.vi v12, v10, 1
; RV64V-NEXT:    lui a7, 349525
; RV64V-NEXT:    addi a7, a7, 1365
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v12, v12, a7
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vadd.vv v10, v10, v10
; RV64V-NEXT:    vor.vv v12, v12, v10
; RV64V-NEXT:    lui t0, 69905
; RV64V-NEXT:    addi t0, t0, 273
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    vand.vx v10, v12, t0
; RV64V-NEXT:    vsrl.vx v14, v8, a0
; RV64V-NEXT:    vsrl.vx v16, v8, a1
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vor.vv v14, v16, v14
; RV64V-NEXT:    vsrl.vi v16, v8, 24
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vsrl.vi v18, v8, 8
; RV64V-NEXT:    vand.vx v18, v18, a4
; RV64V-NEXT:    vor.vv v16, v18, v16
; RV64V-NEXT:    vor.vv v14, v16, v14
; RV64V-NEXT:    vand.vx v16, v8, a3
; RV64V-NEXT:    vsll.vi v16, v16, 24
; RV64V-NEXT:    vand.vx v18, v8, a4
; RV64V-NEXT:    vsll.vi v18, v18, 8
; RV64V-NEXT:    vor.vv v16, v16, v18
; RV64V-NEXT:    vsll.vx v18, v8, a0
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vor.vv v8, v18, v8
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vor.vv v8, v8, v14
; RV64V-NEXT:    vsrl.vi v14, v8, 4
; RV64V-NEXT:    vand.vx v14, v14, a5
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v14, v8
; RV64V-NEXT:    vsrl.vi v14, v8, 2
; RV64V-NEXT:    vand.vx v14, v14, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v14, v8
; RV64V-NEXT:    vsrl.vi v14, v8, 1
; RV64V-NEXT:    vand.vx v14, v14, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v22, v14, v8
; RV64V-NEXT:    lui t1, 139810
; RV64V-NEXT:    addi t1, t1, 546
; RV64V-NEXT:    slli t2, t1, 32
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    vand.vx v14, v22, t1
; RV64V-NEXT:    vand.vx v8, v12, t1
; RV64V-NEXT:    vand.vx v16, v22, t0
; RV64V-NEXT:    vmul.vv v18, v14, v10
; RV64V-NEXT:    vmul.vv v20, v16, v8
; RV64V-NEXT:    lui t2, %hi(.LCPI38_0)
; RV64V-NEXT:    vxor.vv v24, v20, v18
; RV64V-NEXT:    ld t2, %lo(.LCPI38_0)(t2)
; RV64V-NEXT:    vand.vx v18, v12, t2
; RV64V-NEXT:    lui t3, 279620
; RV64V-NEXT:    addi t3, t3, 1092
; RV64V-NEXT:    slli t4, t3, 32
; RV64V-NEXT:    add t3, t3, t4
; RV64V-NEXT:    vand.vx v20, v22, t3
; RV64V-NEXT:    vand.vx v26, v12, t3
; RV64V-NEXT:    vmul.vv v28, v20, v18
; RV64V-NEXT:    vand.vx v12, v22, t2
; RV64V-NEXT:    vmul.vv v22, v12, v26
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v22, v24, v22
; RV64V-NEXT:    vmul.vv v24, v14, v18
; RV64V-NEXT:    vmul.vv v28, v16, v10
; RV64V-NEXT:    vand.vx v22, v22, t1
; RV64V-NEXT:    vxor.vv v24, v28, v24
; RV64V-NEXT:    vmul.vv v28, v20, v26
; RV64V-NEXT:    vmul.vv v30, v12, v8
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v24, v24, v30
; RV64V-NEXT:    vand.vx v24, v24, t0
; RV64V-NEXT:    vmul.vv v28, v14, v8
; RV64V-NEXT:    vmul.vv v30, v16, v26
; RV64V-NEXT:    vor.vv v22, v24, v22
; RV64V-NEXT:    vxor.vv v24, v30, v28
; RV64V-NEXT:    vmul.vv v28, v20, v10
; RV64V-NEXT:    vmul.vv v30, v12, v18
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v24, v24, v30
; RV64V-NEXT:    vand.vx v24, v24, t3
; RV64V-NEXT:    vmul.vv v14, v14, v26
; RV64V-NEXT:    vmul.vv v16, v16, v18
; RV64V-NEXT:    vor.vv v18, v22, v24
; RV64V-NEXT:    vxor.vv v14, v16, v14
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    vmul.vv v10, v12, v10
; RV64V-NEXT:    vxor.vv v8, v14, v8
; RV64V-NEXT:    vxor.vv v8, v8, v10
; RV64V-NEXT:    vand.vx v8, v8, t2
; RV64V-NEXT:    vor.vv v8, v18, v8
; RV64V-NEXT:    vsrl.vx v10, v8, a0
; RV64V-NEXT:    vsrl.vx v12, v8, a1
; RV64V-NEXT:    vand.vx v12, v12, a2
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vsrl.vi v12, v8, 24
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    vsrl.vi v14, v8, 8
; RV64V-NEXT:    vand.vx v14, v14, a4
; RV64V-NEXT:    vor.vv v12, v14, v12
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vand.vx v12, v8, a4
; RV64V-NEXT:    vsll.vi v12, v12, 8
; RV64V-NEXT:    vand.vx v14, v8, a3
; RV64V-NEXT:    vsll.vi v14, v14, 24
; RV64V-NEXT:    vor.vv v12, v14, v12
; RV64V-NEXT:    vsll.vx v14, v8, a0
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vor.vv v8, v14, v8
; RV64V-NEXT:    vor.vv v8, v8, v12
; RV64V-NEXT:    vor.vv v8, v8, v10
; RV64V-NEXT:    vsrl.vi v10, v8, 4
; RV64V-NEXT:    vand.vx v10, v10, a5
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v10, v8, 2
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v10, v8, 1
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i64_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v10
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i64_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vv v8, v8, v10
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i64_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -16
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    sub sp, sp, a0
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vx v12, v10, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v14, v10, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vand.vx v14, v14, a2
; RV32ZVBC32-NEXT:    vor.vv v14, v14, v12
; RV32ZVBC32-NEXT:    vsrl.vi v12, v10, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    sw a3, 8(sp)
; RV32ZVBC32-NEXT:    sw zero, 12(sp)
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    addi a4, sp, 8
; RV32ZVBC32-NEXT:    vand.vx v16, v12, a3
; RV32ZVBC32-NEXT:    vlse64.v v12, (a4), zero
; RV32ZVBC32-NEXT:    vsrl.vi v18, v10, 8
; RV32ZVBC32-NEXT:    vand.vv v18, v18, v12
; RV32ZVBC32-NEXT:    vor.vv v16, v18, v16
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV32ZVBC32-NEXT:    vsll.vx v16, v10, a0
; RV32ZVBC32-NEXT:    vand.vx v18, v10, a2
; RV32ZVBC32-NEXT:    vsll.vx v18, v18, a1
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v18
; RV32ZVBC32-NEXT:    vand.vx v18, v10, a3
; RV32ZVBC32-NEXT:    vsll.vi v18, v18, 24
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vsll.vi v10, v10, 8
; RV32ZVBC32-NEXT:    vor.vv v10, v18, v10
; RV32ZVBC32-NEXT:    vor.vv v10, v16, v10
; RV32ZVBC32-NEXT:    vor.vv v14, v10, v14
; RV32ZVBC32-NEXT:    vsrl.vi v16, v14, 4
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v10, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v10
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v10
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 4
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v14
; RV32ZVBC32-NEXT:    vsrl.vi v18, v16, 2
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v14, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v18, v18, v14
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v14
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC32-NEXT:    vor.vv v18, v18, v16
; RV32ZVBC32-NEXT:    vsrl.vi v20, v18, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v16, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v16
; RV32ZVBC32-NEXT:    vand.vv v18, v18, v16
; RV32ZVBC32-NEXT:    vadd.vv v18, v18, v18
; RV32ZVBC32-NEXT:    vor.vv v22, v20, v18
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v18, v22, v20
; RV32ZVBC32-NEXT:    vsrl.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v26, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v26, v26, a2
; RV32ZVBC32-NEXT:    vor.vv v24, v26, v24
; RV32ZVBC32-NEXT:    vsrl.vi v26, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v26, v26, a3
; RV32ZVBC32-NEXT:    vsrl.vi v28, v8, 8
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vs2r.v v12, (a4) # vscale x 16-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v28, v28, v12
; RV32ZVBC32-NEXT:    vor.vv v26, v28, v26
; RV32ZVBC32-NEXT:    vor.vv v24, v26, v24
; RV32ZVBC32-NEXT:    vsll.vx v26, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v28, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v28, v28, a1
; RV32ZVBC32-NEXT:    vor.vv v26, v26, v28
; RV32ZVBC32-NEXT:    vand.vx v28, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v28, v28, 24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v8, v28, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v26, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs2r.v v10, (a4) # vscale x 16-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v10
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v10
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 2
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs2r.v v14, (a4) # vscale x 16-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v14
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v14
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 1
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v4, v24, v8
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v2, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v4, v2
; RV32ZVBC32-NEXT:    vand.vv v14, v22, v2
; RV32ZVBC32-NEXT:    vand.vv v28, v4, v20
; RV32ZVBC32-NEXT:    vmul.vv v26, v24, v18
; RV32ZVBC32-NEXT:    vmul.vv v30, v28, v14
; RV32ZVBC32-NEXT:    vxor.vv v0, v30, v26
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v26, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v30, v22, v26
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v12, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v22, v12
; RV32ZVBC32-NEXT:    vand.vv v6, v4, v12
; RV32ZVBC32-NEXT:    vand.vv v22, v4, v26
; RV32ZVBC32-NEXT:    vmul.vv v4, v6, v30
; RV32ZVBC32-NEXT:    vmul.vv v10, v22, v8
; RV32ZVBC32-NEXT:    vxor.vv v4, v0, v4
; RV32ZVBC32-NEXT:    vxor.vv v10, v4, v10
; RV32ZVBC32-NEXT:    vmul.vv v4, v24, v30
; RV32ZVBC32-NEXT:    vmul.vv v0, v28, v18
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v2
; RV32ZVBC32-NEXT:    vxor.vv v4, v0, v4
; RV32ZVBC32-NEXT:    vmul.vv v2, v6, v8
; RV32ZVBC32-NEXT:    vmul.vv v0, v22, v14
; RV32ZVBC32-NEXT:    vxor.vv v4, v4, v2
; RV32ZVBC32-NEXT:    vxor.vv v4, v4, v0
; RV32ZVBC32-NEXT:    vand.vv v20, v4, v20
; RV32ZVBC32-NEXT:    vmul.vv v4, v24, v14
; RV32ZVBC32-NEXT:    vmul.vv v2, v28, v8
; RV32ZVBC32-NEXT:    vor.vv v10, v20, v10
; RV32ZVBC32-NEXT:    vxor.vv v20, v2, v4
; RV32ZVBC32-NEXT:    vmul.vv v4, v6, v18
; RV32ZVBC32-NEXT:    vmul.vv v2, v22, v30
; RV32ZVBC32-NEXT:    vxor.vv v20, v20, v4
; RV32ZVBC32-NEXT:    vxor.vv v20, v20, v2
; RV32ZVBC32-NEXT:    vand.vv v12, v20, v12
; RV32ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vmul.vv v20, v28, v30
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vxor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    vmul.vv v12, v6, v14
; RV32ZVBC32-NEXT:    vmul.vv v14, v22, v18
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v14
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v26
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vx v10, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v12, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV32ZVBC32-NEXT:    vsrl.vi v14, v8, 8
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vl2r.v v18, (a4) # vscale x 16-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v18
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV32ZVBC32-NEXT:    vand.vv v12, v8, v18
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV32ZVBC32-NEXT:    vand.vx v14, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 24
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vsll.vx v14, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV32ZVBC32-NEXT:    vor.vv v8, v14, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v10
; RV32ZVBC32-NEXT:    vsrl.vi v10, v8, 4
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vi v10, v8, 2
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vi v10, v8, 1
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add sp, sp, a0
; RV32ZVBC32-NEXT:    addi sp, sp, 16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i64_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    li a0, 56
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v12, v10, a0
; RV64ZVBC32-NEXT:    li a1, 40
; RV64ZVBC32-NEXT:    vsrl.vx v14, v10, a1
; RV64ZVBC32-NEXT:    lui a2, 16
; RV64ZVBC32-NEXT:    addi a2, a2, -256
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a2
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV64ZVBC32-NEXT:    vsrl.vi v14, v10, 24
; RV64ZVBC32-NEXT:    lui a3, 4080
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a3
; RV64ZVBC32-NEXT:    vsrl.vi v16, v10, 8
; RV64ZVBC32-NEXT:    li a4, 255
; RV64ZVBC32-NEXT:    slli a4, a4, 24
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a4
; RV64ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV64ZVBC32-NEXT:    vand.vx v14, v10, a3
; RV64ZVBC32-NEXT:    vsll.vi v14, v14, 24
; RV64ZVBC32-NEXT:    vand.vx v16, v10, a4
; RV64ZVBC32-NEXT:    vsll.vi v16, v16, 8
; RV64ZVBC32-NEXT:    vor.vv v14, v14, v16
; RV64ZVBC32-NEXT:    vsll.vx v16, v10, a0
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a2
; RV64ZVBC32-NEXT:    vsll.vx v10, v10, a1
; RV64ZVBC32-NEXT:    vor.vv v10, v16, v10
; RV64ZVBC32-NEXT:    vor.vv v10, v10, v14
; RV64ZVBC32-NEXT:    vor.vv v10, v10, v12
; RV64ZVBC32-NEXT:    vsrl.vi v12, v10, 4
; RV64ZVBC32-NEXT:    lui a5, 61681
; RV64ZVBC32-NEXT:    addi a5, a5, -241
; RV64ZVBC32-NEXT:    slli a6, a5, 32
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a5
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a5
; RV64ZVBC32-NEXT:    vsll.vi v10, v10, 4
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vsrl.vi v12, v10, 2
; RV64ZVBC32-NEXT:    lui a6, 209715
; RV64ZVBC32-NEXT:    addi a6, a6, 819
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a6
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vsll.vi v10, v10, 2
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vsrl.vi v12, v10, 1
; RV64ZVBC32-NEXT:    lui a7, 349525
; RV64ZVBC32-NEXT:    addi a7, a7, 1365
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a7
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vadd.vv v10, v10, v10
; RV64ZVBC32-NEXT:    vor.vv v12, v12, v10
; RV64ZVBC32-NEXT:    lui t0, 69905
; RV64ZVBC32-NEXT:    addi t0, t0, 273
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    vand.vx v10, v12, t0
; RV64ZVBC32-NEXT:    vsrl.vx v14, v8, a0
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC32-NEXT:    vsrl.vi v18, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v18, v18, a4
; RV64ZVBC32-NEXT:    vor.vv v16, v18, v16
; RV64ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV64ZVBC32-NEXT:    vand.vx v16, v8, a3
; RV64ZVBC32-NEXT:    vsll.vi v16, v16, 24
; RV64ZVBC32-NEXT:    vand.vx v18, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v18, v18, 8
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v18
; RV64ZVBC32-NEXT:    vsll.vx v18, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vor.vv v8, v18, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v14
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a5
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v14, v8
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v14, v8
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v22, v14, v8
; RV64ZVBC32-NEXT:    lui t1, 139810
; RV64ZVBC32-NEXT:    addi t1, t1, 546
; RV64ZVBC32-NEXT:    slli t2, t1, 32
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    vand.vx v14, v22, t1
; RV64ZVBC32-NEXT:    vand.vx v8, v12, t1
; RV64ZVBC32-NEXT:    vand.vx v16, v22, t0
; RV64ZVBC32-NEXT:    vmul.vv v18, v14, v10
; RV64ZVBC32-NEXT:    vmul.vv v20, v16, v8
; RV64ZVBC32-NEXT:    lui t2, %hi(.LCPI38_0)
; RV64ZVBC32-NEXT:    vxor.vv v24, v20, v18
; RV64ZVBC32-NEXT:    ld t2, %lo(.LCPI38_0)(t2)
; RV64ZVBC32-NEXT:    vand.vx v18, v12, t2
; RV64ZVBC32-NEXT:    lui t3, 279620
; RV64ZVBC32-NEXT:    addi t3, t3, 1092
; RV64ZVBC32-NEXT:    slli t4, t3, 32
; RV64ZVBC32-NEXT:    add t3, t3, t4
; RV64ZVBC32-NEXT:    vand.vx v20, v22, t3
; RV64ZVBC32-NEXT:    vand.vx v26, v12, t3
; RV64ZVBC32-NEXT:    vmul.vv v28, v20, v18
; RV64ZVBC32-NEXT:    vand.vx v12, v22, t2
; RV64ZVBC32-NEXT:    vmul.vv v22, v12, v26
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v28
; RV64ZVBC32-NEXT:    vxor.vv v22, v24, v22
; RV64ZVBC32-NEXT:    vmul.vv v24, v14, v18
; RV64ZVBC32-NEXT:    vmul.vv v28, v16, v10
; RV64ZVBC32-NEXT:    vand.vx v22, v22, t1
; RV64ZVBC32-NEXT:    vxor.vv v24, v28, v24
; RV64ZVBC32-NEXT:    vmul.vv v28, v20, v26
; RV64ZVBC32-NEXT:    vmul.vv v30, v12, v8
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v28
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v30
; RV64ZVBC32-NEXT:    vand.vx v24, v24, t0
; RV64ZVBC32-NEXT:    vmul.vv v28, v14, v8
; RV64ZVBC32-NEXT:    vmul.vv v30, v16, v26
; RV64ZVBC32-NEXT:    vor.vv v22, v24, v22
; RV64ZVBC32-NEXT:    vxor.vv v24, v30, v28
; RV64ZVBC32-NEXT:    vmul.vv v28, v20, v10
; RV64ZVBC32-NEXT:    vmul.vv v30, v12, v18
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v28
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v30
; RV64ZVBC32-NEXT:    vand.vx v24, v24, t3
; RV64ZVBC32-NEXT:    vmul.vv v14, v14, v26
; RV64ZVBC32-NEXT:    vmul.vv v16, v16, v18
; RV64ZVBC32-NEXT:    vor.vv v18, v22, v24
; RV64ZVBC32-NEXT:    vxor.vv v14, v16, v14
; RV64ZVBC32-NEXT:    vmul.vv v8, v20, v8
; RV64ZVBC32-NEXT:    vmul.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vxor.vv v8, v14, v8
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v10
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t2
; RV64ZVBC32-NEXT:    vor.vv v8, v18, v8
; RV64ZVBC32-NEXT:    vsrl.vx v10, v8, a0
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a4
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vand.vx v12, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV64ZVBC32-NEXT:    vand.vx v14, v8, a3
; RV64ZVBC32-NEXT:    vsll.vi v14, v14, 24
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV64ZVBC32-NEXT:    vsll.vx v14, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vor.vv v8, v14, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v10
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a5
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 2 x i64> %va to <vscale x 2 x i128>
  %vb.ext = zext <vscale x 2 x i64> %vb to <vscale x 2 x i128>
  %clmul = call <vscale x 2 x i128> @llvm.clmul.nxv2i128(<vscale x 2 x i128> %va.ext, <vscale x 2 x i128> %vb.ext)
  %res.ext = lshr <vscale x 2 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 2 x i128> %res.ext to <vscale x 2 x i64>
  ret <vscale x 2 x i64> %res
}

define <vscale x 2 x i64> @clmulh_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) nounwind {
; RV32V-LABEL: clmulh_nxv2i64_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -32
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    sub sp, sp, a2
; RV32V-NEXT:    sw a0, 16(sp)
; RV32V-NEXT:    sw a1, 20(sp)
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV32V-NEXT:    vlse64.v v12, (a0), zero
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsrl.vx v10, v12, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v14, v12, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vand.vx v14, v14, a2
; RV32V-NEXT:    vor.vv v14, v14, v10
; RV32V-NEXT:    vsrl.vi v10, v12, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    sw a3, 24(sp)
; RV32V-NEXT:    sw zero, 28(sp)
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    addi a4, sp, 24
; RV32V-NEXT:    vand.vx v16, v10, a3
; RV32V-NEXT:    vlse64.v v10, (a4), zero
; RV32V-NEXT:    vsrl.vi v18, v12, 8
; RV32V-NEXT:    vand.vv v18, v18, v10
; RV32V-NEXT:    vor.vv v16, v18, v16
; RV32V-NEXT:    vor.vv v14, v16, v14
; RV32V-NEXT:    vand.vv v16, v12, v10
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vand.vx v18, v12, a3
; RV32V-NEXT:    vsll.vi v18, v18, 24
; RV32V-NEXT:    vor.vv v16, v18, v16
; RV32V-NEXT:    vsll.vx v18, v12, a0
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    vsll.vx v12, v12, a1
; RV32V-NEXT:    vor.vv v12, v18, v12
; RV32V-NEXT:    vor.vv v12, v12, v16
; RV32V-NEXT:    vor.vv v14, v12, v14
; RV32V-NEXT:    vsrl.vi v16, v14, 4
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v12, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v12
; RV32V-NEXT:    vand.vv v14, v14, v12
; RV32V-NEXT:    vsll.vi v14, v14, 4
; RV32V-NEXT:    vor.vv v16, v16, v14
; RV32V-NEXT:    vsrl.vi v18, v16, 2
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v14, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v18, v18, v14
; RV32V-NEXT:    vand.vv v16, v16, v14
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v18, v18, v16
; RV32V-NEXT:    vsrl.vi v20, v18, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v20, v20, v16
; RV32V-NEXT:    vand.vv v18, v18, v16
; RV32V-NEXT:    vadd.vv v18, v18, v18
; RV32V-NEXT:    vor.vv v22, v20, v18
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v18, v22, v20
; RV32V-NEXT:    vsrl.vx v24, v8, a0
; RV32V-NEXT:    vsrl.vx v26, v8, a1
; RV32V-NEXT:    vand.vx v26, v26, a2
; RV32V-NEXT:    vor.vv v24, v26, v24
; RV32V-NEXT:    vsrl.vi v26, v8, 24
; RV32V-NEXT:    vand.vx v26, v26, a3
; RV32V-NEXT:    vsrl.vi v28, v8, 8
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vs2r.v v10, (a4) # vscale x 16-byte Folded Spill
; RV32V-NEXT:    vand.vv v28, v28, v10
; RV32V-NEXT:    vor.vv v26, v28, v26
; RV32V-NEXT:    vor.vv v24, v26, v24
; RV32V-NEXT:    vsll.vx v26, v8, a0
; RV32V-NEXT:    vand.vx v28, v8, a2
; RV32V-NEXT:    vsll.vx v28, v28, a1
; RV32V-NEXT:    vor.vv v26, v26, v28
; RV32V-NEXT:    vand.vx v28, v8, a3
; RV32V-NEXT:    vsll.vi v28, v28, 24
; RV32V-NEXT:    vand.vv v8, v8, v10
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v28, v8
; RV32V-NEXT:    vor.vv v8, v26, v8
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vsrl.vi v24, v8, 4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs2r.v v12, (a4) # vscale x 16-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v24, v12
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 2
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs2r.v v14, (a4) # vscale x 16-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v24, v14
; RV32V-NEXT:    vand.vv v8, v8, v14
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vsrl.vi v24, v8, 1
; RV32V-NEXT:    vand.vv v24, v24, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v4, v24, v8
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v2, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v24, v4, v2
; RV32V-NEXT:    vand.vv v14, v22, v2
; RV32V-NEXT:    vand.vv v28, v4, v20
; RV32V-NEXT:    vmul.vv v26, v24, v18
; RV32V-NEXT:    vmul.vv v30, v28, v14
; RV32V-NEXT:    vxor.vv v0, v30, v26
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v26, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v30, v22, v26
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32V-NEXT:    vmv.v.x v12, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32V-NEXT:    vand.vv v8, v22, v12
; RV32V-NEXT:    vand.vv v6, v4, v12
; RV32V-NEXT:    vand.vv v22, v4, v26
; RV32V-NEXT:    vmul.vv v4, v6, v30
; RV32V-NEXT:    vmul.vv v10, v22, v8
; RV32V-NEXT:    vxor.vv v4, v0, v4
; RV32V-NEXT:    vxor.vv v10, v4, v10
; RV32V-NEXT:    vmul.vv v4, v24, v30
; RV32V-NEXT:    vmul.vv v0, v28, v18
; RV32V-NEXT:    vand.vv v10, v10, v2
; RV32V-NEXT:    vxor.vv v4, v0, v4
; RV32V-NEXT:    vmul.vv v2, v6, v8
; RV32V-NEXT:    vmul.vv v0, v22, v14
; RV32V-NEXT:    vxor.vv v4, v4, v2
; RV32V-NEXT:    vxor.vv v4, v4, v0
; RV32V-NEXT:    vand.vv v20, v4, v20
; RV32V-NEXT:    vmul.vv v4, v24, v14
; RV32V-NEXT:    vmul.vv v2, v28, v8
; RV32V-NEXT:    vor.vv v10, v20, v10
; RV32V-NEXT:    vxor.vv v20, v2, v4
; RV32V-NEXT:    vmul.vv v4, v6, v18
; RV32V-NEXT:    vmul.vv v2, v22, v30
; RV32V-NEXT:    vxor.vv v20, v20, v4
; RV32V-NEXT:    vxor.vv v20, v20, v2
; RV32V-NEXT:    vand.vv v12, v20, v12
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    vmul.vv v20, v28, v30
; RV32V-NEXT:    vor.vv v10, v10, v12
; RV32V-NEXT:    vxor.vv v8, v20, v8
; RV32V-NEXT:    vmul.vv v12, v6, v14
; RV32V-NEXT:    vmul.vv v14, v22, v18
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vxor.vv v8, v8, v14
; RV32V-NEXT:    vand.vv v8, v8, v26
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vx v10, v8, a0
; RV32V-NEXT:    vsrl.vx v12, v8, a1
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    vor.vv v10, v12, v10
; RV32V-NEXT:    vsrl.vi v12, v8, 24
; RV32V-NEXT:    vand.vx v12, v12, a3
; RV32V-NEXT:    vsrl.vi v14, v8, 8
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vl2r.v v18, (a4) # vscale x 16-byte Folded Reload
; RV32V-NEXT:    vand.vv v14, v14, v18
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vor.vv v10, v12, v10
; RV32V-NEXT:    vand.vv v12, v8, v18
; RV32V-NEXT:    vsll.vi v12, v12, 8
; RV32V-NEXT:    vand.vx v14, v8, a3
; RV32V-NEXT:    vsll.vi v14, v14, 24
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vsll.vx v14, v8, a0
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vx v8, v8, a1
; RV32V-NEXT:    vor.vv v8, v14, v8
; RV32V-NEXT:    vor.vv v8, v8, v12
; RV32V-NEXT:    vor.vv v8, v8, v10
; RV32V-NEXT:    vsrl.vi v10, v8, 4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32V-NEXT:    vand.vv v10, v10, v12
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vi v10, v8, 2
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32V-NEXT:    vand.vv v10, v10, v12
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vi v10, v8, 1
; RV32V-NEXT:    vand.vv v10, v10, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v10, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 32
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv2i64_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64V-NEXT:    li a1, 56
; RV64V-NEXT:    vsetvli a2, zero, e64, m2, ta, ma
; RV64V-NEXT:    vsrl.vx v10, v8, a1
; RV64V-NEXT:    li a2, 40
; RV64V-NEXT:    vsrl.vx v12, v8, a2
; RV64V-NEXT:    lui a3, 16
; RV64V-NEXT:    addi a3, a3, -256
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vsrl.vi v12, v8, 24
; RV64V-NEXT:    lui a4, 4080
; RV64V-NEXT:    vand.vx v12, v12, a4
; RV64V-NEXT:    vsrl.vi v14, v8, 8
; RV64V-NEXT:    li a5, 255
; RV64V-NEXT:    slli a5, a5, 24
; RV64V-NEXT:    vand.vx v14, v14, a5
; RV64V-NEXT:    vor.vv v12, v14, v12
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vand.vx v12, v8, a4
; RV64V-NEXT:    vsll.vi v12, v12, 24
; RV64V-NEXT:    vand.vx v14, v8, a5
; RV64V-NEXT:    vsll.vi v14, v14, 8
; RV64V-NEXT:    vor.vv v12, v12, v14
; RV64V-NEXT:    vsll.vx v14, v8, a1
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v14, v8
; RV64V-NEXT:    vor.vv v8, v8, v12
; RV64V-NEXT:    vor.vv v8, v8, v10
; RV64V-NEXT:    vsrl.vi v10, v8, 4
; RV64V-NEXT:    lui a6, 61681
; RV64V-NEXT:    addi a6, a6, -241
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v10, v8, 2
; RV64V-NEXT:    lui a7, 209715
; RV64V-NEXT:    addi a7, a7, 819
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v10, v8, 1
; RV64V-NEXT:    lui t0, 349525
; RV64V-NEXT:    addi t0, t0, 1365
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    vand.vx v10, v10, t0
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    lui t1, 139810
; RV64V-NEXT:    srli t2, a0, 24
; RV64V-NEXT:    srli t3, a0, 8
; RV64V-NEXT:    and t2, t2, a4
; RV64V-NEXT:    and t3, t3, a5
; RV64V-NEXT:    or t2, t3, t2
; RV64V-NEXT:    srli t3, a0, 40
; RV64V-NEXT:    and t3, t3, a3
; RV64V-NEXT:    srli t4, a0, 56
; RV64V-NEXT:    or t3, t3, t4
; RV64V-NEXT:    and t4, a0, a4
; RV64V-NEXT:    slli t4, t4, 24
; RV64V-NEXT:    srliw t5, a0, 24
; RV64V-NEXT:    slli t5, t5, 32
; RV64V-NEXT:    and t6, a0, a3
; RV64V-NEXT:    slli t6, t6, 40
; RV64V-NEXT:    slli a0, a0, 56
; RV64V-NEXT:    or t4, t4, t5
; RV64V-NEXT:    or a0, a0, t6
; RV64V-NEXT:    or t2, t2, t3
; RV64V-NEXT:    or a0, a0, t4
; RV64V-NEXT:    addi t1, t1, 546
; RV64V-NEXT:    or a0, a0, t2
; RV64V-NEXT:    srli t2, a0, 4
; RV64V-NEXT:    and a0, a0, a6
; RV64V-NEXT:    and t2, t2, a6
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    slli t3, t1, 32
; RV64V-NEXT:    or a0, t2, a0
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    srli t2, a0, 2
; RV64V-NEXT:    vand.vx v10, v8, t1
; RV64V-NEXT:    and t2, t2, a7
; RV64V-NEXT:    and a0, a0, a7
; RV64V-NEXT:    lui t3, 69905
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    addi t3, t3, 273
; RV64V-NEXT:    or a0, t2, a0
; RV64V-NEXT:    slli t2, t3, 32
; RV64V-NEXT:    srli t4, a0, 1
; RV64V-NEXT:    add t2, t3, t2
; RV64V-NEXT:    and a0, a0, t0
; RV64V-NEXT:    vand.vx v12, v8, t2
; RV64V-NEXT:    and t3, t4, t0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    or a0, t3, a0
; RV64V-NEXT:    and t3, a0, t2
; RV64V-NEXT:    vmul.vx v14, v10, t3
; RV64V-NEXT:    and t4, a0, t1
; RV64V-NEXT:    vmul.vx v16, v12, t4
; RV64V-NEXT:    vxor.vv v16, v16, v14
; RV64V-NEXT:    lui t5, 279620
; RV64V-NEXT:    addi t5, t5, 1092
; RV64V-NEXT:    slli t6, t5, 32
; RV64V-NEXT:    lui s0, %hi(.LCPI39_0)
; RV64V-NEXT:    add t5, t5, t6
; RV64V-NEXT:    ld t6, %lo(.LCPI39_0)(s0)
; RV64V-NEXT:    vand.vx v14, v8, t5
; RV64V-NEXT:    and s0, a0, t6
; RV64V-NEXT:    vmul.vx v18, v14, s0
; RV64V-NEXT:    vand.vx v8, v8, t6
; RV64V-NEXT:    and a0, a0, t5
; RV64V-NEXT:    vmul.vx v20, v8, a0
; RV64V-NEXT:    vxor.vv v16, v16, v18
; RV64V-NEXT:    vxor.vv v16, v16, v20
; RV64V-NEXT:    vmul.vx v18, v10, s0
; RV64V-NEXT:    vmul.vx v20, v12, t3
; RV64V-NEXT:    vand.vx v16, v16, t1
; RV64V-NEXT:    vxor.vv v18, v20, v18
; RV64V-NEXT:    vmul.vx v20, v14, a0
; RV64V-NEXT:    vmul.vx v22, v8, t4
; RV64V-NEXT:    vxor.vv v18, v18, v20
; RV64V-NEXT:    vxor.vv v18, v18, v22
; RV64V-NEXT:    vand.vx v18, v18, t2
; RV64V-NEXT:    vmul.vx v20, v10, t4
; RV64V-NEXT:    vmul.vx v22, v12, a0
; RV64V-NEXT:    vor.vv v16, v18, v16
; RV64V-NEXT:    vxor.vv v18, v22, v20
; RV64V-NEXT:    vmul.vx v20, v14, t3
; RV64V-NEXT:    vmul.vx v22, v8, s0
; RV64V-NEXT:    vxor.vv v18, v18, v20
; RV64V-NEXT:    vxor.vv v18, v18, v22
; RV64V-NEXT:    vand.vx v18, v18, t5
; RV64V-NEXT:    vmul.vx v10, v10, a0
; RV64V-NEXT:    vmul.vx v12, v12, s0
; RV64V-NEXT:    vor.vv v16, v16, v18
; RV64V-NEXT:    vxor.vv v10, v12, v10
; RV64V-NEXT:    vmul.vx v12, v14, t4
; RV64V-NEXT:    vmul.vx v8, v8, t3
; RV64V-NEXT:    vxor.vv v10, v10, v12
; RV64V-NEXT:    vxor.vv v8, v10, v8
; RV64V-NEXT:    vand.vx v8, v8, t6
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vx v10, v8, a1
; RV64V-NEXT:    vsrl.vx v12, v8, a2
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vsrl.vi v12, v8, 24
; RV64V-NEXT:    vand.vx v12, v12, a4
; RV64V-NEXT:    vsrl.vi v14, v8, 8
; RV64V-NEXT:    vand.vx v14, v14, a5
; RV64V-NEXT:    vor.vv v12, v14, v12
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vand.vx v12, v8, a5
; RV64V-NEXT:    vsll.vi v12, v12, 8
; RV64V-NEXT:    vand.vx v14, v8, a4
; RV64V-NEXT:    vsll.vi v14, v14, 24
; RV64V-NEXT:    vor.vv v12, v14, v12
; RV64V-NEXT:    vsll.vx v14, v8, a1
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v14, v8
; RV64V-NEXT:    vor.vv v8, v8, v12
; RV64V-NEXT:    vor.vv v8, v8, v10
; RV64V-NEXT:    vsrl.vi v10, v8, 4
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v10, v8, 2
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v10, v8, 1
; RV64V-NEXT:    vand.vx v10, v10, t0
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v10, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv2i64_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    sw a0, 8(sp)
; RV32ZVBC64-NEXT:    sw a1, 12(sp)
; RV32ZVBC64-NEXT:    addi a0, sp, 8
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV32ZVBC64-NEXT:    vlse64.v v10, (a0), zero
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v10
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv2i64_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv2i64_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -32
; RV32ZVBC32-NEXT:    csrr a2, vlenb
; RV32ZVBC32-NEXT:    slli a2, a2, 1
; RV32ZVBC32-NEXT:    mv a3, a2
; RV32ZVBC32-NEXT:    slli a2, a2, 1
; RV32ZVBC32-NEXT:    add a2, a2, a3
; RV32ZVBC32-NEXT:    sub sp, sp, a2
; RV32ZVBC32-NEXT:    sw a0, 16(sp)
; RV32ZVBC32-NEXT:    sw a1, 20(sp)
; RV32ZVBC32-NEXT:    addi a0, sp, 16
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vlse64.v v12, (a0), zero
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsrl.vx v10, v12, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v14, v12, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vand.vx v14, v14, a2
; RV32ZVBC32-NEXT:    vor.vv v14, v14, v10
; RV32ZVBC32-NEXT:    vsrl.vi v10, v12, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    sw a3, 24(sp)
; RV32ZVBC32-NEXT:    sw zero, 28(sp)
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    addi a4, sp, 24
; RV32ZVBC32-NEXT:    vand.vx v16, v10, a3
; RV32ZVBC32-NEXT:    vlse64.v v10, (a4), zero
; RV32ZVBC32-NEXT:    vsrl.vi v18, v12, 8
; RV32ZVBC32-NEXT:    vand.vv v18, v18, v10
; RV32ZVBC32-NEXT:    vor.vv v16, v18, v16
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV32ZVBC32-NEXT:    vand.vv v16, v12, v10
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC32-NEXT:    vand.vx v18, v12, a3
; RV32ZVBC32-NEXT:    vsll.vi v18, v18, 24
; RV32ZVBC32-NEXT:    vor.vv v16, v18, v16
; RV32ZVBC32-NEXT:    vsll.vx v18, v12, a0
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    vsll.vx v12, v12, a1
; RV32ZVBC32-NEXT:    vor.vv v12, v18, v12
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vor.vv v14, v12, v14
; RV32ZVBC32-NEXT:    vsrl.vi v16, v14, 4
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v12, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v12
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v12
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 4
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v14
; RV32ZVBC32-NEXT:    vsrl.vi v18, v16, 2
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v14, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v18, v18, v14
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v14
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC32-NEXT:    vor.vv v18, v18, v16
; RV32ZVBC32-NEXT:    vsrl.vi v20, v18, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v16, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v16
; RV32ZVBC32-NEXT:    vand.vv v18, v18, v16
; RV32ZVBC32-NEXT:    vadd.vv v18, v18, v18
; RV32ZVBC32-NEXT:    vor.vv v22, v20, v18
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v18, v22, v20
; RV32ZVBC32-NEXT:    vsrl.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v26, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v26, v26, a2
; RV32ZVBC32-NEXT:    vor.vv v24, v26, v24
; RV32ZVBC32-NEXT:    vsrl.vi v26, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v26, v26, a3
; RV32ZVBC32-NEXT:    vsrl.vi v28, v8, 8
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vs2r.v v10, (a4) # vscale x 16-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v28, v28, v10
; RV32ZVBC32-NEXT:    vor.vv v26, v28, v26
; RV32ZVBC32-NEXT:    vor.vv v24, v26, v24
; RV32ZVBC32-NEXT:    vsll.vx v26, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v28, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v28, v28, a1
; RV32ZVBC32-NEXT:    vor.vv v26, v26, v28
; RV32ZVBC32-NEXT:    vand.vx v28, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v28, v28, 24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v10
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v8, v28, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v26, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs2r.v v12, (a4) # vscale x 16-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v12
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 2
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs2r.v v14, (a4) # vscale x 16-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v14
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v14
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 1
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v4, v24, v8
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v2, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v4, v2
; RV32ZVBC32-NEXT:    vand.vv v14, v22, v2
; RV32ZVBC32-NEXT:    vand.vv v28, v4, v20
; RV32ZVBC32-NEXT:    vmul.vv v26, v24, v18
; RV32ZVBC32-NEXT:    vmul.vv v30, v28, v14
; RV32ZVBC32-NEXT:    vxor.vv v0, v30, v26
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v26, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v30, v22, v26
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m2, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v12, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m2, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v22, v12
; RV32ZVBC32-NEXT:    vand.vv v6, v4, v12
; RV32ZVBC32-NEXT:    vand.vv v22, v4, v26
; RV32ZVBC32-NEXT:    vmul.vv v4, v6, v30
; RV32ZVBC32-NEXT:    vmul.vv v10, v22, v8
; RV32ZVBC32-NEXT:    vxor.vv v4, v0, v4
; RV32ZVBC32-NEXT:    vxor.vv v10, v4, v10
; RV32ZVBC32-NEXT:    vmul.vv v4, v24, v30
; RV32ZVBC32-NEXT:    vmul.vv v0, v28, v18
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v2
; RV32ZVBC32-NEXT:    vxor.vv v4, v0, v4
; RV32ZVBC32-NEXT:    vmul.vv v2, v6, v8
; RV32ZVBC32-NEXT:    vmul.vv v0, v22, v14
; RV32ZVBC32-NEXT:    vxor.vv v4, v4, v2
; RV32ZVBC32-NEXT:    vxor.vv v4, v4, v0
; RV32ZVBC32-NEXT:    vand.vv v20, v4, v20
; RV32ZVBC32-NEXT:    vmul.vv v4, v24, v14
; RV32ZVBC32-NEXT:    vmul.vv v2, v28, v8
; RV32ZVBC32-NEXT:    vor.vv v10, v20, v10
; RV32ZVBC32-NEXT:    vxor.vv v20, v2, v4
; RV32ZVBC32-NEXT:    vmul.vv v4, v6, v18
; RV32ZVBC32-NEXT:    vmul.vv v2, v22, v30
; RV32ZVBC32-NEXT:    vxor.vv v20, v20, v4
; RV32ZVBC32-NEXT:    vxor.vv v20, v20, v2
; RV32ZVBC32-NEXT:    vand.vv v12, v20, v12
; RV32ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vmul.vv v20, v28, v30
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vxor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    vmul.vv v12, v6, v14
; RV32ZVBC32-NEXT:    vmul.vv v14, v22, v18
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v14
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v26
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vx v10, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v12, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV32ZVBC32-NEXT:    vsrl.vi v14, v8, 8
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vl2r.v v18, (a4) # vscale x 16-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v18
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV32ZVBC32-NEXT:    vand.vv v12, v8, v18
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV32ZVBC32-NEXT:    vand.vx v14, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 24
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vsll.vx v14, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV32ZVBC32-NEXT:    vor.vv v8, v14, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v10
; RV32ZVBC32-NEXT:    vsrl.vi v10, v8, 4
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vi v10, v8, 2
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vi v10, v8, 1
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add sp, sp, a0
; RV32ZVBC32-NEXT:    addi sp, sp, 32
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv2i64_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    addi sp, sp, -16
; RV64ZVBC32-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64ZVBC32-NEXT:    li a1, 56
; RV64ZVBC32-NEXT:    vsetvli a2, zero, e64, m2, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v10, v8, a1
; RV64ZVBC32-NEXT:    li a2, 40
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a2
; RV64ZVBC32-NEXT:    lui a3, 16
; RV64ZVBC32-NEXT:    addi a3, a3, -256
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 24
; RV64ZVBC32-NEXT:    lui a4, 4080
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a4
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 8
; RV64ZVBC32-NEXT:    li a5, 255
; RV64ZVBC32-NEXT:    slli a5, a5, 24
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a5
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vand.vx v12, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 24
; RV64ZVBC32-NEXT:    vand.vx v14, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v14, v14, 8
; RV64ZVBC32-NEXT:    vor.vv v12, v12, v14
; RV64ZVBC32-NEXT:    vsll.vx v14, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vor.vv v8, v14, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v10
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 4
; RV64ZVBC32-NEXT:    lui a6, 61681
; RV64ZVBC32-NEXT:    addi a6, a6, -241
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 2
; RV64ZVBC32-NEXT:    lui a7, 209715
; RV64ZVBC32-NEXT:    addi a7, a7, 819
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 1
; RV64ZVBC32-NEXT:    lui t0, 349525
; RV64ZVBC32-NEXT:    addi t0, t0, 1365
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    vand.vx v10, v10, t0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    lui t1, 139810
; RV64ZVBC32-NEXT:    srli t2, a0, 24
; RV64ZVBC32-NEXT:    srli t3, a0, 8
; RV64ZVBC32-NEXT:    and t2, t2, a4
; RV64ZVBC32-NEXT:    and t3, t3, a5
; RV64ZVBC32-NEXT:    or t2, t3, t2
; RV64ZVBC32-NEXT:    srli t3, a0, 40
; RV64ZVBC32-NEXT:    and t3, t3, a3
; RV64ZVBC32-NEXT:    srli t4, a0, 56
; RV64ZVBC32-NEXT:    or t3, t3, t4
; RV64ZVBC32-NEXT:    and t4, a0, a4
; RV64ZVBC32-NEXT:    slli t4, t4, 24
; RV64ZVBC32-NEXT:    srliw t5, a0, 24
; RV64ZVBC32-NEXT:    slli t5, t5, 32
; RV64ZVBC32-NEXT:    and t6, a0, a3
; RV64ZVBC32-NEXT:    slli t6, t6, 40
; RV64ZVBC32-NEXT:    slli a0, a0, 56
; RV64ZVBC32-NEXT:    or t4, t4, t5
; RV64ZVBC32-NEXT:    or a0, a0, t6
; RV64ZVBC32-NEXT:    or t2, t2, t3
; RV64ZVBC32-NEXT:    or a0, a0, t4
; RV64ZVBC32-NEXT:    addi t1, t1, 546
; RV64ZVBC32-NEXT:    or a0, a0, t2
; RV64ZVBC32-NEXT:    srli t2, a0, 4
; RV64ZVBC32-NEXT:    and a0, a0, a6
; RV64ZVBC32-NEXT:    and t2, t2, a6
; RV64ZVBC32-NEXT:    slli a0, a0, 4
; RV64ZVBC32-NEXT:    slli t3, t1, 32
; RV64ZVBC32-NEXT:    or a0, t2, a0
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    srli t2, a0, 2
; RV64ZVBC32-NEXT:    vand.vx v10, v8, t1
; RV64ZVBC32-NEXT:    and t2, t2, a7
; RV64ZVBC32-NEXT:    and a0, a0, a7
; RV64ZVBC32-NEXT:    lui t3, 69905
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    addi t3, t3, 273
; RV64ZVBC32-NEXT:    or a0, t2, a0
; RV64ZVBC32-NEXT:    slli t2, t3, 32
; RV64ZVBC32-NEXT:    srli t4, a0, 1
; RV64ZVBC32-NEXT:    add t2, t3, t2
; RV64ZVBC32-NEXT:    and a0, a0, t0
; RV64ZVBC32-NEXT:    vand.vx v12, v8, t2
; RV64ZVBC32-NEXT:    and t3, t4, t0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    or a0, t3, a0
; RV64ZVBC32-NEXT:    and t3, a0, t2
; RV64ZVBC32-NEXT:    vmul.vx v14, v10, t3
; RV64ZVBC32-NEXT:    and t4, a0, t1
; RV64ZVBC32-NEXT:    vmul.vx v16, v12, t4
; RV64ZVBC32-NEXT:    vxor.vv v16, v16, v14
; RV64ZVBC32-NEXT:    lui t5, 279620
; RV64ZVBC32-NEXT:    addi t5, t5, 1092
; RV64ZVBC32-NEXT:    slli t6, t5, 32
; RV64ZVBC32-NEXT:    lui s0, %hi(.LCPI39_0)
; RV64ZVBC32-NEXT:    add t5, t5, t6
; RV64ZVBC32-NEXT:    ld t6, %lo(.LCPI39_0)(s0)
; RV64ZVBC32-NEXT:    vand.vx v14, v8, t5
; RV64ZVBC32-NEXT:    and s0, a0, t6
; RV64ZVBC32-NEXT:    vmul.vx v18, v14, s0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t6
; RV64ZVBC32-NEXT:    and a0, a0, t5
; RV64ZVBC32-NEXT:    vmul.vx v20, v8, a0
; RV64ZVBC32-NEXT:    vxor.vv v16, v16, v18
; RV64ZVBC32-NEXT:    vxor.vv v16, v16, v20
; RV64ZVBC32-NEXT:    vmul.vx v18, v10, s0
; RV64ZVBC32-NEXT:    vmul.vx v20, v12, t3
; RV64ZVBC32-NEXT:    vand.vx v16, v16, t1
; RV64ZVBC32-NEXT:    vxor.vv v18, v20, v18
; RV64ZVBC32-NEXT:    vmul.vx v20, v14, a0
; RV64ZVBC32-NEXT:    vmul.vx v22, v8, t4
; RV64ZVBC32-NEXT:    vxor.vv v18, v18, v20
; RV64ZVBC32-NEXT:    vxor.vv v18, v18, v22
; RV64ZVBC32-NEXT:    vand.vx v18, v18, t2
; RV64ZVBC32-NEXT:    vmul.vx v20, v10, t4
; RV64ZVBC32-NEXT:    vmul.vx v22, v12, a0
; RV64ZVBC32-NEXT:    vor.vv v16, v18, v16
; RV64ZVBC32-NEXT:    vxor.vv v18, v22, v20
; RV64ZVBC32-NEXT:    vmul.vx v20, v14, t3
; RV64ZVBC32-NEXT:    vmul.vx v22, v8, s0
; RV64ZVBC32-NEXT:    vxor.vv v18, v18, v20
; RV64ZVBC32-NEXT:    vxor.vv v18, v18, v22
; RV64ZVBC32-NEXT:    vand.vx v18, v18, t5
; RV64ZVBC32-NEXT:    vmul.vx v10, v10, a0
; RV64ZVBC32-NEXT:    vmul.vx v12, v12, s0
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v18
; RV64ZVBC32-NEXT:    vxor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vmul.vx v12, v14, t4
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, t3
; RV64ZVBC32-NEXT:    vxor.vv v10, v10, v12
; RV64ZVBC32-NEXT:    vxor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t6
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vx v10, v8, a1
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a2
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a4
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a5
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vand.vx v12, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV64ZVBC32-NEXT:    vand.vx v14, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v14, v14, 24
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV64ZVBC32-NEXT:    vsll.vx v14, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vor.vv v8, v14, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v10
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v10, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v10, v10, t0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v10, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64ZVBC32-NEXT:    addi sp, sp, 16
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i128 0
  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
  %va.ext = zext <vscale x 2 x i64> %va to <vscale x 2 x i128>
  %vb.ext = zext <vscale x 2 x i64> %vb to <vscale x 2 x i128>
  %clmul = call <vscale x 2 x i128> @llvm.clmul.nxv2i128(<vscale x 2 x i128> %va.ext, <vscale x 2 x i128> %vb.ext)
  %res.ext = lshr <vscale x 2 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 2 x i128> %res.ext to <vscale x 2 x i64>
  ret <vscale x 2 x i64> %res
}

define <vscale x 4 x i64> @clmulh_nxv4i64_vv(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv4i64_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV32V-NEXT:    vsrl.vx v16, v12, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v20, v12, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vand.vx v20, v20, a2
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vsrl.vi v20, v12, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    sw a3, 8(sp)
; RV32V-NEXT:    sw zero, 12(sp)
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    addi a4, sp, 8
; RV32V-NEXT:    vand.vx v20, v20, a3
; RV32V-NEXT:    vlse64.v v28, (a4), zero
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v28, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v24, v12, 8
; RV32V-NEXT:    vand.vv v24, v24, v28
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vsll.vx v20, v12, a0
; RV32V-NEXT:    vand.vx v24, v12, a2
; RV32V-NEXT:    vsll.vx v24, v24, a1
; RV32V-NEXT:    vor.vv v20, v20, v24
; RV32V-NEXT:    vand.vx v24, v12, a3
; RV32V-NEXT:    vsll.vi v24, v24, 24
; RV32V-NEXT:    vand.vv v12, v12, v28
; RV32V-NEXT:    vsll.vi v12, v12, 8
; RV32V-NEXT:    vor.vv v12, v24, v12
; RV32V-NEXT:    vor.vv v12, v20, v12
; RV32V-NEXT:    vor.vv v12, v12, v16
; RV32V-NEXT:    vsrl.vi v16, v12, 4
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    vand.vv v12, v12, v20
; RV32V-NEXT:    vsll.vi v12, v12, 4
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vi v16, v12, 2
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    vand.vv v12, v12, v20
; RV32V-NEXT:    vmv4r.v v4, v20
; RV32V-NEXT:    vsll.vi v12, v12, 2
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vi v16, v12, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    vand.vv v12, v12, v20
; RV32V-NEXT:    vmv4r.v v0, v20
; RV32V-NEXT:    vadd.vv v12, v12, v12
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vx v16, v8, a0
; RV32V-NEXT:    vsrl.vx v20, v8, a1
; RV32V-NEXT:    vand.vx v20, v20, a2
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vsrl.vi v20, v8, 24
; RV32V-NEXT:    vand.vx v20, v20, a3
; RV32V-NEXT:    vsrl.vi v24, v8, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v24, v28
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vand.vx v20, v8, a2
; RV32V-NEXT:    vsll.vx v20, v20, a1
; RV32V-NEXT:    vsll.vx v24, v8, a0
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vand.vx v24, v8, a3
; RV32V-NEXT:    vsll.vi v24, v24, 24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v28
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vor.vv v8, v20, v8
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    vand.vv v8, v8, v20
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v16, v4
; RV32V-NEXT:    vand.vv v8, v8, v4
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vand.vv v8, v8, v0
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v28, v16, v8
; RV32V-NEXT:    vmv4r.v v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v12, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v4, v28, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v12, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v0, v28, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v4, v16
; RV32V-NEXT:    vmul.vv v16, v0, v24
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v12, v24
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v4, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v8, v12, v4
; RV32V-NEXT:    vand.vv v12, v28, v4
; RV32V-NEXT:    vand.vv v28, v28, v24
; RV32V-NEXT:    vmul.vv v24, v12, v16
; RV32V-NEXT:    vmul.vv v4, v28, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    vxor.vv v24, v24, v4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v16
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v4, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v20
; RV32V-NEXT:    vmul.vv v4, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v28, v20
; RV32V-NEXT:    vxor.vv v24, v24, v4
; RV32V-NEXT:    vxor.vv v20, v24, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v20, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v4, v24
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v4, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v4, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v4, v12, v20
; RV32V-NEXT:    vmul.vv v20, v28, v16
; RV32V-NEXT:    vxor.vv v24, v24, v4
; RV32V-NEXT:    vxor.vv v20, v24, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v20, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v12, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v28, v16
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vor.vv v8, v20, v8
; RV32V-NEXT:    vsrl.vx v12, v8, a0
; RV32V-NEXT:    vsrl.vx v16, v8, a1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vi v16, v8, 24
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vsrl.vi v20, v8, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v20, v24
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vand.vv v16, v8, v24
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vand.vx v20, v8, a3
; RV32V-NEXT:    vsll.vi v20, v20, 24
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vsll.vx v20, v8, a0
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vx v8, v8, a1
; RV32V-NEXT:    vor.vv v8, v20, v8
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vor.vv v8, v8, v12
; RV32V-NEXT:    vsrl.vi v12, v8, 4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v12, v12, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v12, v8
; RV32V-NEXT:    vsrl.vi v12, v8, 2
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v12, v12, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v12, v8
; RV32V-NEXT:    vsrl.vi v12, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v12, v12, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v12, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i64_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    li a0, 56
; RV64V-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV64V-NEXT:    vsrl.vx v16, v12, a0
; RV64V-NEXT:    li a1, 40
; RV64V-NEXT:    vsrl.vx v20, v12, a1
; RV64V-NEXT:    lui a2, 16
; RV64V-NEXT:    addi a2, a2, -256
; RV64V-NEXT:    vand.vx v20, v20, a2
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vsrl.vi v20, v12, 24
; RV64V-NEXT:    lui a3, 4080
; RV64V-NEXT:    vand.vx v20, v20, a3
; RV64V-NEXT:    vsrl.vi v24, v12, 8
; RV64V-NEXT:    li a4, 255
; RV64V-NEXT:    slli a4, a4, 24
; RV64V-NEXT:    vand.vx v24, v24, a4
; RV64V-NEXT:    vor.vv v20, v24, v20
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vand.vx v20, v12, a3
; RV64V-NEXT:    vsll.vi v20, v20, 24
; RV64V-NEXT:    vand.vx v24, v12, a4
; RV64V-NEXT:    vsll.vi v24, v24, 8
; RV64V-NEXT:    vor.vv v20, v20, v24
; RV64V-NEXT:    vsll.vx v24, v12, a0
; RV64V-NEXT:    vand.vx v12, v12, a2
; RV64V-NEXT:    vsll.vx v12, v12, a1
; RV64V-NEXT:    vor.vv v12, v24, v12
; RV64V-NEXT:    vor.vv v12, v12, v20
; RV64V-NEXT:    vor.vv v12, v12, v16
; RV64V-NEXT:    vsrl.vi v16, v12, 4
; RV64V-NEXT:    lui a5, 61681
; RV64V-NEXT:    addi a5, a5, -241
; RV64V-NEXT:    slli a6, a5, 32
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    vand.vx v16, v16, a5
; RV64V-NEXT:    vand.vx v12, v12, a5
; RV64V-NEXT:    vsll.vi v12, v12, 4
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vsrl.vi v16, v12, 2
; RV64V-NEXT:    lui a6, 209715
; RV64V-NEXT:    addi a6, a6, 819
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v16, v16, a6
; RV64V-NEXT:    vand.vx v12, v12, a6
; RV64V-NEXT:    vsll.vi v12, v12, 2
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vsrl.vi v16, v12, 1
; RV64V-NEXT:    lui a7, 349525
; RV64V-NEXT:    addi a7, a7, 1365
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    vand.vx v12, v12, a7
; RV64V-NEXT:    vadd.vv v12, v12, v12
; RV64V-NEXT:    vor.vv v28, v16, v12
; RV64V-NEXT:    lui t0, 69905
; RV64V-NEXT:    addi t0, t0, 273
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    vand.vx v4, v28, t0
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs4r.v v4, (t1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vsrl.vx v16, v8, a0
; RV64V-NEXT:    vsrl.vx v20, v8, a1
; RV64V-NEXT:    vand.vx v20, v20, a2
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vsrl.vi v20, v8, 24
; RV64V-NEXT:    vand.vx v20, v20, a3
; RV64V-NEXT:    vsrl.vi v24, v8, 8
; RV64V-NEXT:    vand.vx v24, v24, a4
; RV64V-NEXT:    vor.vv v20, v24, v20
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vand.vx v20, v8, a3
; RV64V-NEXT:    vsll.vi v20, v20, 24
; RV64V-NEXT:    vand.vx v24, v8, a4
; RV64V-NEXT:    vsll.vi v24, v24, 8
; RV64V-NEXT:    vor.vv v20, v20, v24
; RV64V-NEXT:    vsll.vx v24, v8, a0
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vor.vv v8, v8, v20
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a5
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    lui t1, 139810
; RV64V-NEXT:    addi t1, t1, 546
; RV64V-NEXT:    slli t3, t1, 32
; RV64V-NEXT:    add t3, t1, t3
; RV64V-NEXT:    vand.vx v20, v16, t3
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs4r.v v28, (t1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v12, v28, t3
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs4r.v v12, (t1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v24, v16, t0
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs4r.v v24, (t1) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui t1, %hi(.LCPI40_0)
; RV64V-NEXT:    ld t1, %lo(.LCPI40_0)(t1)
; RV64V-NEXT:    vand.vx v28, v28, t1
; RV64V-NEXT:    vmul.vv v8, v20, v4
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 4
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vs4r.v v8, (t2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 2
; RV64V-NEXT:    mv t4, t2
; RV64V-NEXT:    slli t2, t2, 1
; RV64V-NEXT:    add t2, t2, t4
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vs4r.v v20, (t2) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    lui t2, 279620
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v24, v8
; RV64V-NEXT:    addi t2, t2, 1092
; RV64V-NEXT:    slli t4, t2, 32
; RV64V-NEXT:    add t2, t2, t4
; RV64V-NEXT:    vand.vx v4, v16, t2
; RV64V-NEXT:    vmul.vv v8, v4, v28
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v12
; RV64V-NEXT:    vxor.vv v8, v0, v8
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs4r.v v8, (t4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v8, t2
; RV64V-NEXT:    vand.vx v16, v16, t1
; RV64V-NEXT:    vmul.vv v8, v16, v0
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs4r.v v8, (t4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vmul.vv v8, v20, v28
; RV64V-NEXT:    addi t4, sp, 16
; RV64V-NEXT:    vs4r.v v8, (t4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 2
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 2
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v24, v8
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v24, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v12, v12, v24
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs4r.v v12, (t4) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    addi t4, sp, 16
; RV64V-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v8, v12
; RV64V-NEXT:    vmul.vv v12, v4, v0
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v16, v8
; RV64V-NEXT:    vxor.vv v12, v24, v12
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vand.vx v12, v12, t3
; RV64V-NEXT:    csrr t3, vlenb
; RV64V-NEXT:    slli t3, t3, 4
; RV64V-NEXT:    add t3, sp, t3
; RV64V-NEXT:    addi t3, t3, 16
; RV64V-NEXT:    vs4r.v v12, (t3) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t3, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v8, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v20, v8
; RV64V-NEXT:    addi t0, sp, 16
; RV64V-NEXT:    vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v24, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v24, v0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v20, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v12, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v20, v12, v20
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs4r.v v20, (t0) # vscale x 32-byte Folded Spill
; RV64V-NEXT:    addi t0, sp, 16
; RV64V-NEXT:    vl4r.v v12, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vxor.vv v20, v8, v12
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    mv t3, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v8, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v4, v8
; RV64V-NEXT:    vmul.vv v8, v16, v28
; RV64V-NEXT:    vxor.vv v12, v20, v12
; RV64V-NEXT:    vxor.vv v8, v12, v8
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    mv t3, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t3
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v12, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v12, v12, v0
; RV64V-NEXT:    vmul.vv v20, v24, v28
; RV64V-NEXT:    vand.vx v8, v8, t2
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v24, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vxor.vv v12, v20, v12
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t2, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t2
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v20, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v20, v4, v20
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    mv t2, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t2
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl4r.v v24, (t0) # vscale x 32-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v24
; RV64V-NEXT:    vxor.vv v12, v12, v20
; RV64V-NEXT:    vxor.vv v12, v12, v16
; RV64V-NEXT:    vand.vx v12, v12, t1
; RV64V-NEXT:    vor.vv v8, v8, v12
; RV64V-NEXT:    vsrl.vx v12, v8, a0
; RV64V-NEXT:    vsrl.vx v16, v8, a1
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vsrl.vi v16, v8, 24
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vsrl.vi v20, v8, 8
; RV64V-NEXT:    vand.vx v20, v20, a4
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vand.vx v16, v8, a4
; RV64V-NEXT:    vsll.vi v16, v16, 8
; RV64V-NEXT:    vand.vx v20, v8, a3
; RV64V-NEXT:    vsll.vi v20, v20, 24
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vsll.vx v20, v8, a0
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vor.vv v8, v20, v8
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vor.vv v8, v8, v12
; RV64V-NEXT:    vsrl.vi v12, v8, 4
; RV64V-NEXT:    vand.vx v12, v12, a5
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v12, v8, 2
; RV64V-NEXT:    vand.vx v12, v12, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v12, v8, 1
; RV64V-NEXT:    vand.vx v12, v12, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i64_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v12
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i64_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vv v8, v8, v12
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i64_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -16
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    add a1, a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    sub sp, sp, a0
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vx v16, v12, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v20, v12, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a2
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vsrl.vi v20, v12, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    sw a3, 8(sp)
; RV32ZVBC32-NEXT:    sw zero, 12(sp)
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    addi a4, sp, 8
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a3
; RV32ZVBC32-NEXT:    vlse64.v v28, (a4), zero
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v28, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v24, v12, 8
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v28
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vsll.vx v20, v12, a0
; RV32ZVBC32-NEXT:    vand.vx v24, v12, a2
; RV32ZVBC32-NEXT:    vsll.vx v24, v24, a1
; RV32ZVBC32-NEXT:    vor.vv v20, v20, v24
; RV32ZVBC32-NEXT:    vand.vx v24, v12, a3
; RV32ZVBC32-NEXT:    vsll.vi v24, v24, 24
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v28
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV32ZVBC32-NEXT:    vor.vv v12, v24, v12
; RV32ZVBC32-NEXT:    vor.vv v12, v20, v12
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 4
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 4
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 2
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vmv4r.v v4, v20
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 2
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vmv4r.v v0, v20
; RV32ZVBC32-NEXT:    vadd.vv v12, v12, v12
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v20, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a2
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vsrl.vi v20, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a3
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v28
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vand.vx v20, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v20, v20, a1
; RV32ZVBC32-NEXT:    vsll.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vand.vx v24, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v24, v24, 24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v28, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v28
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v24, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v20
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v4
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v4
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v0
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v28, v16, v8
; RV32ZVBC32-NEXT:    vmv4r.v v8, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v12, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v4, v28, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v24, v12, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v0, v28, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vmul.vv v8, v4, v16
; RV32ZVBC32-NEXT:    vmul.vv v16, v0, v24
; RV32ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v24, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v12, v24
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v4, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v12, v4
; RV32ZVBC32-NEXT:    vand.vv v12, v28, v4
; RV32ZVBC32-NEXT:    vand.vv v28, v28, v24
; RV32ZVBC32-NEXT:    vmul.vv v24, v12, v16
; RV32ZVBC32-NEXT:    vmul.vv v4, v28, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v16
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v4, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v20
; RV32ZVBC32-NEXT:    vmul.vv v4, v12, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v20, v28, v20
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v4
; RV32ZVBC32-NEXT:    vxor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v20, v4, v24
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vmul.vv v4, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v4, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v4, v12, v20
; RV32ZVBC32-NEXT:    vmul.vv v20, v28, v16
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v4
; RV32ZVBC32-NEXT:    vxor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vmul.vv v16, v0, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v12, v12, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v28, v16
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    vsrl.vx v12, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC32-NEXT:    vsrl.vi v20, v8, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v24
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vand.vv v16, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC32-NEXT:    vand.vx v20, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v20, v20, 24
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vsll.vx v20, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV32ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 4
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 5
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 2
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a1, a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    add a1, a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add sp, sp, a0
; RV32ZVBC32-NEXT:    addi sp, sp, 16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i64_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    addi sp, sp, -16
; RV64ZVBC32-NEXT:    csrr a0, vlenb
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    mv a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    add a1, a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    add a0, a0, a1
; RV64ZVBC32-NEXT:    sub sp, sp, a0
; RV64ZVBC32-NEXT:    li a0, 56
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v16, v12, a0
; RV64ZVBC32-NEXT:    li a1, 40
; RV64ZVBC32-NEXT:    vsrl.vx v20, v12, a1
; RV64ZVBC32-NEXT:    lui a2, 16
; RV64ZVBC32-NEXT:    addi a2, a2, -256
; RV64ZVBC32-NEXT:    vand.vx v20, v20, a2
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vsrl.vi v20, v12, 24
; RV64ZVBC32-NEXT:    lui a3, 4080
; RV64ZVBC32-NEXT:    vand.vx v20, v20, a3
; RV64ZVBC32-NEXT:    vsrl.vi v24, v12, 8
; RV64ZVBC32-NEXT:    li a4, 255
; RV64ZVBC32-NEXT:    slli a4, a4, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a4
; RV64ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vand.vx v20, v12, a3
; RV64ZVBC32-NEXT:    vsll.vi v20, v20, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v12, a4
; RV64ZVBC32-NEXT:    vsll.vi v24, v24, 8
; RV64ZVBC32-NEXT:    vor.vv v20, v20, v24
; RV64ZVBC32-NEXT:    vsll.vx v24, v12, a0
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV64ZVBC32-NEXT:    vsll.vx v12, v12, a1
; RV64ZVBC32-NEXT:    vor.vv v12, v24, v12
; RV64ZVBC32-NEXT:    vor.vv v12, v12, v20
; RV64ZVBC32-NEXT:    vor.vv v12, v12, v16
; RV64ZVBC32-NEXT:    vsrl.vi v16, v12, 4
; RV64ZVBC32-NEXT:    lui a5, 61681
; RV64ZVBC32-NEXT:    addi a5, a5, -241
; RV64ZVBC32-NEXT:    slli a6, a5, 32
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a5
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a5
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 4
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vsrl.vi v16, v12, 2
; RV64ZVBC32-NEXT:    lui a6, 209715
; RV64ZVBC32-NEXT:    addi a6, a6, 819
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a6
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a6
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 2
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vsrl.vi v16, v12, 1
; RV64ZVBC32-NEXT:    lui a7, 349525
; RV64ZVBC32-NEXT:    addi a7, a7, 1365
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a7
; RV64ZVBC32-NEXT:    vadd.vv v12, v12, v12
; RV64ZVBC32-NEXT:    vor.vv v28, v16, v12
; RV64ZVBC32-NEXT:    lui t0, 69905
; RV64ZVBC32-NEXT:    addi t0, t0, 273
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    vand.vx v4, v28, t0
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs4r.v v4, (t1) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a0
; RV64ZVBC32-NEXT:    vsrl.vx v20, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v20, v20, a2
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vsrl.vi v20, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v20, v20, a3
; RV64ZVBC32-NEXT:    vsrl.vi v24, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a4
; RV64ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vand.vx v20, v8, a3
; RV64ZVBC32-NEXT:    vsll.vi v20, v20, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v24, v24, 8
; RV64ZVBC32-NEXT:    vor.vv v20, v20, v24
; RV64ZVBC32-NEXT:    vsll.vx v24, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v20
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a5
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v8
; RV64ZVBC32-NEXT:    lui t1, 139810
; RV64ZVBC32-NEXT:    addi t1, t1, 546
; RV64ZVBC32-NEXT:    slli t3, t1, 32
; RV64ZVBC32-NEXT:    add t3, t1, t3
; RV64ZVBC32-NEXT:    vand.vx v20, v16, t3
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs4r.v v28, (t1) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v12, v28, t3
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs4r.v v12, (t1) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v24, v16, t0
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs4r.v v24, (t1) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    lui t1, %hi(.LCPI40_0)
; RV64ZVBC32-NEXT:    ld t1, %lo(.LCPI40_0)(t1)
; RV64ZVBC32-NEXT:    vand.vx v28, v28, t1
; RV64ZVBC32-NEXT:    vmul.vv v8, v20, v4
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 4
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vs4r.v v8, (t2) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 2
; RV64ZVBC32-NEXT:    mv t4, t2
; RV64ZVBC32-NEXT:    slli t2, t2, 1
; RV64ZVBC32-NEXT:    add t2, t2, t4
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vs4r.v v20, (t2) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    lui t2, 279620
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v0, v24, v8
; RV64ZVBC32-NEXT:    addi t2, t2, 1092
; RV64ZVBC32-NEXT:    slli t4, t2, 32
; RV64ZVBC32-NEXT:    add t2, t2, t4
; RV64ZVBC32-NEXT:    vand.vx v4, v16, t2
; RV64ZVBC32-NEXT:    vmul.vv v8, v4, v28
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v0, v0, v12
; RV64ZVBC32-NEXT:    vxor.vv v8, v0, v8
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs4r.v v8, (t4) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v0, v8, t2
; RV64ZVBC32-NEXT:    vand.vx v16, v16, t1
; RV64ZVBC32-NEXT:    vmul.vv v8, v16, v0
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs4r.v v8, (t4) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    vmul.vv v8, v20, v28
; RV64ZVBC32-NEXT:    addi t4, sp, 16
; RV64ZVBC32-NEXT:    vs4r.v v8, (t4) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 2
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 2
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v24, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v24
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs4r.v v12, (t4) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    addi t4, sp, 16
; RV64ZVBC32-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v24, v8, v12
; RV64ZVBC32-NEXT:    vmul.vv v12, v4, v0
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v8, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vxor.vv v12, v24, v12
; RV64ZVBC32-NEXT:    vxor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl4r.v v12, (t4) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v12, v12, t3
; RV64ZVBC32-NEXT:    csrr t3, vlenb
; RV64ZVBC32-NEXT:    slli t3, t3, 4
; RV64ZVBC32-NEXT:    add t3, sp, t3
; RV64ZVBC32-NEXT:    addi t3, t3, 16
; RV64ZVBC32-NEXT:    vs4r.v v12, (t3) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    mv t3, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 1
; RV64ZVBC32-NEXT:    add t0, t0, t3
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v8, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v20, v8
; RV64ZVBC32-NEXT:    addi t0, sp, 16
; RV64ZVBC32-NEXT:    vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v24, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v24, v0
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 4
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v20, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v12, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v20, v12, v20
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 4
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vs4r.v v20, (t0) # vscale x 32-byte Folded Spill
; RV64ZVBC32-NEXT:    addi t0, sp, 16
; RV64ZVBC32-NEXT:    vl4r.v v12, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v20, v8, v12
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    mv t3, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    add t0, t0, t3
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v8, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v12, v4, v8
; RV64ZVBC32-NEXT:    vmul.vv v8, v16, v28
; RV64ZVBC32-NEXT:    vxor.vv v12, v20, v12
; RV64ZVBC32-NEXT:    vxor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    mv t3, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 1
; RV64ZVBC32-NEXT:    add t0, t0, t3
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v12, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v12, v12, v0
; RV64ZVBC32-NEXT:    vmul.vv v20, v24, v28
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t2
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 4
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v24, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    vxor.vv v12, v20, v12
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    mv t2, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 1
; RV64ZVBC32-NEXT:    add t0, t0, t2
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v20, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v20, v4, v20
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    mv t2, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    add t0, t0, t2
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl4r.v v24, (t0) # vscale x 32-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v16, v16, v24
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v20
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v16
; RV64ZVBC32-NEXT:    vand.vx v12, v12, t1
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a0
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC32-NEXT:    vsrl.vi v20, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v20, v20, a4
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vand.vx v16, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v16, v16, 8
; RV64ZVBC32-NEXT:    vand.vx v20, v8, a3
; RV64ZVBC32-NEXT:    vsll.vi v20, v20, 24
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vsll.vx v20, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a5
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    csrr a0, vlenb
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    mv a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    add a1, a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    add a0, a0, a1
; RV64ZVBC32-NEXT:    add sp, sp, a0
; RV64ZVBC32-NEXT:    addi sp, sp, 16
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 4 x i64> %va to <vscale x 4 x i128>
  %vb.ext = zext <vscale x 4 x i64> %vb to <vscale x 4 x i128>
  %clmul = call <vscale x 4 x i128> @llvm.clmul.nxv4i128(<vscale x 4 x i128> %va.ext, <vscale x 4 x i128> %vb.ext)
  %res.ext = lshr <vscale x 4 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 4 x i128> %res.ext to <vscale x 4 x i64>
  ret <vscale x 4 x i64> %res
}

define <vscale x 4 x i64> @clmulh_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) nounwind {
; RV32V-LABEL: clmulh_nxv4i64_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -32
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 2
; RV32V-NEXT:    add a3, a3, a2
; RV32V-NEXT:    slli a2, a2, 1
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    sub sp, sp, a2
; RV32V-NEXT:    sw a0, 16(sp)
; RV32V-NEXT:    sw a1, 20(sp)
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV32V-NEXT:    vlse64.v v12, (a0), zero
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsrl.vx v16, v12, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v20, v12, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vand.vx v20, v20, a2
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vsrl.vi v20, v12, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    sw a3, 24(sp)
; RV32V-NEXT:    sw zero, 28(sp)
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    addi a4, sp, 24
; RV32V-NEXT:    vand.vx v20, v20, a3
; RV32V-NEXT:    vlse64.v v28, (a4), zero
; RV32V-NEXT:    vsrl.vi v24, v12, 8
; RV32V-NEXT:    vand.vv v24, v24, v28
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vand.vv v20, v12, v28
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v28, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsll.vi v20, v20, 8
; RV32V-NEXT:    vand.vx v24, v12, a3
; RV32V-NEXT:    vsll.vi v24, v24, 24
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vsll.vx v24, v12, a0
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    vsll.vx v12, v12, a1
; RV32V-NEXT:    vor.vv v12, v24, v12
; RV32V-NEXT:    vor.vv v12, v12, v20
; RV32V-NEXT:    vor.vv v12, v12, v16
; RV32V-NEXT:    vsrl.vi v16, v12, 4
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    vand.vv v12, v12, v20
; RV32V-NEXT:    vsll.vi v12, v12, 4
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vi v16, v12, 2
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    vand.vv v12, v12, v20
; RV32V-NEXT:    vmv4r.v v0, v20
; RV32V-NEXT:    vsll.vi v12, v12, 2
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vi v16, v12, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v4, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v16, v4
; RV32V-NEXT:    vand.vv v12, v12, v4
; RV32V-NEXT:    vadd.vv v12, v12, v12
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vx v16, v8, a0
; RV32V-NEXT:    vsrl.vx v20, v8, a1
; RV32V-NEXT:    vand.vx v20, v20, a2
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vsrl.vi v20, v8, 24
; RV32V-NEXT:    vand.vx v20, v20, a3
; RV32V-NEXT:    vsrl.vi v24, v8, 8
; RV32V-NEXT:    vand.vv v24, v24, v28
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vand.vx v20, v8, a2
; RV32V-NEXT:    vsll.vx v20, v20, a1
; RV32V-NEXT:    vsll.vx v24, v8, a0
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vand.vx v24, v8, a3
; RV32V-NEXT:    vsll.vi v24, v24, 24
; RV32V-NEXT:    vand.vv v8, v8, v28
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    vor.vv v8, v20, v8
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v20
; RV32V-NEXT:    vand.vv v8, v8, v20
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vand.vv v8, v8, v0
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v16, v4
; RV32V-NEXT:    vand.vv v8, v8, v4
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v28, v16, v8
; RV32V-NEXT:    vmv4r.v v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v12, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v20, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v4, v28, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v24, v12, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vand.vv v0, v28, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v8, v4, v16
; RV32V-NEXT:    vmul.vv v16, v0, v24
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v16, v12, v24
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32V-NEXT:    vmv.v.x v4, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32V-NEXT:    vand.vv v8, v12, v4
; RV32V-NEXT:    vand.vv v12, v28, v4
; RV32V-NEXT:    vand.vv v28, v28, v24
; RV32V-NEXT:    vmul.vv v24, v12, v16
; RV32V-NEXT:    vmul.vv v4, v28, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    vxor.vv v24, v24, v4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v16
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v4, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v24, v20
; RV32V-NEXT:    vmul.vv v4, v12, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v28, v20
; RV32V-NEXT:    vxor.vv v24, v24, v4
; RV32V-NEXT:    vxor.vv v20, v24, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v20, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v20, v4, v24
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    vmul.vv v4, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v4, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v4, v12, v20
; RV32V-NEXT:    vmul.vv v20, v28, v16
; RV32V-NEXT:    vxor.vv v24, v24, v4
; RV32V-NEXT:    vxor.vv v20, v24, v20
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v20, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    vmul.vv v16, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vor.vv v20, v24, v20
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v12, v12, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v28, v16
; RV32V-NEXT:    vxor.vv v8, v8, v12
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v12
; RV32V-NEXT:    vor.vv v8, v20, v8
; RV32V-NEXT:    vsrl.vx v12, v8, a0
; RV32V-NEXT:    vsrl.vx v16, v8, a1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vsrl.vi v16, v8, 24
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vsrl.vi v20, v8, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v20, v20, v24
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vor.vv v12, v16, v12
; RV32V-NEXT:    vand.vv v16, v8, v24
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vand.vx v20, v8, a3
; RV32V-NEXT:    vsll.vi v20, v20, 24
; RV32V-NEXT:    vor.vv v16, v20, v16
; RV32V-NEXT:    vsll.vx v20, v8, a0
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vx v8, v8, a1
; RV32V-NEXT:    vor.vv v8, v20, v8
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vor.vv v8, v8, v12
; RV32V-NEXT:    vsrl.vi v12, v8, 4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v12, v12, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v12, v8
; RV32V-NEXT:    vsrl.vi v12, v8, 2
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 5
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v12, v12, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v12, v8
; RV32V-NEXT:    vsrl.vi v12, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32V-NEXT:    vand.vv v12, v12, v16
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v12, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 2
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 32
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv4i64_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64V-NEXT:    li a1, 56
; RV64V-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
; RV64V-NEXT:    vsrl.vx v12, v8, a1
; RV64V-NEXT:    li a2, 40
; RV64V-NEXT:    vsrl.vx v16, v8, a2
; RV64V-NEXT:    lui a3, 16
; RV64V-NEXT:    addi a3, a3, -256
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vsrl.vi v16, v8, 24
; RV64V-NEXT:    lui a4, 4080
; RV64V-NEXT:    vand.vx v16, v16, a4
; RV64V-NEXT:    vsrl.vi v20, v8, 8
; RV64V-NEXT:    li a5, 255
; RV64V-NEXT:    slli a5, a5, 24
; RV64V-NEXT:    vand.vx v20, v20, a5
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vand.vx v16, v8, a4
; RV64V-NEXT:    vsll.vi v16, v16, 24
; RV64V-NEXT:    vand.vx v20, v8, a5
; RV64V-NEXT:    vsll.vi v20, v20, 8
; RV64V-NEXT:    vor.vv v16, v16, v20
; RV64V-NEXT:    vsll.vx v20, v8, a1
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v20, v8
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vor.vv v8, v8, v12
; RV64V-NEXT:    vsrl.vi v12, v8, 4
; RV64V-NEXT:    lui a6, 61681
; RV64V-NEXT:    addi a6, a6, -241
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v12, v12, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v12, v8, 2
; RV64V-NEXT:    lui a7, 209715
; RV64V-NEXT:    addi a7, a7, 819
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v12, v12, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v12, v8, 1
; RV64V-NEXT:    lui t0, 349525
; RV64V-NEXT:    addi t0, t0, 1365
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    vand.vx v12, v12, t0
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v12, v12, v8
; RV64V-NEXT:    lui t1, 139810
; RV64V-NEXT:    addi t1, t1, 546
; RV64V-NEXT:    slli t2, t1, 32
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    vand.vx v8, v12, t1
; RV64V-NEXT:    srli t2, a0, 24
; RV64V-NEXT:    srli t3, a0, 8
; RV64V-NEXT:    and t2, t2, a4
; RV64V-NEXT:    and t3, t3, a5
; RV64V-NEXT:    or t2, t3, t2
; RV64V-NEXT:    srli t3, a0, 40
; RV64V-NEXT:    and t3, t3, a3
; RV64V-NEXT:    srli t4, a0, 56
; RV64V-NEXT:    or t3, t3, t4
; RV64V-NEXT:    and t4, a0, a4
; RV64V-NEXT:    slli t4, t4, 24
; RV64V-NEXT:    srliw t5, a0, 24
; RV64V-NEXT:    slli t5, t5, 32
; RV64V-NEXT:    and t6, a0, a3
; RV64V-NEXT:    slli t6, t6, 40
; RV64V-NEXT:    slli a0, a0, 56
; RV64V-NEXT:    or t4, t4, t5
; RV64V-NEXT:    or a0, a0, t6
; RV64V-NEXT:    or t2, t2, t3
; RV64V-NEXT:    or a0, a0, t4
; RV64V-NEXT:    or a0, a0, t2
; RV64V-NEXT:    srli t2, a0, 4
; RV64V-NEXT:    lui t3, 69905
; RV64V-NEXT:    and t2, t2, a6
; RV64V-NEXT:    addi t3, t3, 273
; RV64V-NEXT:    and a0, a0, a6
; RV64V-NEXT:    slli t4, t3, 32
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    add t3, t3, t4
; RV64V-NEXT:    or a0, t2, a0
; RV64V-NEXT:    vand.vx v16, v12, t3
; RV64V-NEXT:    srli t2, a0, 2
; RV64V-NEXT:    and a0, a0, a7
; RV64V-NEXT:    and t2, t2, a7
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    or a0, t2, a0
; RV64V-NEXT:    srli t2, a0, 1
; RV64V-NEXT:    and a0, a0, t0
; RV64V-NEXT:    and t2, t2, t0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    or a0, t2, a0
; RV64V-NEXT:    and t2, a0, t3
; RV64V-NEXT:    vmul.vx v20, v8, t2
; RV64V-NEXT:    and t4, a0, t1
; RV64V-NEXT:    vmul.vx v24, v16, t4
; RV64V-NEXT:    vxor.vv v24, v24, v20
; RV64V-NEXT:    lui t5, 279620
; RV64V-NEXT:    addi t5, t5, 1092
; RV64V-NEXT:    slli t6, t5, 32
; RV64V-NEXT:    add t5, t5, t6
; RV64V-NEXT:    vand.vx v20, v12, t5
; RV64V-NEXT:    lui t6, %hi(.LCPI41_0)
; RV64V-NEXT:    ld t6, %lo(.LCPI41_0)(t6)
; RV64V-NEXT:    and s0, a0, t6
; RV64V-NEXT:    vmul.vx v28, v20, s0
; RV64V-NEXT:    vand.vx v12, v12, t6
; RV64V-NEXT:    and a0, a0, t5
; RV64V-NEXT:    vmul.vx v4, v12, a0
; RV64V-NEXT:    vxor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v24, v24, v4
; RV64V-NEXT:    vmul.vx v28, v8, s0
; RV64V-NEXT:    vmul.vx v4, v16, t2
; RV64V-NEXT:    vand.vx v24, v24, t1
; RV64V-NEXT:    vxor.vv v28, v4, v28
; RV64V-NEXT:    vmul.vx v4, v20, a0
; RV64V-NEXT:    vmul.vx v0, v12, t4
; RV64V-NEXT:    vxor.vv v28, v28, v4
; RV64V-NEXT:    vxor.vv v28, v28, v0
; RV64V-NEXT:    vand.vx v28, v28, t3
; RV64V-NEXT:    vmul.vx v4, v8, t4
; RV64V-NEXT:    vmul.vx v0, v16, a0
; RV64V-NEXT:    vor.vv v24, v28, v24
; RV64V-NEXT:    vxor.vv v28, v0, v4
; RV64V-NEXT:    vmul.vx v4, v20, t2
; RV64V-NEXT:    vmul.vx v0, v12, s0
; RV64V-NEXT:    vxor.vv v28, v28, v4
; RV64V-NEXT:    vxor.vv v28, v28, v0
; RV64V-NEXT:    vand.vx v28, v28, t5
; RV64V-NEXT:    vmul.vx v8, v8, a0
; RV64V-NEXT:    vmul.vx v16, v16, s0
; RV64V-NEXT:    vor.vv v24, v24, v28
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    vmul.vx v16, v20, t4
; RV64V-NEXT:    vmul.vx v12, v12, t2
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vxor.vv v8, v8, v12
; RV64V-NEXT:    vand.vx v8, v8, t6
; RV64V-NEXT:    vor.vv v8, v24, v8
; RV64V-NEXT:    vsrl.vx v12, v8, a1
; RV64V-NEXT:    vsrl.vx v16, v8, a2
; RV64V-NEXT:    vand.vx v16, v16, a3
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vsrl.vi v16, v8, 24
; RV64V-NEXT:    vand.vx v16, v16, a4
; RV64V-NEXT:    vsrl.vi v20, v8, 8
; RV64V-NEXT:    vand.vx v20, v20, a5
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vor.vv v12, v16, v12
; RV64V-NEXT:    vand.vx v16, v8, a5
; RV64V-NEXT:    vsll.vi v16, v16, 8
; RV64V-NEXT:    vand.vx v20, v8, a4
; RV64V-NEXT:    vsll.vi v20, v20, 24
; RV64V-NEXT:    vor.vv v16, v20, v16
; RV64V-NEXT:    vsll.vx v20, v8, a1
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v20, v8
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vor.vv v8, v8, v12
; RV64V-NEXT:    vsrl.vi v12, v8, 4
; RV64V-NEXT:    vand.vx v12, v12, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v12, v8, 2
; RV64V-NEXT:    vand.vx v12, v12, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v12, v8, 1
; RV64V-NEXT:    vand.vx v12, v12, t0
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v12, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv4i64_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    sw a0, 8(sp)
; RV32ZVBC64-NEXT:    sw a1, 12(sp)
; RV32ZVBC64-NEXT:    addi a0, sp, 8
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV32ZVBC64-NEXT:    vlse64.v v12, (a0), zero
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v12
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv4i64_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv4i64_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -32
; RV32ZVBC32-NEXT:    csrr a2, vlenb
; RV32ZVBC32-NEXT:    slli a2, a2, 2
; RV32ZVBC32-NEXT:    mv a3, a2
; RV32ZVBC32-NEXT:    slli a2, a2, 2
; RV32ZVBC32-NEXT:    add a3, a3, a2
; RV32ZVBC32-NEXT:    slli a2, a2, 1
; RV32ZVBC32-NEXT:    add a2, a2, a3
; RV32ZVBC32-NEXT:    sub sp, sp, a2
; RV32ZVBC32-NEXT:    sw a0, 16(sp)
; RV32ZVBC32-NEXT:    sw a1, 20(sp)
; RV32ZVBC32-NEXT:    addi a0, sp, 16
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vlse64.v v12, (a0), zero
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsrl.vx v16, v12, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v20, v12, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a2
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vsrl.vi v20, v12, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    sw a3, 24(sp)
; RV32ZVBC32-NEXT:    sw zero, 28(sp)
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    addi a4, sp, 24
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a3
; RV32ZVBC32-NEXT:    vlse64.v v28, (a4), zero
; RV32ZVBC32-NEXT:    vsrl.vi v24, v12, 8
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v28
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vand.vv v20, v12, v28
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v28, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsll.vi v20, v20, 8
; RV32ZVBC32-NEXT:    vand.vx v24, v12, a3
; RV32ZVBC32-NEXT:    vsll.vi v24, v24, 24
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vsll.vx v24, v12, a0
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    vsll.vx v12, v12, a1
; RV32ZVBC32-NEXT:    vor.vv v12, v24, v12
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 4
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 4
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 2
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v20
; RV32ZVBC32-NEXT:    vmv4r.v v0, v20
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 2
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v12, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v4, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v4
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v4
; RV32ZVBC32-NEXT:    vadd.vv v12, v12, v12
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v20, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a2
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vsrl.vi v20, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v20, v20, a3
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 8
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v28
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vand.vx v20, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v20, v20, a1
; RV32ZVBC32-NEXT:    vsll.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vand.vx v24, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v24, v24, 24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v28
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v24, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v20
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v0
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v4
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v4
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v28, v16, v8
; RV32ZVBC32-NEXT:    vmv4r.v v8, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v12, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v16, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v20, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v4, v28, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v24, v12, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v0, v28, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v0, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vmul.vv v8, v4, v16
; RV32ZVBC32-NEXT:    vmul.vv v16, v0, v24
; RV32ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v8, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v24, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v12, v24
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m4, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v4, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v4, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m4, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v12, v4
; RV32ZVBC32-NEXT:    vand.vv v12, v28, v4
; RV32ZVBC32-NEXT:    vand.vv v28, v28, v24
; RV32ZVBC32-NEXT:    vmul.vv v24, v12, v16
; RV32ZVBC32-NEXT:    vmul.vv v4, v28, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v16
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vs4r.v v24, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v0, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v4, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v20
; RV32ZVBC32-NEXT:    vmul.vv v4, v12, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v20, v28, v20
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v4
; RV32ZVBC32-NEXT:    vxor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v4, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v20, v4, v24
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    vmul.vv v4, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs4r.v v20, (a4) # vscale x 32-byte Folded Spill
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v4, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v20, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v4, v12, v20
; RV32ZVBC32-NEXT:    vmul.vv v20, v28, v16
; RV32ZVBC32-NEXT:    vxor.vv v24, v24, v4
; RV32ZVBC32-NEXT:    vxor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV32ZVBC32-NEXT:    vmul.vv v16, v0, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v20, v24, v20
; RV32ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v12, v12, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v16, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v28, v16
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v12, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    vsrl.vx v12, v8, a0
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC32-NEXT:    vsrl.vi v20, v8, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl4r.v v24, (a4) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v20, v20, v24
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV32ZVBC32-NEXT:    vand.vv v16, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC32-NEXT:    vand.vx v20, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v20, v20, 24
; RV32ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV32ZVBC32-NEXT:    vsll.vx v20, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV32ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 4
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 2
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 5
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v12, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a1, a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v16
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 2
; RV32ZVBC32-NEXT:    add a1, a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add sp, sp, a0
; RV32ZVBC32-NEXT:    addi sp, sp, 32
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv4i64_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    addi sp, sp, -16
; RV64ZVBC32-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64ZVBC32-NEXT:    li a1, 56
; RV64ZVBC32-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a1
; RV64ZVBC32-NEXT:    li a2, 40
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a2
; RV64ZVBC32-NEXT:    lui a3, 16
; RV64ZVBC32-NEXT:    addi a3, a3, -256
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 24
; RV64ZVBC32-NEXT:    lui a4, 4080
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a4
; RV64ZVBC32-NEXT:    vsrl.vi v20, v8, 8
; RV64ZVBC32-NEXT:    li a5, 255
; RV64ZVBC32-NEXT:    slli a5, a5, 24
; RV64ZVBC32-NEXT:    vand.vx v20, v20, a5
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vand.vx v16, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v16, v16, 24
; RV64ZVBC32-NEXT:    vand.vx v20, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v20, v20, 8
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v20
; RV64ZVBC32-NEXT:    vsll.vx v20, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 4
; RV64ZVBC32-NEXT:    lui a6, 61681
; RV64ZVBC32-NEXT:    addi a6, a6, -241
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 2
; RV64ZVBC32-NEXT:    lui a7, 209715
; RV64ZVBC32-NEXT:    addi a7, a7, 819
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 1
; RV64ZVBC32-NEXT:    lui t0, 349525
; RV64ZVBC32-NEXT:    addi t0, t0, 1365
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    vand.vx v12, v12, t0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v12, v12, v8
; RV64ZVBC32-NEXT:    lui t1, 139810
; RV64ZVBC32-NEXT:    addi t1, t1, 546
; RV64ZVBC32-NEXT:    slli t2, t1, 32
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    vand.vx v8, v12, t1
; RV64ZVBC32-NEXT:    srli t2, a0, 24
; RV64ZVBC32-NEXT:    srli t3, a0, 8
; RV64ZVBC32-NEXT:    and t2, t2, a4
; RV64ZVBC32-NEXT:    and t3, t3, a5
; RV64ZVBC32-NEXT:    or t2, t3, t2
; RV64ZVBC32-NEXT:    srli t3, a0, 40
; RV64ZVBC32-NEXT:    and t3, t3, a3
; RV64ZVBC32-NEXT:    srli t4, a0, 56
; RV64ZVBC32-NEXT:    or t3, t3, t4
; RV64ZVBC32-NEXT:    and t4, a0, a4
; RV64ZVBC32-NEXT:    slli t4, t4, 24
; RV64ZVBC32-NEXT:    srliw t5, a0, 24
; RV64ZVBC32-NEXT:    slli t5, t5, 32
; RV64ZVBC32-NEXT:    and t6, a0, a3
; RV64ZVBC32-NEXT:    slli t6, t6, 40
; RV64ZVBC32-NEXT:    slli a0, a0, 56
; RV64ZVBC32-NEXT:    or t4, t4, t5
; RV64ZVBC32-NEXT:    or a0, a0, t6
; RV64ZVBC32-NEXT:    or t2, t2, t3
; RV64ZVBC32-NEXT:    or a0, a0, t4
; RV64ZVBC32-NEXT:    or a0, a0, t2
; RV64ZVBC32-NEXT:    srli t2, a0, 4
; RV64ZVBC32-NEXT:    lui t3, 69905
; RV64ZVBC32-NEXT:    and t2, t2, a6
; RV64ZVBC32-NEXT:    addi t3, t3, 273
; RV64ZVBC32-NEXT:    and a0, a0, a6
; RV64ZVBC32-NEXT:    slli t4, t3, 32
; RV64ZVBC32-NEXT:    slli a0, a0, 4
; RV64ZVBC32-NEXT:    add t3, t3, t4
; RV64ZVBC32-NEXT:    or a0, t2, a0
; RV64ZVBC32-NEXT:    vand.vx v16, v12, t3
; RV64ZVBC32-NEXT:    srli t2, a0, 2
; RV64ZVBC32-NEXT:    and a0, a0, a7
; RV64ZVBC32-NEXT:    and t2, t2, a7
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    or a0, t2, a0
; RV64ZVBC32-NEXT:    srli t2, a0, 1
; RV64ZVBC32-NEXT:    and a0, a0, t0
; RV64ZVBC32-NEXT:    and t2, t2, t0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    or a0, t2, a0
; RV64ZVBC32-NEXT:    and t2, a0, t3
; RV64ZVBC32-NEXT:    vmul.vx v20, v8, t2
; RV64ZVBC32-NEXT:    and t4, a0, t1
; RV64ZVBC32-NEXT:    vmul.vx v24, v16, t4
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v20
; RV64ZVBC32-NEXT:    lui t5, 279620
; RV64ZVBC32-NEXT:    addi t5, t5, 1092
; RV64ZVBC32-NEXT:    slli t6, t5, 32
; RV64ZVBC32-NEXT:    add t5, t5, t6
; RV64ZVBC32-NEXT:    vand.vx v20, v12, t5
; RV64ZVBC32-NEXT:    lui t6, %hi(.LCPI41_0)
; RV64ZVBC32-NEXT:    ld t6, %lo(.LCPI41_0)(t6)
; RV64ZVBC32-NEXT:    and s0, a0, t6
; RV64ZVBC32-NEXT:    vmul.vx v28, v20, s0
; RV64ZVBC32-NEXT:    vand.vx v12, v12, t6
; RV64ZVBC32-NEXT:    and a0, a0, t5
; RV64ZVBC32-NEXT:    vmul.vx v4, v12, a0
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v28
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v4
; RV64ZVBC32-NEXT:    vmul.vx v28, v8, s0
; RV64ZVBC32-NEXT:    vmul.vx v4, v16, t2
; RV64ZVBC32-NEXT:    vand.vx v24, v24, t1
; RV64ZVBC32-NEXT:    vxor.vv v28, v4, v28
; RV64ZVBC32-NEXT:    vmul.vx v4, v20, a0
; RV64ZVBC32-NEXT:    vmul.vx v0, v12, t4
; RV64ZVBC32-NEXT:    vxor.vv v28, v28, v4
; RV64ZVBC32-NEXT:    vxor.vv v28, v28, v0
; RV64ZVBC32-NEXT:    vand.vx v28, v28, t3
; RV64ZVBC32-NEXT:    vmul.vx v4, v8, t4
; RV64ZVBC32-NEXT:    vmul.vx v0, v16, a0
; RV64ZVBC32-NEXT:    vor.vv v24, v28, v24
; RV64ZVBC32-NEXT:    vxor.vv v28, v0, v4
; RV64ZVBC32-NEXT:    vmul.vx v4, v20, t2
; RV64ZVBC32-NEXT:    vmul.vx v0, v12, s0
; RV64ZVBC32-NEXT:    vxor.vv v28, v28, v4
; RV64ZVBC32-NEXT:    vxor.vv v28, v28, v0
; RV64ZVBC32-NEXT:    vand.vx v28, v28, t5
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, a0
; RV64ZVBC32-NEXT:    vmul.vx v16, v16, s0
; RV64ZVBC32-NEXT:    vor.vv v24, v24, v28
; RV64ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vmul.vx v16, v20, t4
; RV64ZVBC32-NEXT:    vmul.vx v12, v12, t2
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t6
; RV64ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a1
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a2
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a4
; RV64ZVBC32-NEXT:    vsrl.vi v20, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v20, v20, a5
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vor.vv v12, v16, v12
; RV64ZVBC32-NEXT:    vand.vx v16, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v16, v16, 8
; RV64ZVBC32-NEXT:    vand.vx v20, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v20, v20, 24
; RV64ZVBC32-NEXT:    vor.vv v16, v20, v16
; RV64ZVBC32-NEXT:    vsll.vx v20, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vor.vv v8, v20, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v12
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v12, v12, t0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v12, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64ZVBC32-NEXT:    addi sp, sp, 16
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i128 0
  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
  %va.ext = zext <vscale x 4 x i64> %va to <vscale x 4 x i128>
  %vb.ext = zext <vscale x 4 x i64> %vb to <vscale x 4 x i128>
  %clmul = call <vscale x 4 x i128> @llvm.clmul.nxv4i128(<vscale x 4 x i128> %va.ext, <vscale x 4 x i128> %vb.ext)
  %res.ext = lshr <vscale x 4 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 4 x i128> %res.ext to <vscale x 4 x i64>
  ret <vscale x 4 x i64> %res
}

define <vscale x 8 x i64> @clmulh_nxv8i64_vv(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) nounwind {
; RV32V-LABEL: clmulh_nxv8i64_vv:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    sub sp, sp, a0
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV32V-NEXT:    vsrl.vx v24, v16, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v0, v16, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vand.vx v0, v0, a2
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 7
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 16
; RV32V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v0, v16, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    sw a3, 8(sp)
; RV32V-NEXT:    sw zero, 12(sp)
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    addi a4, sp, 8
; RV32V-NEXT:    vand.vx v24, v0, a3
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a6, a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a6, a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 16
; RV32V-NEXT:    vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vlse64.v v24, (a4), zero
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v24, v16, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v16, a2
; RV32V-NEXT:    vsll.vx v0, v0, a1
; RV32V-NEXT:    vsll.vx v24, v16, a0
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v0, v16, a3
; RV32V-NEXT:    vsll.vi v0, v0, 24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vsll.vi v16, v16, 8
; RV32V-NEXT:    vor.vv v16, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsrl.vi v24, v16, 4
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vsll.vi v16, v16, 4
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 2
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vadd.vv v16, v16, v16
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vx v16, v8, a1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vsrl.vx v24, v8, a0
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vand.vx v24, v24, a3
; RV32V-NEXT:    vsrl.vi v0, v8, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v0, v0, v16
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v24, v8, a2
; RV32V-NEXT:    vsll.vx v24, v24, a1
; RV32V-NEXT:    vsll.vx v0, v8, a0
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    vand.vx v0, v8, a3
; RV32V-NEXT:    vsll.vi v0, v0, 24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v0, v8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v24, v16, v8
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v16, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v0, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vv v16, v0, v8
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    addi a4, sp, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vx v16, v8, a1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vsrl.vx v24, v8, a0
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vand.vx v24, v24, a3
; RV32V-NEXT:    vsrl.vi v0, v8, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v0, v0, v16
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 16
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v8, v24
; RV32V-NEXT:    vsll.vi v24, v24, 8
; RV32V-NEXT:    vand.vx v0, v8, a3
; RV32V-NEXT:    vsll.vi v0, v0, 24
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    vsll.vx v0, v8, a0
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vx v8, v8, a1
; RV32V-NEXT:    vor.vv v8, v0, v8
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 16
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i64_vv:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    sub sp, sp, a0
; RV64V-NEXT:    li a0, 56
; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV64V-NEXT:    vsrl.vx v24, v16, a0
; RV64V-NEXT:    li a1, 40
; RV64V-NEXT:    vsrl.vx v0, v16, a1
; RV64V-NEXT:    lui a2, 16
; RV64V-NEXT:    addi a2, a2, -256
; RV64V-NEXT:    vand.vx v0, v0, a2
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    csrr a3, vlenb
; RV64V-NEXT:    slli a3, a3, 4
; RV64V-NEXT:    mv a4, a3
; RV64V-NEXT:    slli a3, a3, 2
; RV64V-NEXT:    add a3, a3, a4
; RV64V-NEXT:    add a3, sp, a3
; RV64V-NEXT:    addi a3, a3, 16
; RV64V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vsrl.vi v0, v16, 24
; RV64V-NEXT:    lui a3, 4080
; RV64V-NEXT:    vand.vx v0, v0, a3
; RV64V-NEXT:    vsrl.vi v24, v16, 8
; RV64V-NEXT:    li a4, 255
; RV64V-NEXT:    slli a4, a4, 24
; RV64V-NEXT:    vand.vx v24, v24, a4
; RV64V-NEXT:    vor.vv v24, v24, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v24, v24, v0
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v0, v16, a3
; RV64V-NEXT:    vsll.vi v0, v0, 24
; RV64V-NEXT:    vand.vx v24, v16, a4
; RV64V-NEXT:    vsll.vi v24, v24, 8
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    vsll.vx v0, v16, a0
; RV64V-NEXT:    vand.vx v16, v16, a2
; RV64V-NEXT:    vsll.vx v16, v16, a1
; RV64V-NEXT:    vor.vv v16, v0, v16
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    csrr a5, vlenb
; RV64V-NEXT:    slli a5, a5, 4
; RV64V-NEXT:    mv a6, a5
; RV64V-NEXT:    slli a5, a5, 2
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    add a5, sp, a5
; RV64V-NEXT:    addi a5, a5, 16
; RV64V-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v24
; RV64V-NEXT:    vsrl.vi v24, v16, 4
; RV64V-NEXT:    lui a5, 61681
; RV64V-NEXT:    addi a5, a5, -241
; RV64V-NEXT:    slli a6, a5, 32
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    vand.vx v24, v24, a5
; RV64V-NEXT:    vand.vx v16, v16, a5
; RV64V-NEXT:    vsll.vi v16, v16, 4
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 2
; RV64V-NEXT:    lui a6, 209715
; RV64V-NEXT:    addi a6, a6, 819
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v24, v24, a6
; RV64V-NEXT:    vand.vx v16, v16, a6
; RV64V-NEXT:    vsll.vi v16, v16, 2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v16, 1
; RV64V-NEXT:    lui a7, 349525
; RV64V-NEXT:    addi a7, a7, 1365
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v24, v24, a7
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    vadd.vv v16, v16, v16
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vsrl.vx v16, v8, a0
; RV64V-NEXT:    vsrl.vx v24, v8, a1
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    vand.vx v24, v24, a3
; RV64V-NEXT:    vsrl.vi v0, v8, 8
; RV64V-NEXT:    vand.vx v0, v0, a4
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vx v24, v8, a3
; RV64V-NEXT:    vsll.vi v24, v24, 24
; RV64V-NEXT:    vand.vx v0, v8, a4
; RV64V-NEXT:    vsll.vi v0, v0, 8
; RV64V-NEXT:    vor.vv v24, v24, v0
; RV64V-NEXT:    vsll.vx v0, v8, a0
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vor.vv v8, v0, v8
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    lui t0, 69905
; RV64V-NEXT:    addi t0, t0, 273
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t1, t0, t1
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t2, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t2
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v24, v0, t1
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t2, t0
; RV64V-NEXT:    slli t0, t0, 2
; RV64V-NEXT:    add t0, t0, t2
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a5
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    lui t0, 139810
; RV64V-NEXT:    addi t0, t0, 546
; RV64V-NEXT:    slli t3, t0, 32
; RV64V-NEXT:    add t3, t0, t3
; RV64V-NEXT:    vand.vx v8, v16, t3
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 6
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v0, t3
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 4
; RV64V-NEXT:    mv t2, t0
; RV64V-NEXT:    slli t0, t0, 1
; RV64V-NEXT:    add t0, t0, t2
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v24, v16, t1
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t2, t0
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, t0, t2
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui t0, %hi(.LCPI42_0)
; RV64V-NEXT:    ld t0, %lo(.LCPI42_0)(t0)
; RV64V-NEXT:    vand.vx v8, v0, t0
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 5
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 4
; RV64V-NEXT:    mv t4, t2
; RV64V-NEXT:    slli t2, t2, 2
; RV64V-NEXT:    add t2, t2, t4
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 6
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v24
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 3
; RV64V-NEXT:    mv t4, t2
; RV64V-NEXT:    slli t2, t2, 1
; RV64V-NEXT:    add t2, t2, t4
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 3
; RV64V-NEXT:    mv t4, t2
; RV64V-NEXT:    slli t2, t2, 3
; RV64V-NEXT:    add t2, t2, t4
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 4
; RV64V-NEXT:    mv t4, t2
; RV64V-NEXT:    slli t2, t2, 1
; RV64V-NEXT:    add t2, t2, t4
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v24, v8
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 4
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 16
; RV64V-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    lui t2, 279620
; RV64V-NEXT:    addi t2, t2, 1092
; RV64V-NEXT:    slli t4, t2, 32
; RV64V-NEXT:    add t2, t2, t4
; RV64V-NEXT:    vand.vx v8, v16, t2
; RV64V-NEXT:    vmv.v.v v0, v16
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t5, t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v24
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 2
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v8, v8, t2
; RV64V-NEXT:    vand.vx v16, v0, t0
; RV64V-NEXT:    vmul.vv v0, v16, v8
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v0, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 2
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v16, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 6
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v24
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 2
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v0
; RV64V-NEXT:    addi t4, sp, 16
; RV64V-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v0
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi t4, sp, 16
; RV64V-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t5, t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v24, v8
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v24
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vs8r.v v16, (t4) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 4
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v16
; RV64V-NEXT:    csrr t4, vlenb
; RV64V-NEXT:    slli t4, t4, 3
; RV64V-NEXT:    mv t5, t4
; RV64V-NEXT:    slli t4, t4, 1
; RV64V-NEXT:    add t4, t4, t5
; RV64V-NEXT:    add t4, sp, t4
; RV64V-NEXT:    addi t4, t4, 16
; RV64V-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v16, t3
; RV64V-NEXT:    csrr t3, vlenb
; RV64V-NEXT:    slli t3, t3, 4
; RV64V-NEXT:    add t3, sp, t3
; RV64V-NEXT:    addi t3, t3, 16
; RV64V-NEXT:    vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v16, v0, t1
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 6
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v24
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v16
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t3, t3, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v0, v16
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 5
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v0, v0, v16
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs8r.v v0, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v24, v0
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v0, v0, v24
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs8r.v v0, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 6
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v8
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t3, t1
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, t1, t3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v8, v8, v16
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v0, v16, t2
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v16, v16, v0
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t2, t2, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v24, v0, v16
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t2, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 16
; RV64V-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vv v16, v16, v0
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    csrr t0, vlenb
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    mv t1, t0
; RV64V-NEXT:    slli t0, t0, 3
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    add t0, sp, t0
; RV64V-NEXT:    addi t0, t0, 16
; RV64V-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vx v16, v8, a0
; RV64V-NEXT:    vsrl.vx v24, v8, a1
; RV64V-NEXT:    vand.vx v24, v24, a2
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    vand.vx v24, v24, a3
; RV64V-NEXT:    vsrl.vi v0, v8, 8
; RV64V-NEXT:    vand.vx v0, v0, a4
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vx v24, v8, a4
; RV64V-NEXT:    vsll.vi v24, v24, 8
; RV64V-NEXT:    vand.vx v0, v8, a3
; RV64V-NEXT:    vsll.vi v0, v0, 24
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    vsll.vx v0, v8, a0
; RV64V-NEXT:    vand.vx v8, v8, a2
; RV64V-NEXT:    vsll.vx v8, v8, a1
; RV64V-NEXT:    vor.vv v8, v0, v8
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a5
; RV64V-NEXT:    vand.vx v8, v8, a5
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a1, a1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i64_vv:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i64_vv:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vv v8, v8, v16
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i64_vv:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -16
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 4
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    sub sp, sp, a0
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vx v24, v16, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v0, v16, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vand.vx v0, v0, a2
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a3, vlenb
; RV32ZVBC32-NEXT:    slli a3, a3, 7
; RV32ZVBC32-NEXT:    add a3, sp, a3
; RV32ZVBC32-NEXT:    addi a3, a3, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v0, v16, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    sw a3, 8(sp)
; RV32ZVBC32-NEXT:    sw zero, 12(sp)
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    addi a4, sp, 8
; RV32ZVBC32-NEXT:    vand.vx v24, v0, a3
; RV32ZVBC32-NEXT:    csrr a5, vlenb
; RV32ZVBC32-NEXT:    slli a5, a5, 3
; RV32ZVBC32-NEXT:    mv a6, a5
; RV32ZVBC32-NEXT:    slli a5, a5, 1
; RV32ZVBC32-NEXT:    add a6, a6, a5
; RV32ZVBC32-NEXT:    slli a5, a5, 1
; RV32ZVBC32-NEXT:    add a6, a6, a5
; RV32ZVBC32-NEXT:    slli a5, a5, 1
; RV32ZVBC32-NEXT:    add a5, a5, a6
; RV32ZVBC32-NEXT:    add a5, sp, a5
; RV32ZVBC32-NEXT:    addi a5, a5, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vlse64.v v24, (a4), zero
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vx v0, v16, a2
; RV32ZVBC32-NEXT:    vsll.vx v0, v0, a1
; RV32ZVBC32-NEXT:    vsll.vx v24, v16, a0
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vx v0, v16, a3
; RV32ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 8
; RV32ZVBC32-NEXT:    vor.vv v16, v0, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 4
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v0, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 4
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 2
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v0, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 6
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v0, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vadd.vv v16, v16, v16
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC32-NEXT:    vsrl.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV32ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v0, v0, v16
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vx v24, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v24, v24, a1
; RV32ZVBC32-NEXT:    vsll.vx v0, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    vand.vx v0, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 6
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v24, v16, v8
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v16, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v0, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v0, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vmul.vv v16, v0, v8
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC32-NEXT:    addi a4, sp, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v16, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v16, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC32-NEXT:    vsrl.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV32ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v0, v0, v16
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v24, v24, 8
; RV32ZVBC32-NEXT:    vand.vx v0, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    vsll.vx v0, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV32ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 6
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a1, a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 16
; RV32ZVBC32-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 4
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add sp, sp, a0
; RV32ZVBC32-NEXT:    addi sp, sp, 16
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i64_vv:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    addi sp, sp, -16
; RV64ZVBC32-NEXT:    csrr a0, vlenb
; RV64ZVBC32-NEXT:    slli a0, a0, 3
; RV64ZVBC32-NEXT:    mv a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    add a1, a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    add a0, a0, a1
; RV64ZVBC32-NEXT:    sub sp, sp, a0
; RV64ZVBC32-NEXT:    li a0, 56
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v24, v16, a0
; RV64ZVBC32-NEXT:    li a1, 40
; RV64ZVBC32-NEXT:    vsrl.vx v0, v16, a1
; RV64ZVBC32-NEXT:    lui a2, 16
; RV64ZVBC32-NEXT:    addi a2, a2, -256
; RV64ZVBC32-NEXT:    vand.vx v0, v0, a2
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    csrr a3, vlenb
; RV64ZVBC32-NEXT:    slli a3, a3, 4
; RV64ZVBC32-NEXT:    mv a4, a3
; RV64ZVBC32-NEXT:    slli a3, a3, 2
; RV64ZVBC32-NEXT:    add a3, a3, a4
; RV64ZVBC32-NEXT:    add a3, sp, a3
; RV64ZVBC32-NEXT:    addi a3, a3, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vsrl.vi v0, v16, 24
; RV64ZVBC32-NEXT:    lui a3, 4080
; RV64ZVBC32-NEXT:    vand.vx v0, v0, a3
; RV64ZVBC32-NEXT:    vsrl.vi v24, v16, 8
; RV64ZVBC32-NEXT:    li a4, 255
; RV64ZVBC32-NEXT:    slli a4, a4, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a4
; RV64ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV64ZVBC32-NEXT:    csrr a5, vlenb
; RV64ZVBC32-NEXT:    slli a5, a5, 4
; RV64ZVBC32-NEXT:    mv a6, a5
; RV64ZVBC32-NEXT:    slli a5, a5, 2
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    add a5, sp, a5
; RV64ZVBC32-NEXT:    addi a5, a5, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV64ZVBC32-NEXT:    csrr a5, vlenb
; RV64ZVBC32-NEXT:    slli a5, a5, 4
; RV64ZVBC32-NEXT:    mv a6, a5
; RV64ZVBC32-NEXT:    slli a5, a5, 2
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    add a5, sp, a5
; RV64ZVBC32-NEXT:    addi a5, a5, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v0, v16, a3
; RV64ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v16, a4
; RV64ZVBC32-NEXT:    vsll.vi v24, v24, 8
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    vsll.vx v0, v16, a0
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV64ZVBC32-NEXT:    vsll.vx v16, v16, a1
; RV64ZVBC32-NEXT:    vor.vv v16, v0, v16
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC32-NEXT:    csrr a5, vlenb
; RV64ZVBC32-NEXT:    slli a5, a5, 4
; RV64ZVBC32-NEXT:    mv a6, a5
; RV64ZVBC32-NEXT:    slli a5, a5, 2
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    add a5, sp, a5
; RV64ZVBC32-NEXT:    addi a5, a5, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV64ZVBC32-NEXT:    vsrl.vi v24, v16, 4
; RV64ZVBC32-NEXT:    lui a5, 61681
; RV64ZVBC32-NEXT:    addi a5, a5, -241
; RV64ZVBC32-NEXT:    slli a6, a5, 32
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a5
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a5
; RV64ZVBC32-NEXT:    vsll.vi v16, v16, 4
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vsrl.vi v24, v16, 2
; RV64ZVBC32-NEXT:    lui a6, 209715
; RV64ZVBC32-NEXT:    addi a6, a6, 819
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a6
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a6
; RV64ZVBC32-NEXT:    vsll.vi v16, v16, 2
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vsrl.vi v24, v16, 1
; RV64ZVBC32-NEXT:    lui a7, 349525
; RV64ZVBC32-NEXT:    addi a7, a7, 1365
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a7
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC32-NEXT:    vadd.vv v16, v16, v16
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    mv t1, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a0
; RV64ZVBC32-NEXT:    vsrl.vx v24, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV64ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v0, v0, a4
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vand.vx v24, v8, a3
; RV64ZVBC32-NEXT:    vsll.vi v24, v24, 24
; RV64ZVBC32-NEXT:    vand.vx v0, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v0, v0, 8
; RV64ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV64ZVBC32-NEXT:    vsll.vx v0, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC32-NEXT:    lui t0, 69905
; RV64ZVBC32-NEXT:    addi t0, t0, 273
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t1, t0, t1
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    mv t2, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    add t0, t0, t2
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v24, v0, t1
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 4
; RV64ZVBC32-NEXT:    mv t2, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 2
; RV64ZVBC32-NEXT:    add t0, t0, t2
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a5
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v8
; RV64ZVBC32-NEXT:    lui t0, 139810
; RV64ZVBC32-NEXT:    addi t0, t0, 546
; RV64ZVBC32-NEXT:    slli t3, t0, 32
; RV64ZVBC32-NEXT:    add t3, t0, t3
; RV64ZVBC32-NEXT:    vand.vx v8, v16, t3
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 6
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v8, v0, t3
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 4
; RV64ZVBC32-NEXT:    mv t2, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 1
; RV64ZVBC32-NEXT:    add t0, t0, t2
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v24, v16, t1
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    mv t2, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    add t0, t0, t2
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (t0) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    lui t0, %hi(.LCPI42_0)
; RV64ZVBC32-NEXT:    ld t0, %lo(.LCPI42_0)(t0)
; RV64ZVBC32-NEXT:    vand.vx v8, v0, t0
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 5
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 4
; RV64ZVBC32-NEXT:    mv t4, t2
; RV64ZVBC32-NEXT:    slli t2, t2, 2
; RV64ZVBC32-NEXT:    add t2, t2, t4
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 6
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v8, v24
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 3
; RV64ZVBC32-NEXT:    mv t4, t2
; RV64ZVBC32-NEXT:    slli t2, t2, 1
; RV64ZVBC32-NEXT:    add t2, t2, t4
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 3
; RV64ZVBC32-NEXT:    mv t4, t2
; RV64ZVBC32-NEXT:    slli t2, t2, 3
; RV64ZVBC32-NEXT:    add t2, t2, t4
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 4
; RV64ZVBC32-NEXT:    mv t4, t2
; RV64ZVBC32-NEXT:    slli t2, t2, 1
; RV64ZVBC32-NEXT:    add t2, t2, t4
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vl8r.v v8, (t2) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 4
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    lui t2, 279620
; RV64ZVBC32-NEXT:    addi t2, t2, 1092
; RV64ZVBC32-NEXT:    slli t4, t2, 32
; RV64ZVBC32-NEXT:    add t2, t2, t4
; RV64ZVBC32-NEXT:    vand.vx v8, v16, t2
; RV64ZVBC32-NEXT:    vmv.v.v v0, v16
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t5, t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v8, v24
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v8, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 2
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v8, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t2
; RV64ZVBC32-NEXT:    vand.vx v16, v0, t0
; RV64ZVBC32-NEXT:    vmul.vv v0, v16, v8
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v0, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 2
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 6
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v24, v0, v24
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 2
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v24, v24, v0
; RV64ZVBC32-NEXT:    addi t4, sp, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v0
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    addi t4, sp, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t5, t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v24, v24, v8
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v24, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v16, v16, v24
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t4) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 4
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v0, v0, v16
; RV64ZVBC32-NEXT:    csrr t4, vlenb
; RV64ZVBC32-NEXT:    slli t4, t4, 3
; RV64ZVBC32-NEXT:    mv t5, t4
; RV64ZVBC32-NEXT:    slli t4, t4, 1
; RV64ZVBC32-NEXT:    add t4, t4, t5
; RV64ZVBC32-NEXT:    add t4, sp, t4
; RV64ZVBC32-NEXT:    addi t4, t4, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t4) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v16, v16, t3
; RV64ZVBC32-NEXT:    csrr t3, vlenb
; RV64ZVBC32-NEXT:    slli t3, t3, 4
; RV64ZVBC32-NEXT:    add t3, sp, t3
; RV64ZVBC32-NEXT:    addi t3, t3, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v16, v0, t1
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 6
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v16, v0, v24
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v16
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t3, t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v16, v0, v16
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 5
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v0, v0, v16
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs8r.v v0, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v0, v24, v0
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v0, v0, v24
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs8r.v v0, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 6
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v24, v0, v8
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t3, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, t1, t3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v8, v8, v16
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v0, v16, t2
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v0
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vs8r.v v16, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t2, t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v24, v0, v16
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v0, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t2, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vv v16, v16, v0
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    csrr t0, vlenb
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    mv t1, t0
; RV64ZVBC32-NEXT:    slli t0, t0, 3
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    add t0, sp, t0
; RV64ZVBC32-NEXT:    addi t0, t0, 16
; RV64ZVBC32-NEXT:    vl8r.v v16, (t0) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a0
; RV64ZVBC32-NEXT:    vsrl.vx v24, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a2
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV64ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v0, v0, a4
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vand.vx v24, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v24, v24, 8
; RV64ZVBC32-NEXT:    vand.vx v0, v8, a3
; RV64ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    vsll.vx v0, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV64ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a5
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    csrr a0, vlenb
; RV64ZVBC32-NEXT:    slli a0, a0, 3
; RV64ZVBC32-NEXT:    mv a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    add a1, a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    add a0, a0, a1
; RV64ZVBC32-NEXT:    add sp, sp, a0
; RV64ZVBC32-NEXT:    addi sp, sp, 16
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 8 x i64> %va to <vscale x 8 x i128>
  %vb.ext = zext <vscale x 8 x i64> %vb to <vscale x 8 x i128>
  %clmul = call <vscale x 8 x i128> @llvm.clmul.nxv8i128(<vscale x 8 x i128> %va.ext, <vscale x 8 x i128> %vb.ext)
  %res.ext = lshr <vscale x 8 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 8 x i128> %res.ext to <vscale x 8 x i64>
  ret <vscale x 8 x i64> %res
}

define <vscale x 8 x i64> @clmulh_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) nounwind {
; RV32V-LABEL: clmulh_nxv8i64_vx:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -32
; RV32V-NEXT:    csrr a2, vlenb
; RV32V-NEXT:    slli a2, a2, 4
; RV32V-NEXT:    mv a3, a2
; RV32V-NEXT:    slli a2, a2, 3
; RV32V-NEXT:    add a2, a2, a3
; RV32V-NEXT:    sub sp, sp, a2
; RV32V-NEXT:    sw a0, 16(sp)
; RV32V-NEXT:    sw a1, 20(sp)
; RV32V-NEXT:    addi a0, sp, 16
; RV32V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV32V-NEXT:    vlse64.v v16, (a0), zero
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsrl.vx v24, v16, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v0, v16, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vand.vx v0, v0, a2
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a3, vlenb
; RV32V-NEXT:    slli a3, a3, 7
; RV32V-NEXT:    add a3, sp, a3
; RV32V-NEXT:    addi a3, a3, 32
; RV32V-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v0, v16, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    sw a3, 24(sp)
; RV32V-NEXT:    sw zero, 28(sp)
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    addi a4, sp, 24
; RV32V-NEXT:    vand.vx v24, v0, a3
; RV32V-NEXT:    csrr a5, vlenb
; RV32V-NEXT:    slli a5, a5, 3
; RV32V-NEXT:    mv a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a6, a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a6, a6, a5
; RV32V-NEXT:    slli a5, a5, 1
; RV32V-NEXT:    add a5, a5, a6
; RV32V-NEXT:    add a5, sp, a5
; RV32V-NEXT:    addi a5, a5, 32
; RV32V-NEXT:    vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vlse64.v v24, (a4), zero
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v24, v16, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v0, v16, v24
; RV32V-NEXT:    vsll.vi v0, v0, 8
; RV32V-NEXT:    vand.vx v24, v16, a3
; RV32V-NEXT:    vsll.vi v24, v24, 24
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    vsll.vx v0, v16, a0
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vsll.vx v16, v16, a1
; RV32V-NEXT:    vor.vv v16, v0, v16
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    vsrl.vi v24, v16, 4
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vsll.vi v16, v16, 4
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 2
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vsll.vi v16, v16, 2
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    vsrl.vi v24, v16, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v0, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v24, v24, v0
; RV32V-NEXT:    vand.vv v16, v16, v0
; RV32V-NEXT:    vadd.vv v16, v16, v16
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vx v16, v8, a1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vsrl.vx v24, v8, a0
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vand.vx v24, v24, a3
; RV32V-NEXT:    vsrl.vi v0, v8, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v0, v0, v16
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vx v24, v8, a2
; RV32V-NEXT:    vsll.vx v24, v24, a1
; RV32V-NEXT:    vsll.vx v0, v8, a0
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    vand.vx v0, v8, a3
; RV32V-NEXT:    vsll.vi v0, v0, 24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    vsll.vi v8, v8, 8
; RV32V-NEXT:    vor.vv v8, v0, v8
; RV32V-NEXT:    vor.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 6
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v24, v16, v8
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v16, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v8, a4
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32V-NEXT:    vand.vv v8, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vand.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v0, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vmul.vv v16, v0, v8
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    addi a4, sp, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v16, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v0, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v0, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v8, v24, v8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v24, v24, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v16, v16, v0
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 2
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 5
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vmul.vv v24, v24, v0
; RV32V-NEXT:    vxor.vv v8, v8, v16
; RV32V-NEXT:    vxor.vv v8, v8, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v8, v8, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a5, a5, a4
; RV32V-NEXT:    slli a4, a4, 1
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vx v16, v8, a1
; RV32V-NEXT:    vand.vx v16, v16, a2
; RV32V-NEXT:    vsrl.vx v24, v8, a0
; RV32V-NEXT:    vor.vv v16, v16, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32V-NEXT:    vsrl.vi v24, v8, 24
; RV32V-NEXT:    vand.vx v24, v24, a3
; RV32V-NEXT:    vsrl.vi v0, v8, 8
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v0, v0, v16
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 7
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vor.vv v16, v24, v16
; RV32V-NEXT:    csrr a4, vlenb
; RV32V-NEXT:    slli a4, a4, 3
; RV32V-NEXT:    mv a5, a4
; RV32V-NEXT:    slli a4, a4, 4
; RV32V-NEXT:    add a4, a4, a5
; RV32V-NEXT:    add a4, sp, a4
; RV32V-NEXT:    addi a4, a4, 32
; RV32V-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v24, v8, v24
; RV32V-NEXT:    vsll.vi v24, v24, 8
; RV32V-NEXT:    vand.vx v0, v8, a3
; RV32V-NEXT:    vsll.vi v0, v0, 24
; RV32V-NEXT:    vor.vv v24, v0, v24
; RV32V-NEXT:    vsll.vx v0, v8, a0
; RV32V-NEXT:    vand.vx v8, v8, a2
; RV32V-NEXT:    vsll.vx v8, v8, a1
; RV32V-NEXT:    vor.vv v8, v0, v8
; RV32V-NEXT:    vor.vv v8, v8, v24
; RV32V-NEXT:    vor.vv v8, v8, v16
; RV32V-NEXT:    vsrl.vi v16, v8, 4
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 4
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 2
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 6
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vsll.vi v8, v8, 2
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v16, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a1, a1, a0
; RV32V-NEXT:    slli a0, a0, 1
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add a0, sp, a0
; RV32V-NEXT:    addi a0, a0, 32
; RV32V-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vand.vv v8, v8, v24
; RV32V-NEXT:    vadd.vv v8, v8, v8
; RV32V-NEXT:    vor.vv v8, v16, v8
; RV32V-NEXT:    vsrl.vi v8, v8, 1
; RV32V-NEXT:    csrr a0, vlenb
; RV32V-NEXT:    slli a0, a0, 4
; RV32V-NEXT:    mv a1, a0
; RV32V-NEXT:    slli a0, a0, 3
; RV32V-NEXT:    add a0, a0, a1
; RV32V-NEXT:    add sp, sp, a0
; RV32V-NEXT:    addi sp, sp, 32
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv8i64_vx:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -48
; RV64V-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    sub sp, sp, a1
; RV64V-NEXT:    li a1, 56
; RV64V-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
; RV64V-NEXT:    vsrl.vx v16, v8, a1
; RV64V-NEXT:    li a2, 40
; RV64V-NEXT:    vsrl.vx v24, v8, a2
; RV64V-NEXT:    lui a3, 16
; RV64V-NEXT:    addi a3, a3, -256
; RV64V-NEXT:    vand.vx v24, v24, a3
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    lui a4, 4080
; RV64V-NEXT:    vand.vx v24, v24, a4
; RV64V-NEXT:    vsrl.vi v0, v8, 8
; RV64V-NEXT:    li a5, 255
; RV64V-NEXT:    slli a5, a5, 24
; RV64V-NEXT:    vand.vx v0, v0, a5
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vx v24, v8, a4
; RV64V-NEXT:    vsll.vi v24, v24, 24
; RV64V-NEXT:    vand.vx v0, v8, a5
; RV64V-NEXT:    vsll.vi v0, v0, 8
; RV64V-NEXT:    vor.vv v24, v24, v0
; RV64V-NEXT:    vsll.vx v0, v8, a1
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v0, v8
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    lui a6, 61681
; RV64V-NEXT:    addi a6, a6, -241
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v16, v16, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    lui a7, 209715
; RV64V-NEXT:    addi a7, a7, 819
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    lui t0, 349525
; RV64V-NEXT:    addi t0, t0, 1365
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    vand.vx v16, v16, t0
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v16, v16, v8
; RV64V-NEXT:    lui t1, 139810
; RV64V-NEXT:    addi t1, t1, 546
; RV64V-NEXT:    slli t2, t1, 32
; RV64V-NEXT:    add t1, t1, t2
; RV64V-NEXT:    vand.vx v8, v16, t1
; RV64V-NEXT:    vmv.v.v v24, v16
; RV64V-NEXT:    csrr t2, vlenb
; RV64V-NEXT:    slli t2, t2, 3
; RV64V-NEXT:    mv t3, t2
; RV64V-NEXT:    slli t2, t2, 2
; RV64V-NEXT:    add t2, t2, t3
; RV64V-NEXT:    add t2, sp, t2
; RV64V-NEXT:    addi t2, t2, 32
; RV64V-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    srli t2, a0, 24
; RV64V-NEXT:    and t2, t2, a4
; RV64V-NEXT:    srli t3, a0, 8
; RV64V-NEXT:    and t3, t3, a5
; RV64V-NEXT:    srli t4, a0, 40
; RV64V-NEXT:    or t2, t3, t2
; RV64V-NEXT:    and t3, t4, a3
; RV64V-NEXT:    srli t4, a0, 56
; RV64V-NEXT:    lui t5, 69905
; RV64V-NEXT:    or t3, t3, t4
; RV64V-NEXT:    addi t4, t5, 273
; RV64V-NEXT:    and t5, a0, a4
; RV64V-NEXT:    slli t6, t4, 32
; RV64V-NEXT:    slli t5, t5, 24
; RV64V-NEXT:    add t4, t4, t6
; RV64V-NEXT:    srliw t6, a0, 24
; RV64V-NEXT:    vand.vx v16, v16, t4
; RV64V-NEXT:    csrr s0, vlenb
; RV64V-NEXT:    slli s0, s0, 4
; RV64V-NEXT:    add s0, sp, s0
; RV64V-NEXT:    addi s0, s0, 32
; RV64V-NEXT:    vs8r.v v24, (s0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr s0, vlenb
; RV64V-NEXT:    slli s0, s0, 5
; RV64V-NEXT:    add s0, sp, s0
; RV64V-NEXT:    addi s0, s0, 32
; RV64V-NEXT:    vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    slli t6, t6, 32
; RV64V-NEXT:    and s0, a0, a3
; RV64V-NEXT:    slli s0, s0, 40
; RV64V-NEXT:    slli a0, a0, 56
; RV64V-NEXT:    or t5, t5, t6
; RV64V-NEXT:    or a0, a0, s0
; RV64V-NEXT:    or t2, t2, t3
; RV64V-NEXT:    or a0, a0, t5
; RV64V-NEXT:    or a0, a0, t2
; RV64V-NEXT:    srli t2, a0, 4
; RV64V-NEXT:    and a0, a0, a6
; RV64V-NEXT:    and t2, t2, a6
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    or a0, t2, a0
; RV64V-NEXT:    srli t2, a0, 2
; RV64V-NEXT:    and a0, a0, a7
; RV64V-NEXT:    and t2, t2, a7
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    or a0, t2, a0
; RV64V-NEXT:    srli t2, a0, 1
; RV64V-NEXT:    and a0, a0, t0
; RV64V-NEXT:    and t2, t2, t0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    or s0, t2, a0
; RV64V-NEXT:    and a0, s0, t4
; RV64V-NEXT:    vmul.vx v8, v8, a0
; RV64V-NEXT:    sd a1, 8(sp) # 8-byte Folded Spill
; RV64V-NEXT:    sd a2, 0(sp) # 8-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    and t2, s0, t1
; RV64V-NEXT:    vmul.vx v16, v16, t2
; RV64V-NEXT:    lui t3, 279620
; RV64V-NEXT:    addi t3, t3, 1092
; RV64V-NEXT:    slli t6, t3, 32
; RV64V-NEXT:    add t6, t3, t6
; RV64V-NEXT:    vand.vx v0, v24, t6
; RV64V-NEXT:    lui t3, %hi(.LCPI43_0)
; RV64V-NEXT:    ld t3, %lo(.LCPI43_0)(t3)
; RV64V-NEXT:    and t5, s0, t3
; RV64V-NEXT:    vmul.vx v8, v0, t5
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v16, v16, v24
; RV64V-NEXT:    vxor.vv v8, v16, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vand.vx v16, v8, t3
; RV64V-NEXT:    and s0, s0, t6
; RV64V-NEXT:    vmul.vx v8, v16, s0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 2
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vx v8, v8, t5
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 5
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vx v8, v8, a0
; RV64V-NEXT:    addi a1, sp, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi a1, sp, 32
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v24, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmul.vx v8, v0, s0
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmul.vx v8, v16, t2
; RV64V-NEXT:    addi a1, sp, 32
; RV64V-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 4
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v8
; RV64V-NEXT:    addi a1, sp, 32
; RV64V-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v24, v8
; RV64V-NEXT:    csrr a1, vlenb
; RV64V-NEXT:    slli a1, a1, 3
; RV64V-NEXT:    mv a2, a1
; RV64V-NEXT:    slli a1, a1, 1
; RV64V-NEXT:    add a1, a1, a2
; RV64V-NEXT:    ld a2, 0(sp) # 8-byte Folded Reload
; RV64V-NEXT:    add a1, sp, a1
; RV64V-NEXT:    addi a1, a1, 32
; RV64V-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    ld a1, 8(sp) # 8-byte Folded Reload
; RV64V-NEXT:    vand.vx v24, v24, t1
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v24, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vand.vx v8, v8, t4
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t4, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t4, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vx v8, v8, t2
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 5
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vx v8, v8, s0
; RV64V-NEXT:    addi t1, sp, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t4, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v24, v24, v8
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t4, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v24, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    addi t1, sp, 32
; RV64V-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v24, v8
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmul.vx v8, v0, a0
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    vmul.vx v8, v16, t5
; RV64V-NEXT:    addi t1, sp, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v24, v24, v8
; RV64V-NEXT:    addi t1, sp, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v24, v8
; RV64V-NEXT:    vand.vx v8, v8, t6
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t4, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vx v8, v8, s0
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 5
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vmul.vx v8, v8, t5
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 5
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t4, t1
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t1, t1, t4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v24, v24, v8
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    mv t4, t1
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    add t1, t1, t4
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vs8r.v v24, (t1) # vscale x 64-byte Folded Spill
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 3
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    csrr t1, vlenb
; RV64V-NEXT:    slli t1, t1, 5
; RV64V-NEXT:    add t1, sp, t1
; RV64V-NEXT:    addi t1, t1, 32
; RV64V-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vxor.vv v8, v24, v8
; RV64V-NEXT:    vmul.vx v24, v0, t2
; RV64V-NEXT:    vmul.vx v16, v16, a0
; RV64V-NEXT:    vxor.vv v8, v8, v24
; RV64V-NEXT:    vxor.vv v8, v8, v16
; RV64V-NEXT:    vand.vx v8, v8, t3
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 3
; RV64V-NEXT:    mv t1, a0
; RV64V-NEXT:    slli a0, a0, 2
; RV64V-NEXT:    add a0, a0, t1
; RV64V-NEXT:    add a0, sp, a0
; RV64V-NEXT:    addi a0, a0, 32
; RV64V-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vx v16, v8, a1
; RV64V-NEXT:    vsrl.vx v24, v8, a2
; RV64V-NEXT:    vand.vx v24, v24, a3
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vsrl.vi v24, v8, 24
; RV64V-NEXT:    vand.vx v24, v24, a4
; RV64V-NEXT:    vsrl.vi v0, v8, 8
; RV64V-NEXT:    vand.vx v0, v0, a5
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    vor.vv v16, v24, v16
; RV64V-NEXT:    vand.vx v24, v8, a5
; RV64V-NEXT:    vsll.vi v24, v24, 8
; RV64V-NEXT:    vand.vx v0, v8, a4
; RV64V-NEXT:    vsll.vi v0, v0, 24
; RV64V-NEXT:    vor.vv v24, v0, v24
; RV64V-NEXT:    vsll.vx v0, v8, a1
; RV64V-NEXT:    vand.vx v8, v8, a3
; RV64V-NEXT:    vsll.vx v8, v8, a2
; RV64V-NEXT:    vor.vv v8, v0, v8
; RV64V-NEXT:    vor.vv v8, v8, v24
; RV64V-NEXT:    vor.vv v8, v8, v16
; RV64V-NEXT:    vsrl.vi v16, v8, 4
; RV64V-NEXT:    vand.vx v16, v16, a6
; RV64V-NEXT:    vand.vx v8, v8, a6
; RV64V-NEXT:    vsll.vi v8, v8, 4
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 2
; RV64V-NEXT:    vand.vx v16, v16, a7
; RV64V-NEXT:    vand.vx v8, v8, a7
; RV64V-NEXT:    vsll.vi v8, v8, 2
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v16, v8, 1
; RV64V-NEXT:    vand.vx v16, v16, t0
; RV64V-NEXT:    vand.vx v8, v8, t0
; RV64V-NEXT:    vadd.vv v8, v8, v8
; RV64V-NEXT:    vor.vv v8, v16, v8
; RV64V-NEXT:    vsrl.vi v8, v8, 1
; RV64V-NEXT:    csrr a0, vlenb
; RV64V-NEXT:    slli a0, a0, 4
; RV64V-NEXT:    mv a1, a0
; RV64V-NEXT:    slli a0, a0, 1
; RV64V-NEXT:    add a0, a0, a1
; RV64V-NEXT:    add sp, sp, a0
; RV64V-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
; RV64V-NEXT:    addi sp, sp, 48
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv8i64_vx:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    sw a0, 8(sp)
; RV32ZVBC64-NEXT:    sw a1, 12(sp)
; RV32ZVBC64-NEXT:    addi a0, sp, 8
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV32ZVBC64-NEXT:    vlse64.v v16, (a0), zero
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v16
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv8i64_vx:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV64ZVBC64-NEXT:    vclmulh.vx v8, v8, a0
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv8i64_vx:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -32
; RV32ZVBC32-NEXT:    csrr a2, vlenb
; RV32ZVBC32-NEXT:    slli a2, a2, 4
; RV32ZVBC32-NEXT:    mv a3, a2
; RV32ZVBC32-NEXT:    slli a2, a2, 3
; RV32ZVBC32-NEXT:    add a2, a2, a3
; RV32ZVBC32-NEXT:    sub sp, sp, a2
; RV32ZVBC32-NEXT:    sw a0, 16(sp)
; RV32ZVBC32-NEXT:    sw a1, 20(sp)
; RV32ZVBC32-NEXT:    addi a0, sp, 16
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vlse64.v v16, (a0), zero
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsrl.vx v24, v16, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v0, v16, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vand.vx v0, v0, a2
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a3, vlenb
; RV32ZVBC32-NEXT:    slli a3, a3, 7
; RV32ZVBC32-NEXT:    add a3, sp, a3
; RV32ZVBC32-NEXT:    addi a3, a3, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v0, v16, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    sw a3, 24(sp)
; RV32ZVBC32-NEXT:    sw zero, 28(sp)
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    addi a4, sp, 24
; RV32ZVBC32-NEXT:    vand.vx v24, v0, a3
; RV32ZVBC32-NEXT:    csrr a5, vlenb
; RV32ZVBC32-NEXT:    slli a5, a5, 3
; RV32ZVBC32-NEXT:    mv a6, a5
; RV32ZVBC32-NEXT:    slli a5, a5, 1
; RV32ZVBC32-NEXT:    add a6, a6, a5
; RV32ZVBC32-NEXT:    slli a5, a5, 1
; RV32ZVBC32-NEXT:    add a6, a6, a5
; RV32ZVBC32-NEXT:    slli a5, a5, 1
; RV32ZVBC32-NEXT:    add a5, a5, a6
; RV32ZVBC32-NEXT:    add a5, sp, a5
; RV32ZVBC32-NEXT:    addi a5, a5, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vlse64.v v24, (a4), zero
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v0, v16, v24
; RV32ZVBC32-NEXT:    vsll.vi v0, v0, 8
; RV32ZVBC32-NEXT:    vand.vx v24, v16, a3
; RV32ZVBC32-NEXT:    vsll.vi v24, v24, 24
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vsll.vx v0, v16, a0
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC32-NEXT:    vsll.vx v16, v16, a1
; RV32ZVBC32-NEXT:    vor.vv v16, v0, v16
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 4
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v0, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 4
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 2
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v0, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 6
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 2
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    vsrl.vi v24, v16, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v0, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v0
; RV32ZVBC32-NEXT:    vadd.vv v16, v16, v16
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC32-NEXT:    vsrl.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV32ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v0, v0, v16
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vx v24, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v24, v24, a1
; RV32ZVBC32-NEXT:    vsll.vx v0, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    vand.vx v0, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 8
; RV32ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 6
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v24, v16, v8
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v16, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v8, a4
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m8, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v16, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m8, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v8, v0, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vand.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v0, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vmul.vv v16, v0, v8
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v0, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v16, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC32-NEXT:    addi a4, sp, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v16, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v0, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v0, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v8, v24, v8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v16, v16, v0
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 2
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 5
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vmul.vv v24, v24, v0
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vxor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a5, a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 1
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a2
; RV32ZVBC32-NEXT:    vsrl.vx v24, v8, a0
; RV32ZVBC32-NEXT:    vor.vv v16, v16, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV32ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV32ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v0, v0, v16
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 7
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV32ZVBC32-NEXT:    csrr a4, vlenb
; RV32ZVBC32-NEXT:    slli a4, a4, 3
; RV32ZVBC32-NEXT:    mv a5, a4
; RV32ZVBC32-NEXT:    slli a4, a4, 4
; RV32ZVBC32-NEXT:    add a4, a4, a5
; RV32ZVBC32-NEXT:    add a4, sp, a4
; RV32ZVBC32-NEXT:    addi a4, a4, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v24, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v24, v24, 8
; RV32ZVBC32-NEXT:    vand.vx v0, v8, a3
; RV32ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV32ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV32ZVBC32-NEXT:    vsll.vx v0, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v8, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v8, v8, a1
; RV32ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 6
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a1, a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 1
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add a0, sp, a0
; RV32ZVBC32-NEXT:    addi a0, a0, 32
; RV32ZVBC32-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vand.vv v8, v8, v24
; RV32ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV32ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV32ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV32ZVBC32-NEXT:    csrr a0, vlenb
; RV32ZVBC32-NEXT:    slli a0, a0, 4
; RV32ZVBC32-NEXT:    mv a1, a0
; RV32ZVBC32-NEXT:    slli a0, a0, 3
; RV32ZVBC32-NEXT:    add a0, a0, a1
; RV32ZVBC32-NEXT:    add sp, sp, a0
; RV32ZVBC32-NEXT:    addi sp, sp, 32
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv8i64_vx:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    addi sp, sp, -48
; RV64ZVBC32-NEXT:    sd s0, 40(sp) # 8-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 4
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 1
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    sub sp, sp, a1
; RV64ZVBC32-NEXT:    li a1, 56
; RV64ZVBC32-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV64ZVBC32-NEXT:    li a2, 40
; RV64ZVBC32-NEXT:    vsrl.vx v24, v8, a2
; RV64ZVBC32-NEXT:    lui a3, 16
; RV64ZVBC32-NEXT:    addi a3, a3, -256
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC32-NEXT:    lui a4, 4080
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a4
; RV64ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV64ZVBC32-NEXT:    li a5, 255
; RV64ZVBC32-NEXT:    slli a5, a5, 24
; RV64ZVBC32-NEXT:    vand.vx v0, v0, a5
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vand.vx v24, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v24, v24, 24
; RV64ZVBC32-NEXT:    vand.vx v0, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v0, v0, 8
; RV64ZVBC32-NEXT:    vor.vv v24, v24, v0
; RV64ZVBC32-NEXT:    vsll.vx v0, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC32-NEXT:    lui a6, 61681
; RV64ZVBC32-NEXT:    addi a6, a6, -241
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC32-NEXT:    lui a7, 209715
; RV64ZVBC32-NEXT:    addi a7, a7, 819
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC32-NEXT:    lui t0, 349525
; RV64ZVBC32-NEXT:    addi t0, t0, 1365
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    vand.vx v16, v16, t0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v16, v16, v8
; RV64ZVBC32-NEXT:    lui t1, 139810
; RV64ZVBC32-NEXT:    addi t1, t1, 546
; RV64ZVBC32-NEXT:    slli t2, t1, 32
; RV64ZVBC32-NEXT:    add t1, t1, t2
; RV64ZVBC32-NEXT:    vand.vx v8, v16, t1
; RV64ZVBC32-NEXT:    vmv.v.v v24, v16
; RV64ZVBC32-NEXT:    csrr t2, vlenb
; RV64ZVBC32-NEXT:    slli t2, t2, 3
; RV64ZVBC32-NEXT:    mv t3, t2
; RV64ZVBC32-NEXT:    slli t2, t2, 2
; RV64ZVBC32-NEXT:    add t2, t2, t3
; RV64ZVBC32-NEXT:    add t2, sp, t2
; RV64ZVBC32-NEXT:    addi t2, t2, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    srli t2, a0, 24
; RV64ZVBC32-NEXT:    and t2, t2, a4
; RV64ZVBC32-NEXT:    srli t3, a0, 8
; RV64ZVBC32-NEXT:    and t3, t3, a5
; RV64ZVBC32-NEXT:    srli t4, a0, 40
; RV64ZVBC32-NEXT:    or t2, t3, t2
; RV64ZVBC32-NEXT:    and t3, t4, a3
; RV64ZVBC32-NEXT:    srli t4, a0, 56
; RV64ZVBC32-NEXT:    lui t5, 69905
; RV64ZVBC32-NEXT:    or t3, t3, t4
; RV64ZVBC32-NEXT:    addi t4, t5, 273
; RV64ZVBC32-NEXT:    and t5, a0, a4
; RV64ZVBC32-NEXT:    slli t6, t4, 32
; RV64ZVBC32-NEXT:    slli t5, t5, 24
; RV64ZVBC32-NEXT:    add t4, t4, t6
; RV64ZVBC32-NEXT:    srliw t6, a0, 24
; RV64ZVBC32-NEXT:    vand.vx v16, v16, t4
; RV64ZVBC32-NEXT:    csrr s0, vlenb
; RV64ZVBC32-NEXT:    slli s0, s0, 4
; RV64ZVBC32-NEXT:    add s0, sp, s0
; RV64ZVBC32-NEXT:    addi s0, s0, 32
; RV64ZVBC32-NEXT:    vs8r.v v24, (s0) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr s0, vlenb
; RV64ZVBC32-NEXT:    slli s0, s0, 5
; RV64ZVBC32-NEXT:    add s0, sp, s0
; RV64ZVBC32-NEXT:    addi s0, s0, 32
; RV64ZVBC32-NEXT:    vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    slli t6, t6, 32
; RV64ZVBC32-NEXT:    and s0, a0, a3
; RV64ZVBC32-NEXT:    slli s0, s0, 40
; RV64ZVBC32-NEXT:    slli a0, a0, 56
; RV64ZVBC32-NEXT:    or t5, t5, t6
; RV64ZVBC32-NEXT:    or a0, a0, s0
; RV64ZVBC32-NEXT:    or t2, t2, t3
; RV64ZVBC32-NEXT:    or a0, a0, t5
; RV64ZVBC32-NEXT:    or a0, a0, t2
; RV64ZVBC32-NEXT:    srli t2, a0, 4
; RV64ZVBC32-NEXT:    and a0, a0, a6
; RV64ZVBC32-NEXT:    and t2, t2, a6
; RV64ZVBC32-NEXT:    slli a0, a0, 4
; RV64ZVBC32-NEXT:    or a0, t2, a0
; RV64ZVBC32-NEXT:    srli t2, a0, 2
; RV64ZVBC32-NEXT:    and a0, a0, a7
; RV64ZVBC32-NEXT:    and t2, t2, a7
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    or a0, t2, a0
; RV64ZVBC32-NEXT:    srli t2, a0, 1
; RV64ZVBC32-NEXT:    and a0, a0, t0
; RV64ZVBC32-NEXT:    and t2, t2, t0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    or s0, t2, a0
; RV64ZVBC32-NEXT:    and a0, s0, t4
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, a0
; RV64ZVBC32-NEXT:    sd a1, 8(sp) # 8-byte Folded Spill
; RV64ZVBC32-NEXT:    sd a2, 0(sp) # 8-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 1
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    and t2, s0, t1
; RV64ZVBC32-NEXT:    vmul.vx v16, v16, t2
; RV64ZVBC32-NEXT:    lui t3, 279620
; RV64ZVBC32-NEXT:    addi t3, t3, 1092
; RV64ZVBC32-NEXT:    slli t6, t3, 32
; RV64ZVBC32-NEXT:    add t6, t3, t6
; RV64ZVBC32-NEXT:    vand.vx v0, v24, t6
; RV64ZVBC32-NEXT:    lui t3, %hi(.LCPI43_0)
; RV64ZVBC32-NEXT:    ld t3, %lo(.LCPI43_0)(t3)
; RV64ZVBC32-NEXT:    and t5, s0, t3
; RV64ZVBC32-NEXT:    vmul.vx v8, v0, t5
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 1
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v16, v16, v24
; RV64ZVBC32-NEXT:    vxor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 1
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 4
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v16, v8, t3
; RV64ZVBC32-NEXT:    and s0, s0, t6
; RV64ZVBC32-NEXT:    vmul.vx v8, v16, s0
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 4
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 2
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, t5
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 5
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, a0
; RV64ZVBC32-NEXT:    addi a1, sp, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 1
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 4
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v8
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 1
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    addi a1, sp, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 4
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vmul.vx v8, v0, s0
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vmul.vx v8, v16, t2
; RV64ZVBC32-NEXT:    addi a1, sp, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 4
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v8
; RV64ZVBC32-NEXT:    addi a1, sp, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    csrr a1, vlenb
; RV64ZVBC32-NEXT:    slli a1, a1, 3
; RV64ZVBC32-NEXT:    mv a2, a1
; RV64ZVBC32-NEXT:    slli a1, a1, 1
; RV64ZVBC32-NEXT:    add a1, a1, a2
; RV64ZVBC32-NEXT:    ld a2, 0(sp) # 8-byte Folded Reload
; RV64ZVBC32-NEXT:    add a1, sp, a1
; RV64ZVBC32-NEXT:    addi a1, a1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    ld a1, 8(sp) # 8-byte Folded Reload
; RV64ZVBC32-NEXT:    vand.vx v24, v24, t1
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v24, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t4
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t4, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t4, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, t2
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 5
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, s0
; RV64ZVBC32-NEXT:    addi t1, sp, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t4, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v24, v24, v8
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t4, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v24, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    addi t1, sp, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vmul.vx v8, v0, a0
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    vmul.vx v8, v16, t5
; RV64ZVBC32-NEXT:    addi t1, sp, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v24, v24, v8
; RV64ZVBC32-NEXT:    addi t1, sp, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t6
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t4, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, s0
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 5
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vmul.vx v8, v8, t5
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 5
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v8, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t4, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t1, t1, t4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v24, v24, v8
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    mv t4, t1
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    add t1, t1, t4
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vs8r.v v24, (t1) # vscale x 64-byte Folded Spill
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 3
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v8, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    csrr t1, vlenb
; RV64ZVBC32-NEXT:    slli t1, t1, 5
; RV64ZVBC32-NEXT:    add t1, sp, t1
; RV64ZVBC32-NEXT:    addi t1, t1, 32
; RV64ZVBC32-NEXT:    vl8r.v v24, (t1) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vxor.vv v8, v24, v8
; RV64ZVBC32-NEXT:    vmul.vx v24, v0, t2
; RV64ZVBC32-NEXT:    vmul.vx v16, v16, a0
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v24
; RV64ZVBC32-NEXT:    vxor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t3
; RV64ZVBC32-NEXT:    csrr a0, vlenb
; RV64ZVBC32-NEXT:    slli a0, a0, 3
; RV64ZVBC32-NEXT:    mv t1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 2
; RV64ZVBC32-NEXT:    add a0, a0, t1
; RV64ZVBC32-NEXT:    add a0, sp, a0
; RV64ZVBC32-NEXT:    addi a0, a0, 32
; RV64ZVBC32-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vx v16, v8, a1
; RV64ZVBC32-NEXT:    vsrl.vx v24, v8, a2
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a3
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vsrl.vi v24, v8, 24
; RV64ZVBC32-NEXT:    vand.vx v24, v24, a4
; RV64ZVBC32-NEXT:    vsrl.vi v0, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v0, v0, a5
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    vor.vv v16, v24, v16
; RV64ZVBC32-NEXT:    vand.vx v24, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v24, v24, 8
; RV64ZVBC32-NEXT:    vand.vx v0, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v0, v0, 24
; RV64ZVBC32-NEXT:    vor.vv v24, v0, v24
; RV64ZVBC32-NEXT:    vsll.vx v0, v8, a1
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v8, v8, a2
; RV64ZVBC32-NEXT:    vor.vv v8, v0, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v24
; RV64ZVBC32-NEXT:    vor.vv v8, v8, v16
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 4
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a6
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a6
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 4
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 2
; RV64ZVBC32-NEXT:    vand.vx v16, v16, a7
; RV64ZVBC32-NEXT:    vand.vx v8, v8, a7
; RV64ZVBC32-NEXT:    vsll.vi v8, v8, 2
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v16, v8, 1
; RV64ZVBC32-NEXT:    vand.vx v16, v16, t0
; RV64ZVBC32-NEXT:    vand.vx v8, v8, t0
; RV64ZVBC32-NEXT:    vadd.vv v8, v8, v8
; RV64ZVBC32-NEXT:    vor.vv v8, v16, v8
; RV64ZVBC32-NEXT:    vsrl.vi v8, v8, 1
; RV64ZVBC32-NEXT:    csrr a0, vlenb
; RV64ZVBC32-NEXT:    slli a0, a0, 4
; RV64ZVBC32-NEXT:    mv a1, a0
; RV64ZVBC32-NEXT:    slli a0, a0, 1
; RV64ZVBC32-NEXT:    add a0, a0, a1
; RV64ZVBC32-NEXT:    add sp, sp, a0
; RV64ZVBC32-NEXT:    ld s0, 40(sp) # 8-byte Folded Reload
; RV64ZVBC32-NEXT:    addi sp, sp, 48
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i128 0
  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
  %va.ext = zext <vscale x 8 x i64> %va to <vscale x 8 x i128>
  %vb.ext = zext <vscale x 8 x i64> %vb to <vscale x 8 x i128>
  %clmul = call <vscale x 8 x i128> @llvm.clmul.nxv8i128(<vscale x 8 x i128> %va.ext, <vscale x 8 x i128> %vb.ext)
  %res.ext = lshr <vscale x 8 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 8 x i128> %res.ext to <vscale x 8 x i64>
  ret <vscale x 8 x i64> %res
}

define <vscale x 1 x i64> @clmulh_nxv1i64_vv_mask(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %mask) {
; RV32V-LABEL: clmulh_nxv1i64_vv_mask:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    .cfi_def_cfa_offset 16
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vx v11, v9, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v10, v9, a1
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    vsrl.vi v12, v9, 24
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    addi a4, sp, 8
; RV32V-NEXT:    vand.vx v13, v10, a2
; RV32V-NEXT:    sw a3, 8(sp)
; RV32V-NEXT:    sw zero, 12(sp)
; RV32V-NEXT:    vsrl.vi v14, v9, 8
; RV32V-NEXT:    vlse64.v v10, (a4), zero
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    vand.vx v12, v12, a3
; RV32V-NEXT:    vand.vv v14, v14, v10
; RV32V-NEXT:    vor.vv v11, v13, v11
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vand.vx v13, v9, a2
; RV32V-NEXT:    vsll.vx v14, v9, a0
; RV32V-NEXT:    vsll.vx v13, v13, a1
; RV32V-NEXT:    vand.vx v15, v9, a3
; RV32V-NEXT:    vand.vv v9, v9, v10
; RV32V-NEXT:    vsll.vi v15, v15, 24
; RV32V-NEXT:    vsll.vi v9, v9, 8
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v9, v15, v9
; RV32V-NEXT:    vor.vv v11, v12, v11
; RV32V-NEXT:    vor.vv v9, v13, v9
; RV32V-NEXT:    vor.vv v11, v9, v11
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v9, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v12, v11, 4
; RV32V-NEXT:    vand.vv v11, v11, v9
; RV32V-NEXT:    vand.vv v12, v12, v9
; RV32V-NEXT:    vsll.vi v11, v11, 4
; RV32V-NEXT:    vor.vv v12, v12, v11
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v11, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v13, v12, 2
; RV32V-NEXT:    vand.vv v12, v12, v11
; RV32V-NEXT:    vand.vv v13, v13, v11
; RV32V-NEXT:    vsll.vi v12, v12, 2
; RV32V-NEXT:    vor.vv v13, v13, v12
; RV32V-NEXT:    vsrl.vx v12, v8, a1
; RV32V-NEXT:    vsrl.vx v14, v8, a0
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    vsrl.vi v15, v8, 24
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v15, v15, a3
; RV32V-NEXT:    vand.vv v16, v16, v10
; RV32V-NEXT:    vor.vv v12, v12, v14
; RV32V-NEXT:    vor.vv v14, v16, v15
; RV32V-NEXT:    vand.vx v15, v8, a2
; RV32V-NEXT:    vsll.vx v16, v8, a0
; RV32V-NEXT:    vsll.vx v15, v15, a1
; RV32V-NEXT:    vand.vx v17, v8, a3
; RV32V-NEXT:    vand.vv v18, v8, v10
; RV32V-NEXT:    vsll.vi v17, v17, 24
; RV32V-NEXT:    vsll.vi v18, v18, 8
; RV32V-NEXT:    vor.vv v15, v16, v15
; RV32V-NEXT:    vor.vv v16, v17, v18
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vor.vv v14, v15, v16
; RV32V-NEXT:    vsrl.vi v15, v13, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    vor.vv v14, v14, v12
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v12, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v16, v14, 4
; RV32V-NEXT:    vand.vv v14, v14, v9
; RV32V-NEXT:    vand.vv v16, v16, v9
; RV32V-NEXT:    vsll.vi v14, v14, 4
; RV32V-NEXT:    vand.vv v15, v15, v12
; RV32V-NEXT:    vor.vv v14, v16, v14
; RV32V-NEXT:    vand.vv v13, v13, v12
; RV32V-NEXT:    vsrl.vi v16, v14, 2
; RV32V-NEXT:    vand.vv v14, v14, v11
; RV32V-NEXT:    vand.vv v16, v16, v11
; RV32V-NEXT:    vsll.vi v14, v14, 2
; RV32V-NEXT:    vadd.vv v13, v13, v13
; RV32V-NEXT:    vor.vv v14, v16, v14
; RV32V-NEXT:    vor.vv v13, v15, v13
; RV32V-NEXT:    vsrl.vi v15, v14, 1
; RV32V-NEXT:    vand.vv v14, v14, v12
; RV32V-NEXT:    vand.vv v15, v15, v12
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    vadd.vv v14, v14, v14
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v15, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v17, v13, v16
; RV32V-NEXT:    vand.vv v18, v14, v15
; RV32V-NEXT:    vand.vv v19, v13, v15
; RV32V-NEXT:    vand.vv v20, v14, v16
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v21, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vmul.vv v22, v18, v17
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    vmul.vv v23, v20, v19
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, mu
; RV32V-NEXT:    vand.vv v25, v13, v21
; RV32V-NEXT:    vand.vv v26, v14, v24
; RV32V-NEXT:    vxor.vv v22, v23, v22
; RV32V-NEXT:    vmul.vv v23, v26, v25
; RV32V-NEXT:    vand.vv v13, v13, v24
; RV32V-NEXT:    vand.vv v14, v14, v21
; RV32V-NEXT:    vmul.vv v27, v18, v25
; RV32V-NEXT:    vmul.vv v28, v20, v17
; RV32V-NEXT:    vxor.vv v22, v22, v23
; RV32V-NEXT:    vmul.vv v23, v14, v13
; RV32V-NEXT:    vmul.vv v29, v26, v13
; RV32V-NEXT:    vxor.vv v27, v28, v27
; RV32V-NEXT:    vmul.vv v28, v14, v19
; RV32V-NEXT:    vxor.vv v22, v22, v23
; RV32V-NEXT:    vxor.vv v23, v27, v29
; RV32V-NEXT:    vand.vv v15, v22, v15
; RV32V-NEXT:    vxor.vv v22, v23, v28
; RV32V-NEXT:    vmul.vv v23, v18, v19
; RV32V-NEXT:    vmul.vv v27, v20, v13
; RV32V-NEXT:    vand.vv v16, v22, v16
; RV32V-NEXT:    vmul.vv v22, v26, v17
; RV32V-NEXT:    vor.vv v15, v16, v15
; RV32V-NEXT:    vxor.vv v16, v27, v23
; RV32V-NEXT:    vmul.vv v13, v18, v13
; RV32V-NEXT:    vmul.vv v18, v20, v25
; RV32V-NEXT:    vxor.vv v16, v16, v22
; RV32V-NEXT:    vmul.vv v20, v14, v25
; RV32V-NEXT:    vmul.vv v19, v26, v19
; RV32V-NEXT:    vxor.vv v13, v18, v13
; RV32V-NEXT:    vmul.vv v14, v14, v17
; RV32V-NEXT:    vxor.vv v16, v16, v20
; RV32V-NEXT:    vxor.vv v13, v13, v19
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vxor.vv v13, v13, v14
; RV32V-NEXT:    vor.vv v14, v15, v16
; RV32V-NEXT:    vand.vv v13, v13, v21
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vsrl.vx v14, v13, a1
; RV32V-NEXT:    vsrl.vx v15, v13, a0
; RV32V-NEXT:    vand.vx v14, v14, a2
; RV32V-NEXT:    vsrl.vi v16, v13, 24
; RV32V-NEXT:    vsrl.vi v17, v13, 8
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vand.vv v17, v17, v10
; RV32V-NEXT:    vor.vv v14, v14, v15
; RV32V-NEXT:    vor.vv v15, v17, v16
; RV32V-NEXT:    vand.vv v10, v13, v10
; RV32V-NEXT:    vand.vx v16, v13, a3
; RV32V-NEXT:    vsll.vi v10, v10, 8
; RV32V-NEXT:    vsll.vi v16, v16, 24
; RV32V-NEXT:    vand.vx v17, v13, a2
; RV32V-NEXT:    vsll.vx v13, v13, a0
; RV32V-NEXT:    vsll.vx v17, v17, a1
; RV32V-NEXT:    vor.vv v10, v16, v10
; RV32V-NEXT:    vor.vv v13, v13, v17
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    vor.vv v10, v13, v10
; RV32V-NEXT:    vor.vv v10, v10, v14
; RV32V-NEXT:    vsrl.vi v13, v10, 4
; RV32V-NEXT:    vand.vv v10, v10, v9
; RV32V-NEXT:    vand.vv v9, v13, v9
; RV32V-NEXT:    vsll.vi v10, v10, 4
; RV32V-NEXT:    vor.vv v9, v9, v10
; RV32V-NEXT:    vsrl.vi v10, v9, 2
; RV32V-NEXT:    vand.vv v9, v9, v11
; RV32V-NEXT:    vand.vv v10, v10, v11
; RV32V-NEXT:    vsll.vi v9, v9, 2
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v10, v9, 1
; RV32V-NEXT:    vand.vv v9, v9, v12
; RV32V-NEXT:    vand.vv v10, v10, v12
; RV32V-NEXT:    vadd.vv v9, v9, v9
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    .cfi_def_cfa_offset 0
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i64_vv_mask:
; RV64V:       # %bb.0:
; RV64V-NEXT:    li a0, 56
; RV64V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
; RV64V-NEXT:    vsrl.vx v10, v9, a0
; RV64V-NEXT:    li a1, 40
; RV64V-NEXT:    vsrl.vx v11, v9, a1
; RV64V-NEXT:    lui a2, 16
; RV64V-NEXT:    vsrl.vi v12, v9, 24
; RV64V-NEXT:    addi a2, a2, -256
; RV64V-NEXT:    vand.vx v11, v11, a2
; RV64V-NEXT:    vsrl.vi v13, v9, 8
; RV64V-NEXT:    lui a3, 4080
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    li a4, 255
; RV64V-NEXT:    slli a4, a4, 24
; RV64V-NEXT:    vand.vx v13, v13, a4
; RV64V-NEXT:    vor.vv v10, v11, v10
; RV64V-NEXT:    vor.vv v11, v13, v12
; RV64V-NEXT:    vand.vx v12, v9, a3
; RV64V-NEXT:    vand.vx v13, v9, a4
; RV64V-NEXT:    vsll.vi v12, v12, 24
; RV64V-NEXT:    vsll.vi v13, v13, 8
; RV64V-NEXT:    vand.vx v14, v9, a2
; RV64V-NEXT:    vsll.vx v9, v9, a0
; RV64V-NEXT:    vsll.vx v14, v14, a1
; RV64V-NEXT:    vor.vv v12, v12, v13
; RV64V-NEXT:    vor.vv v9, v9, v14
; RV64V-NEXT:    vor.vv v10, v11, v10
; RV64V-NEXT:    vor.vv v9, v9, v12
; RV64V-NEXT:    vor.vv v9, v9, v10
; RV64V-NEXT:    lui a5, 61681
; RV64V-NEXT:    addi a5, a5, -241
; RV64V-NEXT:    vsrl.vi v10, v9, 4
; RV64V-NEXT:    slli a6, a5, 32
; RV64V-NEXT:    add a5, a5, a6
; RV64V-NEXT:    vand.vx v9, v9, a5
; RV64V-NEXT:    vand.vx v10, v10, a5
; RV64V-NEXT:    vsll.vi v9, v9, 4
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v9, 2
; RV64V-NEXT:    lui a6, 209715
; RV64V-NEXT:    addi a6, a6, 819
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vsrl.vx v11, v8, a1
; RV64V-NEXT:    vsrl.vx v12, v8, a0
; RV64V-NEXT:    vand.vx v11, v11, a2
; RV64V-NEXT:    vsrl.vi v13, v8, 24
; RV64V-NEXT:    vsrl.vi v14, v8, 8
; RV64V-NEXT:    vand.vx v13, v13, a3
; RV64V-NEXT:    vand.vx v14, v14, a4
; RV64V-NEXT:    vor.vv v11, v11, v12
; RV64V-NEXT:    vor.vv v12, v14, v13
; RV64V-NEXT:    vand.vx v13, v8, a3
; RV64V-NEXT:    vand.vx v14, v8, a4
; RV64V-NEXT:    vsll.vi v13, v13, 24
; RV64V-NEXT:    vsll.vi v14, v14, 8
; RV64V-NEXT:    vand.vx v15, v8, a2
; RV64V-NEXT:    vsll.vx v16, v8, a0
; RV64V-NEXT:    vsll.vx v15, v15, a1
; RV64V-NEXT:    vor.vv v13, v13, v14
; RV64V-NEXT:    vor.vv v14, v16, v15
; RV64V-NEXT:    vor.vv v11, v12, v11
; RV64V-NEXT:    vor.vv v12, v14, v13
; RV64V-NEXT:    vsll.vi v9, v9, 2
; RV64V-NEXT:    vor.vv v11, v12, v11
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v11, 4
; RV64V-NEXT:    vand.vx v11, v11, a5
; RV64V-NEXT:    vand.vx v10, v10, a5
; RV64V-NEXT:    vsll.vi v11, v11, 4
; RV64V-NEXT:    vsrl.vi v12, v9, 1
; RV64V-NEXT:    lui a7, 349525
; RV64V-NEXT:    addi a7, a7, 1365
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    vor.vv v10, v10, v11
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v11, v12, a7
; RV64V-NEXT:    vsrl.vi v12, v10, 2
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vand.vx v12, v12, a6
; RV64V-NEXT:    vsll.vi v10, v10, 2
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    vadd.vv v9, v9, v9
; RV64V-NEXT:    vsrl.vi v12, v10, 1
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vand.vx v12, v12, a7
; RV64V-NEXT:    vadd.vv v10, v10, v10
; RV64V-NEXT:    lui t0, 69905
; RV64V-NEXT:    vor.vv v9, v11, v9
; RV64V-NEXT:    addi t0, t0, 273
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    vor.vv v10, v12, v10
; RV64V-NEXT:    lui t2, 139810
; RV64V-NEXT:    add t1, t0, t1
; RV64V-NEXT:    addi t0, t2, 546
; RV64V-NEXT:    vand.vx v11, v9, t1
; RV64V-NEXT:    slli t2, t0, 32
; RV64V-NEXT:    add t2, t0, t2
; RV64V-NEXT:    vand.vx v12, v10, t2
; RV64V-NEXT:    vand.vx v13, v9, t2
; RV64V-NEXT:    vand.vx v14, v10, t1
; RV64V-NEXT:    lui t0, %hi(.LCPI44_0)
; RV64V-NEXT:    vmul.vv v15, v12, v11
; RV64V-NEXT:    ld t0, %lo(.LCPI44_0)(t0)
; RV64V-NEXT:    vmul.vv v16, v14, v13
; RV64V-NEXT:    lui t3, 279620
; RV64V-NEXT:    addi t3, t3, 1092
; RV64V-NEXT:    vand.vx v17, v9, t0
; RV64V-NEXT:    slli t4, t3, 32
; RV64V-NEXT:    add t3, t3, t4
; RV64V-NEXT:    vand.vx v18, v10, t3
; RV64V-NEXT:    vxor.vv v15, v16, v15
; RV64V-NEXT:    vmul.vv v16, v18, v17
; RV64V-NEXT:    vand.vx v9, v9, t3
; RV64V-NEXT:    vand.vx v10, v10, t0
; RV64V-NEXT:    vmul.vv v19, v12, v17
; RV64V-NEXT:    vmul.vv v20, v14, v11
; RV64V-NEXT:    vxor.vv v15, v15, v16
; RV64V-NEXT:    vmul.vv v16, v10, v9
; RV64V-NEXT:    vmul.vv v21, v18, v9
; RV64V-NEXT:    vxor.vv v19, v20, v19
; RV64V-NEXT:    vmul.vv v20, v10, v13
; RV64V-NEXT:    vxor.vv v15, v15, v16
; RV64V-NEXT:    vxor.vv v16, v19, v21
; RV64V-NEXT:    vand.vx v15, v15, t2
; RV64V-NEXT:    vxor.vv v16, v16, v20
; RV64V-NEXT:    vmul.vv v19, v12, v13
; RV64V-NEXT:    vmul.vv v20, v14, v9
; RV64V-NEXT:    vand.vx v16, v16, t1
; RV64V-NEXT:    vmul.vv v21, v18, v11
; RV64V-NEXT:    vor.vv v15, v16, v15
; RV64V-NEXT:    vxor.vv v16, v20, v19
; RV64V-NEXT:    vmul.vv v9, v12, v9
; RV64V-NEXT:    vmul.vv v12, v14, v17
; RV64V-NEXT:    vxor.vv v14, v16, v21
; RV64V-NEXT:    vmul.vv v16, v10, v17
; RV64V-NEXT:    vmul.vv v13, v18, v13
; RV64V-NEXT:    vxor.vv v9, v12, v9
; RV64V-NEXT:    vmul.vv v10, v10, v11
; RV64V-NEXT:    vxor.vv v11, v14, v16
; RV64V-NEXT:    vxor.vv v9, v9, v13
; RV64V-NEXT:    vand.vx v11, v11, t3
; RV64V-NEXT:    vxor.vv v9, v9, v10
; RV64V-NEXT:    vor.vv v10, v15, v11
; RV64V-NEXT:    vand.vx v9, v9, t0
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vx v10, v9, a1
; RV64V-NEXT:    vsrl.vx v11, v9, a0
; RV64V-NEXT:    vand.vx v10, v10, a2
; RV64V-NEXT:    vsrl.vi v12, v9, 24
; RV64V-NEXT:    vsrl.vi v13, v9, 8
; RV64V-NEXT:    vand.vx v12, v12, a3
; RV64V-NEXT:    vand.vx v13, v13, a4
; RV64V-NEXT:    vor.vv v10, v10, v11
; RV64V-NEXT:    vor.vv v11, v13, v12
; RV64V-NEXT:    vand.vx v12, v9, a4
; RV64V-NEXT:    vand.vx v13, v9, a3
; RV64V-NEXT:    vsll.vi v12, v12, 8
; RV64V-NEXT:    vsll.vi v13, v13, 24
; RV64V-NEXT:    vand.vx v14, v9, a2
; RV64V-NEXT:    vsll.vx v9, v9, a0
; RV64V-NEXT:    vsll.vx v14, v14, a1
; RV64V-NEXT:    vor.vv v12, v13, v12
; RV64V-NEXT:    vor.vv v9, v9, v14
; RV64V-NEXT:    vor.vv v10, v11, v10
; RV64V-NEXT:    vor.vv v9, v9, v12
; RV64V-NEXT:    vor.vv v9, v9, v10
; RV64V-NEXT:    vsrl.vi v10, v9, 4
; RV64V-NEXT:    vand.vx v9, v9, a5
; RV64V-NEXT:    vand.vx v10, v10, a5
; RV64V-NEXT:    vsll.vi v9, v9, 4
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v9, 2
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vsll.vi v9, v9, 2
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v9, 1
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vadd.vv v9, v9, v9
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i64_vv_mask:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v9, v0.t
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i64_vv_mask:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
; RV64ZVBC64-NEXT:    vclmulh.vv v8, v8, v9, v0.t
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i64_vv_mask:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -16
; RV32ZVBC32-NEXT:    .cfi_def_cfa_offset 16
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vx v11, v9, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v10, v9, a1
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    vsrl.vi v12, v9, 24
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    addi a4, sp, 8
; RV32ZVBC32-NEXT:    vand.vx v13, v10, a2
; RV32ZVBC32-NEXT:    sw a3, 8(sp)
; RV32ZVBC32-NEXT:    sw zero, 12(sp)
; RV32ZVBC32-NEXT:    vsrl.vi v14, v9, 8
; RV32ZVBC32-NEXT:    vlse64.v v10, (a4), zero
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v10
; RV32ZVBC32-NEXT:    vor.vv v11, v13, v11
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vand.vx v13, v9, a2
; RV32ZVBC32-NEXT:    vsll.vx v14, v9, a0
; RV32ZVBC32-NEXT:    vsll.vx v13, v13, a1
; RV32ZVBC32-NEXT:    vand.vx v15, v9, a3
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v10
; RV32ZVBC32-NEXT:    vsll.vi v15, v15, 24
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 8
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v9, v15, v9
; RV32ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV32ZVBC32-NEXT:    vor.vv v9, v13, v9
; RV32ZVBC32-NEXT:    vor.vv v11, v9, v11
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v9, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v12, v11, 4
; RV32ZVBC32-NEXT:    vand.vv v11, v11, v9
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v9
; RV32ZVBC32-NEXT:    vsll.vi v11, v11, 4
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v11
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v11, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v13, v12, 2
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v11
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v11
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 2
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vx v12, v8, a1
; RV32ZVBC32-NEXT:    vsrl.vx v14, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    vsrl.vi v15, v8, 24
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC32-NEXT:    vand.vx v15, v15, a3
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v10
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v15
; RV32ZVBC32-NEXT:    vand.vx v15, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v16, v8, a0
; RV32ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV32ZVBC32-NEXT:    vand.vx v17, v8, a3
; RV32ZVBC32-NEXT:    vand.vv v18, v8, v10
; RV32ZVBC32-NEXT:    vsll.vi v17, v17, 24
; RV32ZVBC32-NEXT:    vsll.vi v18, v18, 8
; RV32ZVBC32-NEXT:    vor.vv v15, v16, v15
; RV32ZVBC32-NEXT:    vor.vv v16, v17, v18
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v16
; RV32ZVBC32-NEXT:    vsrl.vi v15, v13, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    vor.vv v14, v14, v12
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v12, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v16, v14, 4
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v9
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v9
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 4
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v12
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v14, 2
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v11
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v11
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 2
; RV32ZVBC32-NEXT:    vadd.vv v13, v13, v13
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV32ZVBC32-NEXT:    vor.vv v13, v15, v13
; RV32ZVBC32-NEXT:    vsrl.vi v15, v14, 1
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v12
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v12
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    vadd.vv v14, v14, v14
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v16, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v14
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v15, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v17, v13, v16
; RV32ZVBC32-NEXT:    vand.vv v18, v14, v15
; RV32ZVBC32-NEXT:    vand.vv v19, v13, v15
; RV32ZVBC32-NEXT:    vand.vv v20, v14, v16
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v21, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vmul.vv v22, v18, v17
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    vmul.vv v23, v20, v19
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v24, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, mu
; RV32ZVBC32-NEXT:    vand.vv v25, v13, v21
; RV32ZVBC32-NEXT:    vand.vv v26, v14, v24
; RV32ZVBC32-NEXT:    vxor.vv v22, v23, v22
; RV32ZVBC32-NEXT:    vmul.vv v23, v26, v25
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v24
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v21
; RV32ZVBC32-NEXT:    vmul.vv v27, v18, v25
; RV32ZVBC32-NEXT:    vmul.vv v28, v20, v17
; RV32ZVBC32-NEXT:    vxor.vv v22, v22, v23
; RV32ZVBC32-NEXT:    vmul.vv v23, v14, v13
; RV32ZVBC32-NEXT:    vmul.vv v29, v26, v13
; RV32ZVBC32-NEXT:    vxor.vv v27, v28, v27
; RV32ZVBC32-NEXT:    vmul.vv v28, v14, v19
; RV32ZVBC32-NEXT:    vxor.vv v22, v22, v23
; RV32ZVBC32-NEXT:    vxor.vv v23, v27, v29
; RV32ZVBC32-NEXT:    vand.vv v15, v22, v15
; RV32ZVBC32-NEXT:    vxor.vv v22, v23, v28
; RV32ZVBC32-NEXT:    vmul.vv v23, v18, v19
; RV32ZVBC32-NEXT:    vmul.vv v27, v20, v13
; RV32ZVBC32-NEXT:    vand.vv v16, v22, v16
; RV32ZVBC32-NEXT:    vmul.vv v22, v26, v17
; RV32ZVBC32-NEXT:    vor.vv v15, v16, v15
; RV32ZVBC32-NEXT:    vxor.vv v16, v27, v23
; RV32ZVBC32-NEXT:    vmul.vv v13, v18, v13
; RV32ZVBC32-NEXT:    vmul.vv v18, v20, v25
; RV32ZVBC32-NEXT:    vxor.vv v16, v16, v22
; RV32ZVBC32-NEXT:    vmul.vv v20, v14, v25
; RV32ZVBC32-NEXT:    vmul.vv v19, v26, v19
; RV32ZVBC32-NEXT:    vxor.vv v13, v18, v13
; RV32ZVBC32-NEXT:    vmul.vv v14, v14, v17
; RV32ZVBC32-NEXT:    vxor.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vxor.vv v13, v13, v19
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vxor.vv v13, v13, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v16
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v21
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vsrl.vx v14, v13, a1
; RV32ZVBC32-NEXT:    vsrl.vx v15, v13, a0
; RV32ZVBC32-NEXT:    vand.vx v14, v14, a2
; RV32ZVBC32-NEXT:    vsrl.vi v16, v13, 24
; RV32ZVBC32-NEXT:    vsrl.vi v17, v13, 8
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC32-NEXT:    vand.vv v17, v17, v10
; RV32ZVBC32-NEXT:    vor.vv v14, v14, v15
; RV32ZVBC32-NEXT:    vor.vv v15, v17, v16
; RV32ZVBC32-NEXT:    vand.vv v10, v13, v10
; RV32ZVBC32-NEXT:    vand.vx v16, v13, a3
; RV32ZVBC32-NEXT:    vsll.vi v10, v10, 8
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 24
; RV32ZVBC32-NEXT:    vand.vx v17, v13, a2
; RV32ZVBC32-NEXT:    vsll.vx v13, v13, a0
; RV32ZVBC32-NEXT:    vsll.vx v17, v17, a1
; RV32ZVBC32-NEXT:    vor.vv v10, v16, v10
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v17
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v14
; RV32ZVBC32-NEXT:    vor.vv v10, v13, v10
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v14
; RV32ZVBC32-NEXT:    vsrl.vi v13, v10, 4
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v9
; RV32ZVBC32-NEXT:    vand.vv v9, v13, v9
; RV32ZVBC32-NEXT:    vsll.vi v10, v10, 4
; RV32ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v11
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v11
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 1
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v12
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV32ZVBC32-NEXT:    addi sp, sp, 16
; RV32ZVBC32-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i64_vv_mask:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    li a0, 56
; RV64ZVBC32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
; RV64ZVBC32-NEXT:    vsrl.vx v10, v9, a0
; RV64ZVBC32-NEXT:    li a1, 40
; RV64ZVBC32-NEXT:    vsrl.vx v11, v9, a1
; RV64ZVBC32-NEXT:    lui a2, 16
; RV64ZVBC32-NEXT:    vsrl.vi v12, v9, 24
; RV64ZVBC32-NEXT:    addi a2, a2, -256
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a2
; RV64ZVBC32-NEXT:    vsrl.vi v13, v9, 8
; RV64ZVBC32-NEXT:    lui a3, 4080
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV64ZVBC32-NEXT:    li a4, 255
; RV64ZVBC32-NEXT:    slli a4, a4, 24
; RV64ZVBC32-NEXT:    vand.vx v13, v13, a4
; RV64ZVBC32-NEXT:    vor.vv v10, v11, v10
; RV64ZVBC32-NEXT:    vor.vv v11, v13, v12
; RV64ZVBC32-NEXT:    vand.vx v12, v9, a3
; RV64ZVBC32-NEXT:    vand.vx v13, v9, a4
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 24
; RV64ZVBC32-NEXT:    vsll.vi v13, v13, 8
; RV64ZVBC32-NEXT:    vand.vx v14, v9, a2
; RV64ZVBC32-NEXT:    vsll.vx v9, v9, a0
; RV64ZVBC32-NEXT:    vsll.vx v14, v14, a1
; RV64ZVBC32-NEXT:    vor.vv v12, v12, v13
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v14
; RV64ZVBC32-NEXT:    vor.vv v10, v11, v10
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v12
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV64ZVBC32-NEXT:    lui a5, 61681
; RV64ZVBC32-NEXT:    addi a5, a5, -241
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 4
; RV64ZVBC32-NEXT:    slli a6, a5, 32
; RV64ZVBC32-NEXT:    add a5, a5, a6
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a5
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a5
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 4
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV64ZVBC32-NEXT:    lui a6, 209715
; RV64ZVBC32-NEXT:    addi a6, a6, 819
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vsrl.vx v11, v8, a1
; RV64ZVBC32-NEXT:    vsrl.vx v12, v8, a0
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a2
; RV64ZVBC32-NEXT:    vsrl.vi v13, v8, 24
; RV64ZVBC32-NEXT:    vsrl.vi v14, v8, 8
; RV64ZVBC32-NEXT:    vand.vx v13, v13, a3
; RV64ZVBC32-NEXT:    vand.vx v14, v14, a4
; RV64ZVBC32-NEXT:    vor.vv v11, v11, v12
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v13
; RV64ZVBC32-NEXT:    vand.vx v13, v8, a3
; RV64ZVBC32-NEXT:    vand.vx v14, v8, a4
; RV64ZVBC32-NEXT:    vsll.vi v13, v13, 24
; RV64ZVBC32-NEXT:    vsll.vi v14, v14, 8
; RV64ZVBC32-NEXT:    vand.vx v15, v8, a2
; RV64ZVBC32-NEXT:    vsll.vx v16, v8, a0
; RV64ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV64ZVBC32-NEXT:    vor.vv v13, v13, v14
; RV64ZVBC32-NEXT:    vor.vv v14, v16, v15
; RV64ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v13
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV64ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v11, 4
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a5
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a5
; RV64ZVBC32-NEXT:    vsll.vi v11, v11, 4
; RV64ZVBC32-NEXT:    vsrl.vi v12, v9, 1
; RV64ZVBC32-NEXT:    lui a7, 349525
; RV64ZVBC32-NEXT:    addi a7, a7, 1365
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    vor.vv v10, v10, v11
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v11, v12, a7
; RV64ZVBC32-NEXT:    vsrl.vi v12, v10, 2
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a6
; RV64ZVBC32-NEXT:    vsll.vi v10, v10, 2
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV64ZVBC32-NEXT:    vsrl.vi v12, v10, 1
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a7
; RV64ZVBC32-NEXT:    vadd.vv v10, v10, v10
; RV64ZVBC32-NEXT:    lui t0, 69905
; RV64ZVBC32-NEXT:    vor.vv v9, v11, v9
; RV64ZVBC32-NEXT:    addi t0, t0, 273
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v10
; RV64ZVBC32-NEXT:    lui t2, 139810
; RV64ZVBC32-NEXT:    add t1, t0, t1
; RV64ZVBC32-NEXT:    addi t0, t2, 546
; RV64ZVBC32-NEXT:    vand.vx v11, v9, t1
; RV64ZVBC32-NEXT:    slli t2, t0, 32
; RV64ZVBC32-NEXT:    add t2, t0, t2
; RV64ZVBC32-NEXT:    vand.vx v12, v10, t2
; RV64ZVBC32-NEXT:    vand.vx v13, v9, t2
; RV64ZVBC32-NEXT:    vand.vx v14, v10, t1
; RV64ZVBC32-NEXT:    lui t0, %hi(.LCPI44_0)
; RV64ZVBC32-NEXT:    vmul.vv v15, v12, v11
; RV64ZVBC32-NEXT:    ld t0, %lo(.LCPI44_0)(t0)
; RV64ZVBC32-NEXT:    vmul.vv v16, v14, v13
; RV64ZVBC32-NEXT:    lui t3, 279620
; RV64ZVBC32-NEXT:    addi t3, t3, 1092
; RV64ZVBC32-NEXT:    vand.vx v17, v9, t0
; RV64ZVBC32-NEXT:    slli t4, t3, 32
; RV64ZVBC32-NEXT:    add t3, t3, t4
; RV64ZVBC32-NEXT:    vand.vx v18, v10, t3
; RV64ZVBC32-NEXT:    vxor.vv v15, v16, v15
; RV64ZVBC32-NEXT:    vmul.vv v16, v18, v17
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t3
; RV64ZVBC32-NEXT:    vand.vx v10, v10, t0
; RV64ZVBC32-NEXT:    vmul.vv v19, v12, v17
; RV64ZVBC32-NEXT:    vmul.vv v20, v14, v11
; RV64ZVBC32-NEXT:    vxor.vv v15, v15, v16
; RV64ZVBC32-NEXT:    vmul.vv v16, v10, v9
; RV64ZVBC32-NEXT:    vmul.vv v21, v18, v9
; RV64ZVBC32-NEXT:    vxor.vv v19, v20, v19
; RV64ZVBC32-NEXT:    vmul.vv v20, v10, v13
; RV64ZVBC32-NEXT:    vxor.vv v15, v15, v16
; RV64ZVBC32-NEXT:    vxor.vv v16, v19, v21
; RV64ZVBC32-NEXT:    vand.vx v15, v15, t2
; RV64ZVBC32-NEXT:    vxor.vv v16, v16, v20
; RV64ZVBC32-NEXT:    vmul.vv v19, v12, v13
; RV64ZVBC32-NEXT:    vmul.vv v20, v14, v9
; RV64ZVBC32-NEXT:    vand.vx v16, v16, t1
; RV64ZVBC32-NEXT:    vmul.vv v21, v18, v11
; RV64ZVBC32-NEXT:    vor.vv v15, v16, v15
; RV64ZVBC32-NEXT:    vxor.vv v16, v20, v19
; RV64ZVBC32-NEXT:    vmul.vv v9, v12, v9
; RV64ZVBC32-NEXT:    vmul.vv v12, v14, v17
; RV64ZVBC32-NEXT:    vxor.vv v14, v16, v21
; RV64ZVBC32-NEXT:    vmul.vv v16, v10, v17
; RV64ZVBC32-NEXT:    vmul.vv v13, v18, v13
; RV64ZVBC32-NEXT:    vxor.vv v9, v12, v9
; RV64ZVBC32-NEXT:    vmul.vv v10, v10, v11
; RV64ZVBC32-NEXT:    vxor.vv v11, v14, v16
; RV64ZVBC32-NEXT:    vxor.vv v9, v9, v13
; RV64ZVBC32-NEXT:    vand.vx v11, v11, t3
; RV64ZVBC32-NEXT:    vxor.vv v9, v9, v10
; RV64ZVBC32-NEXT:    vor.vv v10, v15, v11
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t0
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vx v10, v9, a1
; RV64ZVBC32-NEXT:    vsrl.vx v11, v9, a0
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a2
; RV64ZVBC32-NEXT:    vsrl.vi v12, v9, 24
; RV64ZVBC32-NEXT:    vsrl.vi v13, v9, 8
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a3
; RV64ZVBC32-NEXT:    vand.vx v13, v13, a4
; RV64ZVBC32-NEXT:    vor.vv v10, v10, v11
; RV64ZVBC32-NEXT:    vor.vv v11, v13, v12
; RV64ZVBC32-NEXT:    vand.vx v12, v9, a4
; RV64ZVBC32-NEXT:    vand.vx v13, v9, a3
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV64ZVBC32-NEXT:    vsll.vi v13, v13, 24
; RV64ZVBC32-NEXT:    vand.vx v14, v9, a2
; RV64ZVBC32-NEXT:    vsll.vx v9, v9, a0
; RV64ZVBC32-NEXT:    vsll.vx v14, v14, a1
; RV64ZVBC32-NEXT:    vor.vv v12, v13, v12
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v14
; RV64ZVBC32-NEXT:    vor.vv v10, v11, v10
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v12
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 4
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a5
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a5
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 4
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 1
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV64ZVBC32-NEXT:    ret
  %va.ext = zext <vscale x 1 x i64> %va to <vscale x 1 x i128>
  %vb.ext = zext <vscale x 1 x i64> %vb to <vscale x 1 x i128>
  %clmul = call <vscale x 1 x i128> @llvm.clmul.nxv1i128(<vscale x 1 x i128> %va.ext, <vscale x 1 x i128> %vb.ext)
  %res.ext = lshr <vscale x 1 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 1 x i128> %res.ext to <vscale x 1 x i64>
  %sel = select <vscale x 1 x i1> %mask, <vscale x 1 x i64> %res, <vscale x 1 x i64> %va
  ret <vscale x 1 x i64> %sel
}

define <vscale x 1 x i64> @clmulh_nxv1i64_vx_mask(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %mask) {
; RV32V-LABEL: clmulh_nxv1i64_vx_mask:
; RV32V:       # %bb.0:
; RV32V-NEXT:    addi sp, sp, -16
; RV32V-NEXT:    .cfi_def_cfa_offset 16
; RV32V-NEXT:    sw a0, 0(sp)
; RV32V-NEXT:    sw a1, 4(sp)
; RV32V-NEXT:    mv a0, sp
; RV32V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32V-NEXT:    vlse64.v v10, (a0), zero
; RV32V-NEXT:    li a0, 56
; RV32V-NEXT:    vsrl.vx v11, v10, a0
; RV32V-NEXT:    li a1, 40
; RV32V-NEXT:    vsrl.vx v12, v10, a1
; RV32V-NEXT:    lui a3, 1044480
; RV32V-NEXT:    vsrl.vi v13, v10, 24
; RV32V-NEXT:    lui a2, 16
; RV32V-NEXT:    addi a4, sp, 8
; RV32V-NEXT:    addi a2, a2, -256
; RV32V-NEXT:    vsrl.vi v14, v10, 8
; RV32V-NEXT:    sw a3, 8(sp)
; RV32V-NEXT:    sw zero, 12(sp)
; RV32V-NEXT:    vlse64.v v9, (a4), zero
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    lui a3, 4080
; RV32V-NEXT:    vand.vx v13, v13, a3
; RV32V-NEXT:    vand.vv v14, v14, v9
; RV32V-NEXT:    vor.vv v11, v12, v11
; RV32V-NEXT:    vor.vv v12, v14, v13
; RV32V-NEXT:    vand.vv v13, v10, v9
; RV32V-NEXT:    vand.vx v14, v10, a3
; RV32V-NEXT:    vsll.vi v13, v13, 8
; RV32V-NEXT:    vsll.vi v14, v14, 24
; RV32V-NEXT:    vand.vx v15, v10, a2
; RV32V-NEXT:    vsll.vx v10, v10, a0
; RV32V-NEXT:    vsll.vx v15, v15, a1
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vor.vv v10, v10, v15
; RV32V-NEXT:    vor.vv v11, v12, v11
; RV32V-NEXT:    vor.vv v10, v10, v13
; RV32V-NEXT:    vor.vv v11, v10, v11
; RV32V-NEXT:    lui a4, 61681
; RV32V-NEXT:    addi a4, a4, -241
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v10, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v12, v11, 4
; RV32V-NEXT:    vand.vv v11, v11, v10
; RV32V-NEXT:    vand.vv v12, v12, v10
; RV32V-NEXT:    vsll.vi v11, v11, 4
; RV32V-NEXT:    vor.vv v12, v12, v11
; RV32V-NEXT:    lui a4, 209715
; RV32V-NEXT:    addi a4, a4, 819
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v11, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v13, v12, 2
; RV32V-NEXT:    vand.vv v12, v12, v11
; RV32V-NEXT:    vand.vv v13, v13, v11
; RV32V-NEXT:    vsll.vi v12, v12, 2
; RV32V-NEXT:    vor.vv v13, v13, v12
; RV32V-NEXT:    vsrl.vx v12, v8, a1
; RV32V-NEXT:    vsrl.vx v14, v8, a0
; RV32V-NEXT:    vand.vx v12, v12, a2
; RV32V-NEXT:    vsrl.vi v15, v8, 24
; RV32V-NEXT:    vsrl.vi v16, v8, 8
; RV32V-NEXT:    vand.vx v15, v15, a3
; RV32V-NEXT:    vand.vv v16, v16, v9
; RV32V-NEXT:    vor.vv v12, v12, v14
; RV32V-NEXT:    vor.vv v14, v16, v15
; RV32V-NEXT:    vand.vx v15, v8, a2
; RV32V-NEXT:    vsll.vx v16, v8, a0
; RV32V-NEXT:    vsll.vx v15, v15, a1
; RV32V-NEXT:    vand.vx v17, v8, a3
; RV32V-NEXT:    vand.vv v18, v8, v9
; RV32V-NEXT:    vsll.vi v17, v17, 24
; RV32V-NEXT:    vsll.vi v18, v18, 8
; RV32V-NEXT:    vor.vv v15, v16, v15
; RV32V-NEXT:    vor.vv v16, v17, v18
; RV32V-NEXT:    vor.vv v12, v14, v12
; RV32V-NEXT:    vor.vv v14, v15, v16
; RV32V-NEXT:    vsrl.vi v15, v13, 1
; RV32V-NEXT:    lui a4, 349525
; RV32V-NEXT:    vor.vv v14, v14, v12
; RV32V-NEXT:    addi a4, a4, 1365
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v12, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vsrl.vi v16, v14, 4
; RV32V-NEXT:    vand.vv v14, v14, v10
; RV32V-NEXT:    vand.vv v16, v16, v10
; RV32V-NEXT:    vsll.vi v14, v14, 4
; RV32V-NEXT:    vand.vv v15, v15, v12
; RV32V-NEXT:    vor.vv v14, v16, v14
; RV32V-NEXT:    vand.vv v13, v13, v12
; RV32V-NEXT:    vsrl.vi v16, v14, 2
; RV32V-NEXT:    vand.vv v14, v14, v11
; RV32V-NEXT:    vand.vv v16, v16, v11
; RV32V-NEXT:    vsll.vi v14, v14, 2
; RV32V-NEXT:    vadd.vv v13, v13, v13
; RV32V-NEXT:    vor.vv v14, v16, v14
; RV32V-NEXT:    vor.vv v13, v15, v13
; RV32V-NEXT:    vsrl.vi v15, v14, 1
; RV32V-NEXT:    vand.vv v14, v14, v12
; RV32V-NEXT:    vand.vv v15, v15, v12
; RV32V-NEXT:    lui a4, 69905
; RV32V-NEXT:    vadd.vv v14, v14, v14
; RV32V-NEXT:    addi a4, a4, 273
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v16, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    lui a4, 139810
; RV32V-NEXT:    addi a4, a4, 546
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v15, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vand.vv v17, v13, v16
; RV32V-NEXT:    vand.vv v18, v14, v15
; RV32V-NEXT:    vand.vv v19, v13, v15
; RV32V-NEXT:    vand.vv v20, v14, v16
; RV32V-NEXT:    lui a4, 559241
; RV32V-NEXT:    addi a4, a4, -1912
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v21, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32V-NEXT:    vmul.vv v22, v18, v17
; RV32V-NEXT:    lui a4, 279620
; RV32V-NEXT:    vmul.vv v23, v20, v19
; RV32V-NEXT:    addi a4, a4, 1092
; RV32V-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32V-NEXT:    vmv.v.x v24, a4
; RV32V-NEXT:    vsetvli a4, zero, e64, m1, ta, mu
; RV32V-NEXT:    vand.vv v25, v13, v21
; RV32V-NEXT:    vand.vv v26, v14, v24
; RV32V-NEXT:    vxor.vv v22, v23, v22
; RV32V-NEXT:    vmul.vv v23, v26, v25
; RV32V-NEXT:    vand.vv v13, v13, v24
; RV32V-NEXT:    vand.vv v14, v14, v21
; RV32V-NEXT:    vmul.vv v27, v18, v25
; RV32V-NEXT:    vmul.vv v28, v20, v17
; RV32V-NEXT:    vxor.vv v22, v22, v23
; RV32V-NEXT:    vmul.vv v23, v14, v13
; RV32V-NEXT:    vmul.vv v29, v26, v13
; RV32V-NEXT:    vxor.vv v27, v28, v27
; RV32V-NEXT:    vmul.vv v28, v14, v19
; RV32V-NEXT:    vxor.vv v22, v22, v23
; RV32V-NEXT:    vxor.vv v23, v27, v29
; RV32V-NEXT:    vand.vv v15, v22, v15
; RV32V-NEXT:    vxor.vv v22, v23, v28
; RV32V-NEXT:    vmul.vv v23, v18, v19
; RV32V-NEXT:    vmul.vv v27, v20, v13
; RV32V-NEXT:    vand.vv v16, v22, v16
; RV32V-NEXT:    vmul.vv v22, v26, v17
; RV32V-NEXT:    vor.vv v15, v16, v15
; RV32V-NEXT:    vxor.vv v16, v27, v23
; RV32V-NEXT:    vmul.vv v13, v18, v13
; RV32V-NEXT:    vmul.vv v18, v20, v25
; RV32V-NEXT:    vxor.vv v16, v16, v22
; RV32V-NEXT:    vmul.vv v20, v14, v25
; RV32V-NEXT:    vmul.vv v19, v26, v19
; RV32V-NEXT:    vxor.vv v13, v18, v13
; RV32V-NEXT:    vmul.vv v14, v14, v17
; RV32V-NEXT:    vxor.vv v16, v16, v20
; RV32V-NEXT:    vxor.vv v13, v13, v19
; RV32V-NEXT:    vand.vv v16, v16, v24
; RV32V-NEXT:    vxor.vv v13, v13, v14
; RV32V-NEXT:    vor.vv v14, v15, v16
; RV32V-NEXT:    vand.vv v13, v13, v21
; RV32V-NEXT:    vor.vv v13, v14, v13
; RV32V-NEXT:    vsrl.vx v14, v13, a1
; RV32V-NEXT:    vsrl.vx v15, v13, a0
; RV32V-NEXT:    vand.vx v14, v14, a2
; RV32V-NEXT:    vsrl.vi v16, v13, 24
; RV32V-NEXT:    vsrl.vi v17, v13, 8
; RV32V-NEXT:    vand.vx v16, v16, a3
; RV32V-NEXT:    vand.vv v17, v17, v9
; RV32V-NEXT:    vor.vv v14, v14, v15
; RV32V-NEXT:    vor.vv v15, v17, v16
; RV32V-NEXT:    vand.vv v9, v13, v9
; RV32V-NEXT:    vand.vx v16, v13, a3
; RV32V-NEXT:    vsll.vi v9, v9, 8
; RV32V-NEXT:    vsll.vi v16, v16, 24
; RV32V-NEXT:    vand.vx v17, v13, a2
; RV32V-NEXT:    vsll.vx v13, v13, a0
; RV32V-NEXT:    vsll.vx v17, v17, a1
; RV32V-NEXT:    vor.vv v9, v16, v9
; RV32V-NEXT:    vor.vv v13, v13, v17
; RV32V-NEXT:    vor.vv v14, v15, v14
; RV32V-NEXT:    vor.vv v9, v13, v9
; RV32V-NEXT:    vor.vv v9, v9, v14
; RV32V-NEXT:    vsrl.vi v13, v9, 4
; RV32V-NEXT:    vand.vv v9, v9, v10
; RV32V-NEXT:    vand.vv v10, v13, v10
; RV32V-NEXT:    vsll.vi v9, v9, 4
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v10, v9, 2
; RV32V-NEXT:    vand.vv v9, v9, v11
; RV32V-NEXT:    vand.vv v10, v10, v11
; RV32V-NEXT:    vsll.vi v9, v9, 2
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v10, v9, 1
; RV32V-NEXT:    vand.vv v9, v9, v12
; RV32V-NEXT:    vand.vv v10, v10, v12
; RV32V-NEXT:    vadd.vv v9, v9, v9
; RV32V-NEXT:    vor.vv v9, v10, v9
; RV32V-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV32V-NEXT:    addi sp, sp, 16
; RV32V-NEXT:    .cfi_def_cfa_offset 0
; RV32V-NEXT:    ret
;
; RV64V-LABEL: clmulh_nxv1i64_vx_mask:
; RV64V:       # %bb.0:
; RV64V-NEXT:    addi sp, sp, -16
; RV64V-NEXT:    .cfi_def_cfa_offset 16
; RV64V-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64V-NEXT:    .cfi_offset s0, -8
; RV64V-NEXT:    li a1, 56
; RV64V-NEXT:    vsetvli a2, zero, e64, m1, ta, mu
; RV64V-NEXT:    vsrl.vx v9, v8, a1
; RV64V-NEXT:    li a2, 40
; RV64V-NEXT:    vsrl.vx v10, v8, a2
; RV64V-NEXT:    lui a3, 16
; RV64V-NEXT:    vsrl.vi v11, v8, 24
; RV64V-NEXT:    addi a3, a3, -256
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vsrl.vi v12, v8, 8
; RV64V-NEXT:    lui a4, 4080
; RV64V-NEXT:    vand.vx v11, v11, a4
; RV64V-NEXT:    li a5, 255
; RV64V-NEXT:    slli a5, a5, 24
; RV64V-NEXT:    vand.vx v12, v12, a5
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vor.vv v10, v12, v11
; RV64V-NEXT:    vand.vx v11, v8, a4
; RV64V-NEXT:    vand.vx v12, v8, a5
; RV64V-NEXT:    vsll.vi v11, v11, 24
; RV64V-NEXT:    vsll.vi v12, v12, 8
; RV64V-NEXT:    vand.vx v13, v8, a3
; RV64V-NEXT:    vsll.vx v14, v8, a1
; RV64V-NEXT:    vsll.vx v13, v13, a2
; RV64V-NEXT:    vor.vv v11, v11, v12
; RV64V-NEXT:    vor.vv v12, v14, v13
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vor.vv v10, v12, v11
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    lui a6, 61681
; RV64V-NEXT:    addi a6, a6, -241
; RV64V-NEXT:    vsrl.vi v10, v9, 4
; RV64V-NEXT:    slli a7, a6, 32
; RV64V-NEXT:    add a6, a6, a7
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vsll.vi v9, v9, 4
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    lui a7, 209715
; RV64V-NEXT:    addi a7, a7, 819
; RV64V-NEXT:    vsrl.vi v10, v9, 2
; RV64V-NEXT:    slli t0, a7, 32
; RV64V-NEXT:    add a7, a7, t0
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vsll.vi v9, v9, 2
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    lui t0, 349525
; RV64V-NEXT:    addi t0, t0, 1365
; RV64V-NEXT:    vsrl.vi v10, v9, 1
; RV64V-NEXT:    slli t1, t0, 32
; RV64V-NEXT:    add t0, t0, t1
; RV64V-NEXT:    vand.vx v9, v9, t0
; RV64V-NEXT:    vand.vx v10, v10, t0
; RV64V-NEXT:    vadd.vv v9, v9, v9
; RV64V-NEXT:    lui t1, 139810
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    addi t1, t1, 546
; RV64V-NEXT:    srli t2, a0, 24
; RV64V-NEXT:    srli t3, a0, 8
; RV64V-NEXT:    and t2, t2, a4
; RV64V-NEXT:    and t3, t3, a5
; RV64V-NEXT:    or t2, t3, t2
; RV64V-NEXT:    srli t3, a0, 40
; RV64V-NEXT:    and t3, t3, a3
; RV64V-NEXT:    srli t4, a0, 56
; RV64V-NEXT:    or t3, t3, t4
; RV64V-NEXT:    and t4, a0, a4
; RV64V-NEXT:    slli t4, t4, 24
; RV64V-NEXT:    srliw t5, a0, 24
; RV64V-NEXT:    slli t5, t5, 32
; RV64V-NEXT:    and t6, a0, a3
; RV64V-NEXT:    slli t6, t6, 40
; RV64V-NEXT:    slli a0, a0, 56
; RV64V-NEXT:    or t4, t4, t5
; RV64V-NEXT:    or a0, a0, t6
; RV64V-NEXT:    or t2, t2, t3
; RV64V-NEXT:    or a0, a0, t4
; RV64V-NEXT:    slli t3, t1, 32
; RV64V-NEXT:    or a0, a0, t2
; RV64V-NEXT:    srli t2, a0, 4
; RV64V-NEXT:    and a0, a0, a6
; RV64V-NEXT:    and t2, t2, a6
; RV64V-NEXT:    slli t4, a0, 4
; RV64V-NEXT:    add a0, t1, t3
; RV64V-NEXT:    or t1, t2, t4
; RV64V-NEXT:    srli t2, t1, 2
; RV64V-NEXT:    and t1, t1, a7
; RV64V-NEXT:    and t2, t2, a7
; RV64V-NEXT:    slli t1, t1, 2
; RV64V-NEXT:    vand.vx v10, v9, a0
; RV64V-NEXT:    or t1, t2, t1
; RV64V-NEXT:    srli t2, t1, 1
; RV64V-NEXT:    lui t3, 69905
; RV64V-NEXT:    and t2, t2, t0
; RV64V-NEXT:    addi t3, t3, 273
; RV64V-NEXT:    and t1, t1, t0
; RV64V-NEXT:    slli t4, t3, 32
; RV64V-NEXT:    slli t1, t1, 1
; RV64V-NEXT:    add t3, t3, t4
; RV64V-NEXT:    or t2, t2, t1
; RV64V-NEXT:    vand.vx v11, v9, t3
; RV64V-NEXT:    and t1, t2, t3
; RV64V-NEXT:    vmul.vx v12, v10, t1
; RV64V-NEXT:    and t4, t2, a0
; RV64V-NEXT:    lui t5, 279620
; RV64V-NEXT:    vmul.vx v13, v11, t4
; RV64V-NEXT:    addi t5, t5, 1092
; RV64V-NEXT:    slli t6, t5, 32
; RV64V-NEXT:    lui s0, %hi(.LCPI45_0)
; RV64V-NEXT:    add t5, t5, t6
; RV64V-NEXT:    ld t6, %lo(.LCPI45_0)(s0)
; RV64V-NEXT:    vand.vx v14, v9, t5
; RV64V-NEXT:    and s0, t2, t6
; RV64V-NEXT:    vmul.vx v15, v14, s0
; RV64V-NEXT:    vxor.vv v12, v13, v12
; RV64V-NEXT:    vand.vx v9, v9, t6
; RV64V-NEXT:    vmul.vx v13, v10, s0
; RV64V-NEXT:    vmul.vx v16, v11, t1
; RV64V-NEXT:    vxor.vv v12, v12, v15
; RV64V-NEXT:    and t2, t2, t5
; RV64V-NEXT:    vmul.vx v15, v9, t2
; RV64V-NEXT:    vmul.vx v17, v14, t2
; RV64V-NEXT:    vxor.vv v13, v16, v13
; RV64V-NEXT:    vmul.vx v16, v9, t4
; RV64V-NEXT:    vxor.vv v12, v12, v15
; RV64V-NEXT:    vxor.vv v13, v13, v17
; RV64V-NEXT:    vand.vx v12, v12, a0
; RV64V-NEXT:    vxor.vv v13, v13, v16
; RV64V-NEXT:    vmul.vx v15, v10, t4
; RV64V-NEXT:    vmul.vx v16, v11, t2
; RV64V-NEXT:    vand.vx v13, v13, t3
; RV64V-NEXT:    vmul.vx v17, v14, t1
; RV64V-NEXT:    vor.vv v12, v13, v12
; RV64V-NEXT:    vxor.vv v13, v16, v15
; RV64V-NEXT:    vmul.vx v10, v10, t2
; RV64V-NEXT:    vmul.vx v11, v11, s0
; RV64V-NEXT:    vxor.vv v13, v13, v17
; RV64V-NEXT:    vmul.vx v15, v9, s0
; RV64V-NEXT:    vmul.vx v14, v14, t4
; RV64V-NEXT:    vxor.vv v10, v11, v10
; RV64V-NEXT:    vmul.vx v9, v9, t1
; RV64V-NEXT:    vxor.vv v11, v13, v15
; RV64V-NEXT:    vxor.vv v10, v10, v14
; RV64V-NEXT:    vand.vx v11, v11, t5
; RV64V-NEXT:    vxor.vv v9, v10, v9
; RV64V-NEXT:    vor.vv v10, v12, v11
; RV64V-NEXT:    vand.vx v9, v9, t6
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vx v10, v9, a2
; RV64V-NEXT:    vsrl.vx v11, v9, a1
; RV64V-NEXT:    vand.vx v10, v10, a3
; RV64V-NEXT:    vsrl.vi v12, v9, 24
; RV64V-NEXT:    vsrl.vi v13, v9, 8
; RV64V-NEXT:    vand.vx v12, v12, a4
; RV64V-NEXT:    vand.vx v13, v13, a5
; RV64V-NEXT:    vor.vv v10, v10, v11
; RV64V-NEXT:    vor.vv v11, v13, v12
; RV64V-NEXT:    vand.vx v12, v9, a5
; RV64V-NEXT:    vand.vx v13, v9, a4
; RV64V-NEXT:    vsll.vi v12, v12, 8
; RV64V-NEXT:    vsll.vi v13, v13, 24
; RV64V-NEXT:    vand.vx v14, v9, a3
; RV64V-NEXT:    vsll.vx v9, v9, a1
; RV64V-NEXT:    vsll.vx v14, v14, a2
; RV64V-NEXT:    vor.vv v12, v13, v12
; RV64V-NEXT:    vor.vv v9, v9, v14
; RV64V-NEXT:    vor.vv v10, v11, v10
; RV64V-NEXT:    vor.vv v9, v9, v12
; RV64V-NEXT:    vor.vv v9, v9, v10
; RV64V-NEXT:    vsrl.vi v10, v9, 4
; RV64V-NEXT:    vand.vx v9, v9, a6
; RV64V-NEXT:    vand.vx v10, v10, a6
; RV64V-NEXT:    vsll.vi v9, v9, 4
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v9, 2
; RV64V-NEXT:    vand.vx v9, v9, a7
; RV64V-NEXT:    vand.vx v10, v10, a7
; RV64V-NEXT:    vsll.vi v9, v9, 2
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v10, v9, 1
; RV64V-NEXT:    vand.vx v9, v9, t0
; RV64V-NEXT:    vand.vx v10, v10, t0
; RV64V-NEXT:    vadd.vv v9, v9, v9
; RV64V-NEXT:    vor.vv v9, v10, v9
; RV64V-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV64V-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64V-NEXT:    .cfi_restore s0
; RV64V-NEXT:    addi sp, sp, 16
; RV64V-NEXT:    .cfi_def_cfa_offset 0
; RV64V-NEXT:    ret
;
; RV32ZVBC64-LABEL: clmulh_nxv1i64_vx_mask:
; RV32ZVBC64:       # %bb.0:
; RV32ZVBC64-NEXT:    addi sp, sp, -16
; RV32ZVBC64-NEXT:    .cfi_def_cfa_offset 16
; RV32ZVBC64-NEXT:    sw a0, 8(sp)
; RV32ZVBC64-NEXT:    sw a1, 12(sp)
; RV32ZVBC64-NEXT:    addi a0, sp, 8
; RV32ZVBC64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
; RV32ZVBC64-NEXT:    vlse64.v v9, (a0), zero
; RV32ZVBC64-NEXT:    vclmulh.vv v8, v8, v9, v0.t
; RV32ZVBC64-NEXT:    addi sp, sp, 16
; RV32ZVBC64-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVBC64-NEXT:    ret
;
; RV64ZVBC64-LABEL: clmulh_nxv1i64_vx_mask:
; RV64ZVBC64:       # %bb.0:
; RV64ZVBC64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
; RV64ZVBC64-NEXT:    vclmulh.vx v8, v8, a0, v0.t
; RV64ZVBC64-NEXT:    ret
;
; RV32ZVBC32-LABEL: clmulh_nxv1i64_vx_mask:
; RV32ZVBC32:       # %bb.0:
; RV32ZVBC32-NEXT:    addi sp, sp, -16
; RV32ZVBC32-NEXT:    .cfi_def_cfa_offset 16
; RV32ZVBC32-NEXT:    sw a0, 0(sp)
; RV32ZVBC32-NEXT:    sw a1, 4(sp)
; RV32ZVBC32-NEXT:    mv a0, sp
; RV32ZVBC32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vlse64.v v10, (a0), zero
; RV32ZVBC32-NEXT:    li a0, 56
; RV32ZVBC32-NEXT:    vsrl.vx v11, v10, a0
; RV32ZVBC32-NEXT:    li a1, 40
; RV32ZVBC32-NEXT:    vsrl.vx v12, v10, a1
; RV32ZVBC32-NEXT:    lui a3, 1044480
; RV32ZVBC32-NEXT:    vsrl.vi v13, v10, 24
; RV32ZVBC32-NEXT:    lui a2, 16
; RV32ZVBC32-NEXT:    addi a4, sp, 8
; RV32ZVBC32-NEXT:    addi a2, a2, -256
; RV32ZVBC32-NEXT:    vsrl.vi v14, v10, 8
; RV32ZVBC32-NEXT:    sw a3, 8(sp)
; RV32ZVBC32-NEXT:    sw zero, 12(sp)
; RV32ZVBC32-NEXT:    vlse64.v v9, (a4), zero
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    lui a3, 4080
; RV32ZVBC32-NEXT:    vand.vx v13, v13, a3
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v9
; RV32ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v13
; RV32ZVBC32-NEXT:    vand.vv v13, v10, v9
; RV32ZVBC32-NEXT:    vand.vx v14, v10, a3
; RV32ZVBC32-NEXT:    vsll.vi v13, v13, 8
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 24
; RV32ZVBC32-NEXT:    vand.vx v15, v10, a2
; RV32ZVBC32-NEXT:    vsll.vx v10, v10, a0
; RV32ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v15
; RV32ZVBC32-NEXT:    vor.vv v11, v12, v11
; RV32ZVBC32-NEXT:    vor.vv v10, v10, v13
; RV32ZVBC32-NEXT:    vor.vv v11, v10, v11
; RV32ZVBC32-NEXT:    lui a4, 61681
; RV32ZVBC32-NEXT:    addi a4, a4, -241
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v10, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v12, v11, 4
; RV32ZVBC32-NEXT:    vand.vv v11, v11, v10
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v10
; RV32ZVBC32-NEXT:    vsll.vi v11, v11, 4
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v11
; RV32ZVBC32-NEXT:    lui a4, 209715
; RV32ZVBC32-NEXT:    addi a4, a4, 819
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v11, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v13, v12, 2
; RV32ZVBC32-NEXT:    vand.vv v12, v12, v11
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v11
; RV32ZVBC32-NEXT:    vsll.vi v12, v12, 2
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vx v12, v8, a1
; RV32ZVBC32-NEXT:    vsrl.vx v14, v8, a0
; RV32ZVBC32-NEXT:    vand.vx v12, v12, a2
; RV32ZVBC32-NEXT:    vsrl.vi v15, v8, 24
; RV32ZVBC32-NEXT:    vsrl.vi v16, v8, 8
; RV32ZVBC32-NEXT:    vand.vx v15, v15, a3
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v9
; RV32ZVBC32-NEXT:    vor.vv v12, v12, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v15
; RV32ZVBC32-NEXT:    vand.vx v15, v8, a2
; RV32ZVBC32-NEXT:    vsll.vx v16, v8, a0
; RV32ZVBC32-NEXT:    vsll.vx v15, v15, a1
; RV32ZVBC32-NEXT:    vand.vx v17, v8, a3
; RV32ZVBC32-NEXT:    vand.vv v18, v8, v9
; RV32ZVBC32-NEXT:    vsll.vi v17, v17, 24
; RV32ZVBC32-NEXT:    vsll.vi v18, v18, 8
; RV32ZVBC32-NEXT:    vor.vv v15, v16, v15
; RV32ZVBC32-NEXT:    vor.vv v16, v17, v18
; RV32ZVBC32-NEXT:    vor.vv v12, v14, v12
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v16
; RV32ZVBC32-NEXT:    vsrl.vi v15, v13, 1
; RV32ZVBC32-NEXT:    lui a4, 349525
; RV32ZVBC32-NEXT:    vor.vv v14, v14, v12
; RV32ZVBC32-NEXT:    addi a4, a4, 1365
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v12, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vsrl.vi v16, v14, 4
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v10
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v10
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 4
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v12
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v12
; RV32ZVBC32-NEXT:    vsrl.vi v16, v14, 2
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v11
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v11
; RV32ZVBC32-NEXT:    vsll.vi v14, v14, 2
; RV32ZVBC32-NEXT:    vadd.vv v13, v13, v13
; RV32ZVBC32-NEXT:    vor.vv v14, v16, v14
; RV32ZVBC32-NEXT:    vor.vv v13, v15, v13
; RV32ZVBC32-NEXT:    vsrl.vi v15, v14, 1
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v12
; RV32ZVBC32-NEXT:    vand.vv v15, v15, v12
; RV32ZVBC32-NEXT:    lui a4, 69905
; RV32ZVBC32-NEXT:    vadd.vv v14, v14, v14
; RV32ZVBC32-NEXT:    addi a4, a4, 273
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v16, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v14
; RV32ZVBC32-NEXT:    lui a4, 139810
; RV32ZVBC32-NEXT:    addi a4, a4, 546
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v15, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vand.vv v17, v13, v16
; RV32ZVBC32-NEXT:    vand.vv v18, v14, v15
; RV32ZVBC32-NEXT:    vand.vv v19, v13, v15
; RV32ZVBC32-NEXT:    vand.vv v20, v14, v16
; RV32ZVBC32-NEXT:    lui a4, 559241
; RV32ZVBC32-NEXT:    addi a4, a4, -1912
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v21, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, ma
; RV32ZVBC32-NEXT:    vmul.vv v22, v18, v17
; RV32ZVBC32-NEXT:    lui a4, 279620
; RV32ZVBC32-NEXT:    vmul.vv v23, v20, v19
; RV32ZVBC32-NEXT:    addi a4, a4, 1092
; RV32ZVBC32-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; RV32ZVBC32-NEXT:    vmv.v.x v24, a4
; RV32ZVBC32-NEXT:    vsetvli a4, zero, e64, m1, ta, mu
; RV32ZVBC32-NEXT:    vand.vv v25, v13, v21
; RV32ZVBC32-NEXT:    vand.vv v26, v14, v24
; RV32ZVBC32-NEXT:    vxor.vv v22, v23, v22
; RV32ZVBC32-NEXT:    vmul.vv v23, v26, v25
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v24
; RV32ZVBC32-NEXT:    vand.vv v14, v14, v21
; RV32ZVBC32-NEXT:    vmul.vv v27, v18, v25
; RV32ZVBC32-NEXT:    vmul.vv v28, v20, v17
; RV32ZVBC32-NEXT:    vxor.vv v22, v22, v23
; RV32ZVBC32-NEXT:    vmul.vv v23, v14, v13
; RV32ZVBC32-NEXT:    vmul.vv v29, v26, v13
; RV32ZVBC32-NEXT:    vxor.vv v27, v28, v27
; RV32ZVBC32-NEXT:    vmul.vv v28, v14, v19
; RV32ZVBC32-NEXT:    vxor.vv v22, v22, v23
; RV32ZVBC32-NEXT:    vxor.vv v23, v27, v29
; RV32ZVBC32-NEXT:    vand.vv v15, v22, v15
; RV32ZVBC32-NEXT:    vxor.vv v22, v23, v28
; RV32ZVBC32-NEXT:    vmul.vv v23, v18, v19
; RV32ZVBC32-NEXT:    vmul.vv v27, v20, v13
; RV32ZVBC32-NEXT:    vand.vv v16, v22, v16
; RV32ZVBC32-NEXT:    vmul.vv v22, v26, v17
; RV32ZVBC32-NEXT:    vor.vv v15, v16, v15
; RV32ZVBC32-NEXT:    vxor.vv v16, v27, v23
; RV32ZVBC32-NEXT:    vmul.vv v13, v18, v13
; RV32ZVBC32-NEXT:    vmul.vv v18, v20, v25
; RV32ZVBC32-NEXT:    vxor.vv v16, v16, v22
; RV32ZVBC32-NEXT:    vmul.vv v20, v14, v25
; RV32ZVBC32-NEXT:    vmul.vv v19, v26, v19
; RV32ZVBC32-NEXT:    vxor.vv v13, v18, v13
; RV32ZVBC32-NEXT:    vmul.vv v14, v14, v17
; RV32ZVBC32-NEXT:    vxor.vv v16, v16, v20
; RV32ZVBC32-NEXT:    vxor.vv v13, v13, v19
; RV32ZVBC32-NEXT:    vand.vv v16, v16, v24
; RV32ZVBC32-NEXT:    vxor.vv v13, v13, v14
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v16
; RV32ZVBC32-NEXT:    vand.vv v13, v13, v21
; RV32ZVBC32-NEXT:    vor.vv v13, v14, v13
; RV32ZVBC32-NEXT:    vsrl.vx v14, v13, a1
; RV32ZVBC32-NEXT:    vsrl.vx v15, v13, a0
; RV32ZVBC32-NEXT:    vand.vx v14, v14, a2
; RV32ZVBC32-NEXT:    vsrl.vi v16, v13, 24
; RV32ZVBC32-NEXT:    vsrl.vi v17, v13, 8
; RV32ZVBC32-NEXT:    vand.vx v16, v16, a3
; RV32ZVBC32-NEXT:    vand.vv v17, v17, v9
; RV32ZVBC32-NEXT:    vor.vv v14, v14, v15
; RV32ZVBC32-NEXT:    vor.vv v15, v17, v16
; RV32ZVBC32-NEXT:    vand.vv v9, v13, v9
; RV32ZVBC32-NEXT:    vand.vx v16, v13, a3
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 8
; RV32ZVBC32-NEXT:    vsll.vi v16, v16, 24
; RV32ZVBC32-NEXT:    vand.vx v17, v13, a2
; RV32ZVBC32-NEXT:    vsll.vx v13, v13, a0
; RV32ZVBC32-NEXT:    vsll.vx v17, v17, a1
; RV32ZVBC32-NEXT:    vor.vv v9, v16, v9
; RV32ZVBC32-NEXT:    vor.vv v13, v13, v17
; RV32ZVBC32-NEXT:    vor.vv v14, v15, v14
; RV32ZVBC32-NEXT:    vor.vv v9, v13, v9
; RV32ZVBC32-NEXT:    vor.vv v9, v9, v14
; RV32ZVBC32-NEXT:    vsrl.vi v13, v9, 4
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v10
; RV32ZVBC32-NEXT:    vand.vv v10, v13, v10
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 4
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v11
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v11
; RV32ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v10, v9, 1
; RV32ZVBC32-NEXT:    vand.vv v9, v9, v12
; RV32ZVBC32-NEXT:    vand.vv v10, v10, v12
; RV32ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV32ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV32ZVBC32-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV32ZVBC32-NEXT:    addi sp, sp, 16
; RV32ZVBC32-NEXT:    .cfi_def_cfa_offset 0
; RV32ZVBC32-NEXT:    ret
;
; RV64ZVBC32-LABEL: clmulh_nxv1i64_vx_mask:
; RV64ZVBC32:       # %bb.0:
; RV64ZVBC32-NEXT:    addi sp, sp, -16
; RV64ZVBC32-NEXT:    .cfi_def_cfa_offset 16
; RV64ZVBC32-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64ZVBC32-NEXT:    .cfi_offset s0, -8
; RV64ZVBC32-NEXT:    li a1, 56
; RV64ZVBC32-NEXT:    vsetvli a2, zero, e64, m1, ta, mu
; RV64ZVBC32-NEXT:    vsrl.vx v9, v8, a1
; RV64ZVBC32-NEXT:    li a2, 40
; RV64ZVBC32-NEXT:    vsrl.vx v10, v8, a2
; RV64ZVBC32-NEXT:    lui a3, 16
; RV64ZVBC32-NEXT:    vsrl.vi v11, v8, 24
; RV64ZVBC32-NEXT:    addi a3, a3, -256
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a3
; RV64ZVBC32-NEXT:    vsrl.vi v12, v8, 8
; RV64ZVBC32-NEXT:    lui a4, 4080
; RV64ZVBC32-NEXT:    vand.vx v11, v11, a4
; RV64ZVBC32-NEXT:    li a5, 255
; RV64ZVBC32-NEXT:    slli a5, a5, 24
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a5
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v11
; RV64ZVBC32-NEXT:    vand.vx v11, v8, a4
; RV64ZVBC32-NEXT:    vand.vx v12, v8, a5
; RV64ZVBC32-NEXT:    vsll.vi v11, v11, 24
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV64ZVBC32-NEXT:    vand.vx v13, v8, a3
; RV64ZVBC32-NEXT:    vsll.vx v14, v8, a1
; RV64ZVBC32-NEXT:    vsll.vx v13, v13, a2
; RV64ZVBC32-NEXT:    vor.vv v11, v11, v12
; RV64ZVBC32-NEXT:    vor.vv v12, v14, v13
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v11
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    lui a6, 61681
; RV64ZVBC32-NEXT:    addi a6, a6, -241
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 4
; RV64ZVBC32-NEXT:    slli a7, a6, 32
; RV64ZVBC32-NEXT:    add a6, a6, a7
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 4
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    lui a7, 209715
; RV64ZVBC32-NEXT:    addi a7, a7, 819
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV64ZVBC32-NEXT:    slli t0, a7, 32
; RV64ZVBC32-NEXT:    add a7, a7, t0
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    lui t0, 349525
; RV64ZVBC32-NEXT:    addi t0, t0, 1365
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 1
; RV64ZVBC32-NEXT:    slli t1, t0, 32
; RV64ZVBC32-NEXT:    add t0, t0, t1
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t0
; RV64ZVBC32-NEXT:    vand.vx v10, v10, t0
; RV64ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV64ZVBC32-NEXT:    lui t1, 139810
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    addi t1, t1, 546
; RV64ZVBC32-NEXT:    srli t2, a0, 24
; RV64ZVBC32-NEXT:    srli t3, a0, 8
; RV64ZVBC32-NEXT:    and t2, t2, a4
; RV64ZVBC32-NEXT:    and t3, t3, a5
; RV64ZVBC32-NEXT:    or t2, t3, t2
; RV64ZVBC32-NEXT:    srli t3, a0, 40
; RV64ZVBC32-NEXT:    and t3, t3, a3
; RV64ZVBC32-NEXT:    srli t4, a0, 56
; RV64ZVBC32-NEXT:    or t3, t3, t4
; RV64ZVBC32-NEXT:    and t4, a0, a4
; RV64ZVBC32-NEXT:    slli t4, t4, 24
; RV64ZVBC32-NEXT:    srliw t5, a0, 24
; RV64ZVBC32-NEXT:    slli t5, t5, 32
; RV64ZVBC32-NEXT:    and t6, a0, a3
; RV64ZVBC32-NEXT:    slli t6, t6, 40
; RV64ZVBC32-NEXT:    slli a0, a0, 56
; RV64ZVBC32-NEXT:    or t4, t4, t5
; RV64ZVBC32-NEXT:    or a0, a0, t6
; RV64ZVBC32-NEXT:    or t2, t2, t3
; RV64ZVBC32-NEXT:    or a0, a0, t4
; RV64ZVBC32-NEXT:    slli t3, t1, 32
; RV64ZVBC32-NEXT:    or a0, a0, t2
; RV64ZVBC32-NEXT:    srli t2, a0, 4
; RV64ZVBC32-NEXT:    and a0, a0, a6
; RV64ZVBC32-NEXT:    and t2, t2, a6
; RV64ZVBC32-NEXT:    slli t4, a0, 4
; RV64ZVBC32-NEXT:    add a0, t1, t3
; RV64ZVBC32-NEXT:    or t1, t2, t4
; RV64ZVBC32-NEXT:    srli t2, t1, 2
; RV64ZVBC32-NEXT:    and t1, t1, a7
; RV64ZVBC32-NEXT:    and t2, t2, a7
; RV64ZVBC32-NEXT:    slli t1, t1, 2
; RV64ZVBC32-NEXT:    vand.vx v10, v9, a0
; RV64ZVBC32-NEXT:    or t1, t2, t1
; RV64ZVBC32-NEXT:    srli t2, t1, 1
; RV64ZVBC32-NEXT:    lui t3, 69905
; RV64ZVBC32-NEXT:    and t2, t2, t0
; RV64ZVBC32-NEXT:    addi t3, t3, 273
; RV64ZVBC32-NEXT:    and t1, t1, t0
; RV64ZVBC32-NEXT:    slli t4, t3, 32
; RV64ZVBC32-NEXT:    slli t1, t1, 1
; RV64ZVBC32-NEXT:    add t3, t3, t4
; RV64ZVBC32-NEXT:    or t2, t2, t1
; RV64ZVBC32-NEXT:    vand.vx v11, v9, t3
; RV64ZVBC32-NEXT:    and t1, t2, t3
; RV64ZVBC32-NEXT:    vmul.vx v12, v10, t1
; RV64ZVBC32-NEXT:    and t4, t2, a0
; RV64ZVBC32-NEXT:    lui t5, 279620
; RV64ZVBC32-NEXT:    vmul.vx v13, v11, t4
; RV64ZVBC32-NEXT:    addi t5, t5, 1092
; RV64ZVBC32-NEXT:    slli t6, t5, 32
; RV64ZVBC32-NEXT:    lui s0, %hi(.LCPI45_0)
; RV64ZVBC32-NEXT:    add t5, t5, t6
; RV64ZVBC32-NEXT:    ld t6, %lo(.LCPI45_0)(s0)
; RV64ZVBC32-NEXT:    vand.vx v14, v9, t5
; RV64ZVBC32-NEXT:    and s0, t2, t6
; RV64ZVBC32-NEXT:    vmul.vx v15, v14, s0
; RV64ZVBC32-NEXT:    vxor.vv v12, v13, v12
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t6
; RV64ZVBC32-NEXT:    vmul.vx v13, v10, s0
; RV64ZVBC32-NEXT:    vmul.vx v16, v11, t1
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v15
; RV64ZVBC32-NEXT:    and t2, t2, t5
; RV64ZVBC32-NEXT:    vmul.vx v15, v9, t2
; RV64ZVBC32-NEXT:    vmul.vx v17, v14, t2
; RV64ZVBC32-NEXT:    vxor.vv v13, v16, v13
; RV64ZVBC32-NEXT:    vmul.vx v16, v9, t4
; RV64ZVBC32-NEXT:    vxor.vv v12, v12, v15
; RV64ZVBC32-NEXT:    vxor.vv v13, v13, v17
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a0
; RV64ZVBC32-NEXT:    vxor.vv v13, v13, v16
; RV64ZVBC32-NEXT:    vmul.vx v15, v10, t4
; RV64ZVBC32-NEXT:    vmul.vx v16, v11, t2
; RV64ZVBC32-NEXT:    vand.vx v13, v13, t3
; RV64ZVBC32-NEXT:    vmul.vx v17, v14, t1
; RV64ZVBC32-NEXT:    vor.vv v12, v13, v12
; RV64ZVBC32-NEXT:    vxor.vv v13, v16, v15
; RV64ZVBC32-NEXT:    vmul.vx v10, v10, t2
; RV64ZVBC32-NEXT:    vmul.vx v11, v11, s0
; RV64ZVBC32-NEXT:    vxor.vv v13, v13, v17
; RV64ZVBC32-NEXT:    vmul.vx v15, v9, s0
; RV64ZVBC32-NEXT:    vmul.vx v14, v14, t4
; RV64ZVBC32-NEXT:    vxor.vv v10, v11, v10
; RV64ZVBC32-NEXT:    vmul.vx v9, v9, t1
; RV64ZVBC32-NEXT:    vxor.vv v11, v13, v15
; RV64ZVBC32-NEXT:    vxor.vv v10, v10, v14
; RV64ZVBC32-NEXT:    vand.vx v11, v11, t5
; RV64ZVBC32-NEXT:    vxor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vor.vv v10, v12, v11
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t6
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vx v10, v9, a2
; RV64ZVBC32-NEXT:    vsrl.vx v11, v9, a1
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a3
; RV64ZVBC32-NEXT:    vsrl.vi v12, v9, 24
; RV64ZVBC32-NEXT:    vsrl.vi v13, v9, 8
; RV64ZVBC32-NEXT:    vand.vx v12, v12, a4
; RV64ZVBC32-NEXT:    vand.vx v13, v13, a5
; RV64ZVBC32-NEXT:    vor.vv v10, v10, v11
; RV64ZVBC32-NEXT:    vor.vv v11, v13, v12
; RV64ZVBC32-NEXT:    vand.vx v12, v9, a5
; RV64ZVBC32-NEXT:    vand.vx v13, v9, a4
; RV64ZVBC32-NEXT:    vsll.vi v12, v12, 8
; RV64ZVBC32-NEXT:    vsll.vi v13, v13, 24
; RV64ZVBC32-NEXT:    vand.vx v14, v9, a3
; RV64ZVBC32-NEXT:    vsll.vx v9, v9, a1
; RV64ZVBC32-NEXT:    vsll.vx v14, v14, a2
; RV64ZVBC32-NEXT:    vor.vv v12, v13, v12
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v14
; RV64ZVBC32-NEXT:    vor.vv v10, v11, v10
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v12
; RV64ZVBC32-NEXT:    vor.vv v9, v9, v10
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 4
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a6
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a6
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 4
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 2
; RV64ZVBC32-NEXT:    vand.vx v9, v9, a7
; RV64ZVBC32-NEXT:    vand.vx v10, v10, a7
; RV64ZVBC32-NEXT:    vsll.vi v9, v9, 2
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v10, v9, 1
; RV64ZVBC32-NEXT:    vand.vx v9, v9, t0
; RV64ZVBC32-NEXT:    vand.vx v10, v10, t0
; RV64ZVBC32-NEXT:    vadd.vv v9, v9, v9
; RV64ZVBC32-NEXT:    vor.vv v9, v10, v9
; RV64ZVBC32-NEXT:    vsrl.vi v8, v9, 1, v0.t
; RV64ZVBC32-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64ZVBC32-NEXT:    .cfi_restore s0
; RV64ZVBC32-NEXT:    addi sp, sp, 16
; RV64ZVBC32-NEXT:    .cfi_def_cfa_offset 0
; RV64ZVBC32-NEXT:    ret
  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i128 0
  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
  %va.ext = zext <vscale x 1 x i64> %va to <vscale x 1 x i128>
  %vb.ext = zext <vscale x 1 x i64> %vb to <vscale x 1 x i128>
  %clmul = call <vscale x 1 x i128> @llvm.clmul.nxv1i128(<vscale x 1 x i128> %va.ext, <vscale x 1 x i128> %vb.ext)
  %res.ext = lshr <vscale x 1 x i128> %clmul, splat(i128 64)
  %res = trunc <vscale x 1 x i128> %res.ext to <vscale x 1 x i64>
  %sel = select <vscale x 1 x i1> %mask, <vscale x 1 x i64> %res, <vscale x 1 x i64> %va
  ret <vscale x 1 x i64> %sel
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}
; RV32: {{.*}}
; RV32ZVBC: {{.*}}
; RV64: {{.*}}
; RV64ZVBC: {{.*}}