llvm/test/CodeGen/RISCV/rvp-bitreverse-zbkb.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb,+zbkb \
; RUN:   -verify-machineinstrs < %s | \
; RUN:   FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb,+zbkb \
; RUN:   -verify-machineinstrs < %s | \
; RUN:   FileCheck %s --check-prefixes=CHECK,RV64

; With Zbkb, a per-byte-lane bitreverse (v4i8/v8i8) selects a single brev8
; instead of rev+rev8. Halfword/word lanes still need the rev-based sequence.

define <4 x i8> @test_bitreverse_v4i8(<4 x i8> %a) {
; CHECK-LABEL: test_bitreverse_v4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    brev8 a0, a0
; CHECK-NEXT:    ret
  %res = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %a)
  ret <4 x i8> %res
}

define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) {
; RV32-LABEL: test_bitreverse_v2i16:
; RV32:       # %bb.0:
; RV32-NEXT:    rev a0, a0
; RV32-NEXT:    ppairoe.h a0, a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_bitreverse_v2i16:
; RV64:       # %bb.0:
; RV64-NEXT:    rev a0, a0
; RV64-NEXT:    rev16 a0, a0
; RV64-NEXT:    ret
  %res = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
  ret <2 x i16> %res
}

define <8 x i8> @test_bitreverse_v8i8(<8 x i8> %a) {
; RV32-LABEL: test_bitreverse_v8i8:
; RV32:       # %bb.0:
; RV32-NEXT:    brev8 a1, a1
; RV32-NEXT:    brev8 a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_bitreverse_v8i8:
; RV64:       # %bb.0:
; RV64-NEXT:    brev8 a0, a0
; RV64-NEXT:    ret
  %res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)
  ret <8 x i8> %res
}

define <4 x i16> @test_bitreverse_v4i16(<4 x i16> %a) {
; RV32-LABEL: test_bitreverse_v4i16:
; RV32:       # %bb.0:
; RV32-NEXT:    rev a1, a1
; RV32-NEXT:    rev a0, a0
; RV32-NEXT:    ppairoe.dh a0, a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_bitreverse_v4i16:
; RV64:       # %bb.0:
; RV64-NEXT:    rev a0, a0
; RV64-NEXT:    rev16 a0, a0
; RV64-NEXT:    ret
  %res = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %a)
  ret <4 x i16> %res
}

define <2 x i32> @test_bitreverse_v2i32(<2 x i32> %a) {
; RV32-LABEL: test_bitreverse_v2i32:
; RV32:       # %bb.0:
; RV32-NEXT:    rev a1, a1
; RV32-NEXT:    rev a0, a0
; RV32-NEXT:    ret
;
; RV64-LABEL: test_bitreverse_v2i32:
; RV64:       # %bb.0:
; RV64-NEXT:    rev a0, a0
; RV64-NEXT:    ppairoe.w a0, a0, a0
; RV64-NEXT:    ret
  %res = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
  ret <2 x i32> %res
}