llvm/test/CodeGen/M68k/Arith/rem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s

; Remainder is expected to lower to DIV -> SWAP

define zeroext i16 @test1(i16 zeroext %a, i16 zeroext %b) nounwind {
; CHECK-LABEL: test1:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    move.w (6,%sp), %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    clr.w %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    move.w (10,%sp), %d1
; CHECK-NEXT:    divu %d1, %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    clr.w %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    rts
entry:
	%rem = urem i16 %a, %b
	ret i16 %rem
}

define zeroext i16 @test2(i16 zeroext %a, i16 zeroext %b) nounwind {
; CHECK-LABEL: test2:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    move.w (6,%sp), %d0
; CHECK-NEXT:    ext.l %d0
; CHECK-NEXT:    move.w (10,%sp), %d1
; CHECK-NEXT:    divs %d1, %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    clr.w %d0
; CHECK-NEXT:    swap %d0
; CHECK-NEXT:    rts
entry:
	%rem = srem i16 %a, %b
	ret i16 %rem
}

define zeroext i8 @test3(i8 zeroext %a, i8 zeroext %b) nounwind {
; CHECK-LABEL: test3:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    move.b (11,%sp), %d0
; CHECK-NEXT:    and.w #255, %d0
; CHECK-NEXT:    move.b (7,%sp), %d1
; CHECK-NEXT:    and.l #255, %d1
; CHECK-NEXT:    divu %d0, %d1
; CHECK-NEXT:    swap %d1
; CHECK-NEXT:    moveq #0, %d0
; CHECK-NEXT:    move.b %d1, %d0
; CHECK-NEXT:    rts
entry:
	%rem = urem i8 %a, %b
	ret i8 %rem
}

define zeroext i8 @test4(i8 zeroext %a, i8 zeroext %b) nounwind {
; CHECK-LABEL: test4:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    move.b (11,%sp), %d0
; CHECK-NEXT:    ext.w %d0
; CHECK-NEXT:    move.b (7,%sp), %d1
; CHECK-NEXT:    ext.w %d1
; CHECK-NEXT:    ext.l %d1
; CHECK-NEXT:    divs %d0, %d1
; CHECK-NEXT:    swap %d1
; CHECK-NEXT:    moveq #0, %d0
; CHECK-NEXT:    move.b %d1, %d0
; CHECK-NEXT:    rts
entry:
	%rem = srem i8 %a, %b
	ret i8 %rem
}