llvm/test/CodeGen/AMDGPU/wqm-debug-instr-terminator.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu10.10 -run-pass si-wqm -o - %s | FileCheck %s

# Regression test for the toExact() crash with debug instructions (PR #189370).
#
# In a non-entry block that starts in WQM (WQMFromExec=false), a
# StrictWQM->Exact transition has SaveSCC=false, so prepareInsertion()
# returns the raw First iterator without resolving it through SlotIndexes.
# If consecutive debug instructions sit right after the StrictWQM
# instruction, FirstStrict points to the first one.  The second consecutive
# DBG_VALUE is needed because getInstructionIndex uses getBundleEnd (= next
# instruction) as the skip limit; with two consecutive debug instructions
# the skip lands on the second debug instruction and the assertion
# !BundleNonDebug.isDebugInstr() fires inside toExact's call to
# getInstructionIndex(*Before).

--- |
  define amdgpu_ps void @wqm_debug_strict_to_exact() !dbg !4 {
  entry:
    br label %body, !dbg !10
  body:
    ret void, !dbg !10
  }

  !llvm.dbg.cu = !{!0}
  !llvm.module.flags = !{!1, !2}
  !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "test", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
  !1 = !{i32 7, !"Dwarf Version", i32 4}
  !2 = !{i32 2, !"Debug Info Version", i32 3}
  !3 = !DIFile(filename: "test.hlsl", directory: "/tmp")
  !4 = distinct !DISubprogram(name: "wqm_debug_strict_to_exact", scope: !3, file: !3, line: 1, type: !5, scopeLine: 1, unit: !0)
  !5 = !DISubroutineType(types: !{null})
  !7 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
  !8 = !DILocalVariable(name: "v", scope: !4, file: !3, line: 2, type: !7)
  !10 = !DILocation(line: 2, scope: !4)
...
---

---
name: wqm_debug_strict_to_exact
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: wqm_debug_strict_to_exact
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $vgpr0, $vgpr1, $m0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $exec_lo
  ; CHECK-NEXT:   $exec_lo = S_WQM_B32 $exec_lo, implicit-def $scc
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   S_BRANCH %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.body:
  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $m0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[ENTER_STRICT_WQM:%[0-9]+]]:sreg_32 = ENTER_STRICT_WQM -1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; CHECK-NEXT:   [[DS_PARAM_LOAD:%[0-9]+]]:vgpr_32 = DS_PARAM_LOAD 0, 0, 0, 1, implicit $m0, implicit $exec
  ; CHECK-NEXT:   $exec_lo = EXIT_STRICT_WQM [[ENTER_STRICT_WQM]]
  ; CHECK-NEXT:   DBG_VALUE $noreg, $noreg
  ; CHECK-NEXT:   DBG_VALUE $noreg, $noreg
  ; CHECK-NEXT:   [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_AND_SAVEEXEC_B32 [[COPY]], implicit-def $exec, implicit-def $scc, implicit $exec
  ; CHECK-NEXT:   BUFFER_STORE_DWORD_OFFSET_exact [[DS_PARAM_LOAD]], [[DEF1]], [[DEF2]], 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   $exec_lo = COPY [[S_AND_SAVEEXEC_B32_]]
  ; CHECK-NEXT:   undef [[COPY3:%[0-9]+]].sub0:vreg_64 = COPY [[DS_PARAM_LOAD]]
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]].sub1:vreg_64 = COPY [[COPY2]]
  ; CHECK-NEXT:   $exec_lo = S_AND_B32 $exec_lo, [[COPY]], implicit-def $scc
  ; CHECK-NEXT:   [[IMAGE_SAMPLE_V4_V2_:%[0-9]+]]:vreg_128 = IMAGE_SAMPLE_V4_V2 [[COPY3]], [[DEF]], [[DEF1]], 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8)
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.3, implicit $exec
  ; CHECK-NEXT:   S_BRANCH %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   EXP_DONE 0, [[IMAGE_SAMPLE_V4_V2_]].sub0, [[IMAGE_SAMPLE_V4_V2_]].sub1, [[IMAGE_SAMPLE_V4_V2_]].sub2, [[IMAGE_SAMPLE_V4_V2_]].sub3, 0, 0, 0, implicit $exec
  ; CHECK-NEXT:   S_ENDPGM 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   $vgpr0 = COPY [[COPY1]]
  ; CHECK-NEXT:   SI_RETURN_TO_EPILOG $vgpr0
  bb.0.entry:
    liveins: $vgpr0, $vgpr1, $m0

    %0:vgpr_32 = COPY $vgpr0
    %1:vgpr_32 = COPY $vgpr1
    %2:sgpr_256 = IMPLICIT_DEF
    %3:sgpr_128 = IMPLICIT_DEF
    %4:sgpr_32 = IMPLICIT_DEF
    S_BRANCH %bb.1

  bb.1.body:
    liveins: $m0

    ; DS_PARAM_LOAD needs StrictWQM; its result feeds IMAGE_SAMPLE (below)
    ; so WQM propagates here, making InNeeds include WQM -> block starts WQM.
    %5:vgpr_32 = DS_PARAM_LOAD 0, 0, 0, 1, implicit $m0, implicit $exec
    ; Two consecutive debug instructions after the StrictWQM instruction.
    ; DS_PARAM_LOAD resets FirstStrict to the block-end sentinel (MBB.end()),
    ; so the first DBG_VALUE becomes FirstStrict.  The second is needed so
    ; getInstructionIndex's bundle-end
    ; skip still lands on a debug instruction, triggering the assertion.
    DBG_VALUE $noreg, $noreg
    DBG_VALUE $noreg, $noreg
    ; BUFFER_STORE_exact has DisableWQM -> Needs = StateExact only.
    ; StrictWQM -> Exact: SaveSCC=false (non-entry, Needs has no Strict/WQM).
    ; prepareInsertion returns First (= first DBG_VALUE) directly.
    ; toExact receives Before = first DBG_VALUE and calls
    ; getInstructionIndex(*Before) which asserts on the debug instruction.
    BUFFER_STORE_DWORD_OFFSET_exact %5, %3, %4, 0, 0, 0, implicit $exec
    ; IMAGE_SAMPLE propagates WQM to its inputs (including DS_PARAM_LOAD),
    ; making this block need WQM -> NonStrictState = WQM -> WQMToExact = true.
    undef %6.sub0:vreg_64 = COPY %5
    %6.sub1:vreg_64 = COPY %1
    %7:vreg_128 = IMAGE_SAMPLE_V4_V2 %6, %2, %3, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 8)
    S_CBRANCH_EXECZ %bb.3, implicit $exec
    S_BRANCH %bb.2

  bb.2:
    EXP_DONE 0, %7.sub0, %7.sub1, %7.sub2, %7.sub3, 0, 0, 0, implicit $exec
    S_ENDPGM 0

  bb.3:
    $vgpr0 = COPY %0
    SI_RETURN_TO_EPILOG $vgpr0

...