llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir

# RUN: llc %s -o - -mtriple=amdgpu10.30-amd-amdpal -O0 -run-pass=si-pre-allocate-wwm-regs | FileCheck %s

# Simple regression test to make sure DBG_VALUE $noreg does not assert in the pass

# CHECK: $vgpr0 = IMPLICIT_DEF
# CHECK: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, $vgpr0

--- |
  %dx.types.ResRet.f32 = type { float, float, float, float, i32 }

  define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg noundef %globalTable, i32 inreg noundef %userdata4, <3 x i32> inreg noundef %WorkgroupId, i32 inreg noundef %MultiDispatchInfo, <3 x i32> noundef %LocalInvocationId) #0 !dbg !5 {
      #dbg_value(i32 poison, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), !20)
      #dbg_value(%dx.types.ResRet.f32 poison, !21, !DIExpression(), !23)
    ret void, !dbg !24
  }

  attributes #0 = { memory(readwrite) "amdgpu-prealloc-sgpr-spill-vgprs" }

  !llvm.dbg.cu = !{!0}
  !llvm.module.flags = !{!3, !4}

  !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "dxcoob 1.7.2308.16 (52da17e29)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, globals: !2)
  !1 = !DIFile(filename: "tests\\basic_var.hlsl", directory: "")
  !2 = !{}
  !3 = !{i32 2, !"Dwarf Version", i32 5}
  !4 = !{i32 2, !"Debug Info Version", i32 3}
  !5 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 7, type: !6, scopeLine: 7, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0)
  !6 = !DISubroutineType(types: !7)
  !7 = !{null, !8}
  !8 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint3", file: !1, baseType: !9)
  !9 = !DICompositeType(tag: DW_TAG_class_type, name: "vector<unsigned int, 3>", file: !1, size: 96, align: 32, elements: !10, templateParams: !15)
  !10 = !{!11, !13, !14}
  !11 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !9, file: !1, baseType: !12, size: 32, align: 32, flags: DIFlagPublic)
  !12 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned)
  !13 = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: !9, file: !1, baseType: !12, size: 32, align: 32, offset: 32, flags: DIFlagPublic)
  !14 = !DIDerivedType(tag: DW_TAG_member, name: "z", scope: !9, file: !1, baseType: !12, size: 32, align: 32, offset: 64, flags: DIFlagPublic)
  !15 = !{!16, !17}
  !16 = !DITemplateTypeParameter(name: "element", type: !12)
  !17 = !DITemplateValueParameter(name: "element_count", type: !18, value: i32 3)
  !18 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
  !19 = !DILocalVariable(name: "dtid", arg: 1, scope: !5, file: !1, line: 7, type: !8)
  !20 = !DILocation(line: 7, column: 17, scope: !5)
  !21 = !DILocalVariable(name: "my_var", scope: !5, file: !1, line: 11, type: !22)
  !22 = !DIBasicType(name: "float", size: 32, align: 32, encoding: DW_ATE_float)
  !23 = !DILocation(line: 11, column: 9, scope: !5)
  !24 = !DILocation(line: 19, column: 1, scope: !5)
...
---
name:            _amdgpu_cs_main
tracksRegLiveness: true
machineFunctionInfo:
  isEntryFunction: true
  hasSpilledSGPRs: true
  stackPtrOffsetReg: '$sgpr32'
  occupancy:       16
  sgprForEXECCopy: '$sgpr12_sgpr13'
body:             |
  bb.0 (%ir-block.0):
    liveins: $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2

    %0:vgpr_32 = IMPLICIT_DEF
    %2:vgpr_32 = IMPLICIT_DEF
    %2:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr3, 0, %2
    renamable $sgpr3 = COPY killed $sgpr2
    renamable $sgpr4 = S_MOV_B32 6
    %3:vgpr_32 = V_LSHL_ADD_U32_e64 killed $sgpr3, killed $sgpr4, %0, implicit $exec
    DBG_VALUE %3, $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32),  debug-location !20
    DBG_VALUE $noreg, $noreg, !21, !DIExpression(),  debug-location !23
    S_ENDPGM 0
...