llvm/test/CodeGen/AMDGPU/iterative-ilp-restore-undef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -run-pass=machine-scheduler -o - %s | FileCheck %s

# Ensure that the scheduler preserves operand liveness and instruction flags
# even if it fails to find a schedule that meets the occupancy requirement.
--- |
  target triple = "amdgpu9.42-amd-amdhsa"

  define amdgpu_kernel void @test() #0 {
    ret void
  }

  attributes #0 = { "amdgpu-sched-strategy"="iterative-ilp" }
...
---
name:            test
tracksRegLiveness: true
machineFunctionInfo:
  occupancy:       4
body:             |
  bb.0:
    ; CHECK-LABEL: name: test
    ; CHECK: dead undef [[DEF:%[0-9]+]].sub0:vreg_64_align2 = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_1024_align2 = COPY [[DEF1]]
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:vreg_1024_align2 = COPY [[DEF2]]
    ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[COPY2:%[0-9]+]]:vreg_1024_align2 = COPY [[DEF3]]
    ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[COPY3:%[0-9]+]]:vreg_1024_align2 = COPY [[DEF4]]
    ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:vreg_1024_align2 = COPY [[DEF5]]
    ; CHECK-NEXT: dead [[S_ADD_U32_:%[0-9]+]]:sreg_32 = nuw S_ADD_U32 0, 1, implicit-def dead $scc
    ; CHECK-NEXT: S_ENDPGM 0
    undef %0.sub0:vreg_64_align2 = IMPLICIT_DEF
    %1:vreg_1024_align2 = IMPLICIT_DEF
    dead %2:vreg_1024_align2 = COPY %1
    %3:vreg_1024_align2 = IMPLICIT_DEF
    dead %4:vreg_1024_align2 = COPY %3
    %5:vreg_1024_align2 = IMPLICIT_DEF
    dead %6:vreg_1024_align2 = COPY %5
    %7:vreg_1024_align2 = IMPLICIT_DEF
    dead %8:vreg_1024_align2 = COPY %7
    %9:vreg_1024_align2 = IMPLICIT_DEF
    dead %10:vreg_1024_align2 = COPY %9
    %11:sreg_32 = nuw S_ADD_U32 0, 1, implicit-def dead $scc
    S_ENDPGM 0
...