llvm/test/CodeGen/AMDGPU/fence-barrier-latency.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa --misched-prera-direction=topdown -o - %s | FileCheck %s

@lds = internal unnamed_addr addrspace(3) global [65536 x i8] poison, align 16

define amdgpu_kernel void @fence_barrier_latency_test(ptr addrspace(1) %global_ptr, i32 %offset, <8 x i32> %tdesc, <4 x i32> %src_desc) #0 {
; CHECK-LABEL: fence_barrier_latency_test:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_clause 0x2
; CHECK-NEXT:    s_load_b128 s[0:3], s[4:5], 0x40 nv
; CHECK-NEXT:    s_load_b96 s[16:18], s[4:5], 0x0 nv
; CHECK-NEXT:    s_load_b256 s[8:15], s[4:5], 0x20 nv
; CHECK-NEXT:    s_wait_kmcnt 0x0
; CHECK-NEXT:    v_dual_mov_b32 v32, 0 :: v_dual_mov_b32 v28, s18
; CHECK-NEXT:    tensor_load_to_lds s[0:3], s[8:15]
; CHECK-NEXT:    s_barrier_signal -1
; CHECK-NEXT:    s_barrier_wait -1
; CHECK-NEXT:    ds_load_b128 v[0:3], v28
; CHECK-NEXT:    ds_load_b128 v[4:7], v28 offset:32
; CHECK-NEXT:    ds_load_b128 v[8:11], v28 offset:64
; CHECK-NEXT:    ds_load_b128 v[12:15], v28 offset:96
; CHECK-NEXT:    ds_load_b128 v[16:19], v28 offset:128
; CHECK-NEXT:    ds_load_b128 v[20:23], v28 offset:160
; CHECK-NEXT:    ds_load_b128 v[24:27], v28 offset:192
; CHECK-NEXT:    ds_load_b128 v[28:31], v28 offset:224
; CHECK-NEXT:    s_wait_dscnt 0x7
; CHECK-NEXT:    v_readfirstlane_b32 s4, v3
; CHECK-NEXT:    s_wait_dscnt 0x6
; CHECK-NEXT:    v_readfirstlane_b32 s5, v7
; CHECK-NEXT:    v_readfirstlane_b32 s6, v6
; CHECK-NEXT:    v_readfirstlane_b32 s7, v2
; CHECK-NEXT:    v_readfirstlane_b32 s18, v5
; CHECK-NEXT:    v_readfirstlane_b32 s19, v1
; CHECK-NEXT:    v_readfirstlane_b32 s20, v4
; CHECK-NEXT:    v_readfirstlane_b32 s21, v0
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_wait_dscnt 0x0
; CHECK-NEXT:    s_barrier_signal -1
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_barrier_wait -1
; CHECK-NEXT:    tensor_load_to_lds s[0:3], s[8:15]
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    v_dual_add_nc_u32 v0, v11, v15 :: v_dual_add_nc_u32 v1, v10, v14
; CHECK-NEXT:    v_dual_add_nc_u32 v2, v9, v13 :: v_dual_add_nc_u32 v3, v8, v12
; CHECK-NEXT:    v_dual_add_nc_u32 v4, v19, v23 :: v_dual_add_nc_u32 v5, v18, v22
; CHECK-NEXT:    v_dual_add_nc_u32 v6, v17, v21 :: v_dual_add_nc_u32 v7, v16, v20
; CHECK-NEXT:    v_dual_add_nc_u32 v8, v27, v31 :: v_dual_add_nc_u32 v9, v26, v30
; CHECK-NEXT:    v_dual_add_nc_u32 v10, v25, v29 :: v_dual_add_nc_u32 v11, v24, v28
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s7, s7, s6
; CHECK-NEXT:    s_add_co_i32 s4, s4, s5
; CHECK-NEXT:    s_add_co_i32 s19, s19, s18
; CHECK-NEXT:    s_add_co_i32 s21, s21, s20
; CHECK-NEXT:    v_dual_add_nc_u32 v2, s19, v2 :: v_dual_add_nc_u32 v3, s21, v3
; CHECK-NEXT:    v_dual_add_nc_u32 v12, s7, v1 :: v_dual_add_nc_u32 v13, s4, v0
; CHECK-NEXT:    v_dual_add_nc_u32 v0, v7, v11 :: v_dual_add_nc_u32 v1, v6, v10
; CHECK-NEXT:    v_dual_add_nc_u32 v5, v5, v9 :: v_dual_add_nc_u32 v4, v4, v8
; CHECK-NEXT:    v_dual_add_nc_u32 v0, v3, v0 :: v_dual_add_nc_u32 v1, v2, v1
; CHECK-NEXT:    v_dual_add_nc_u32 v2, v12, v5 :: v_dual_add_nc_u32 v3, v13, v4
; CHECK-NEXT:    global_store_b128 v32, v[0:3], s[16:17]
; CHECK-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %src_desc, <8 x i32> %tdesc, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  fence syncscope("workgroup") release
  tail call void @llvm.amdgcn.s.barrier()
  fence syncscope("workgroup") acquire
  %lds_base = getelementptr i8, ptr addrspace(3) @lds, i32 %offset
  %ptr0 = getelementptr i8, ptr addrspace(3) %lds_base, i32 0
  %v0 = load <4 x i32>, ptr addrspace(3) %ptr0, align 16
  %ptr1 = getelementptr i8, ptr addrspace(3) %lds_base, i32 32
  %v1 = load <4 x i32>, ptr addrspace(3) %ptr1, align 16
  %ptr2 = getelementptr i8, ptr addrspace(3) %lds_base, i32 64
  %v2 = load <4 x i32>, ptr addrspace(3) %ptr2, align 16
  %ptr3 = getelementptr i8, ptr addrspace(3) %lds_base, i32 96
  %v3 = load <4 x i32>, ptr addrspace(3) %ptr3, align 16
  %ptr4 = getelementptr i8, ptr addrspace(3) %lds_base, i32 128
  %v4 = load <4 x i32>, ptr addrspace(3) %ptr4, align 16
  %ptr5 = getelementptr i8, ptr addrspace(3) %lds_base, i32 160
  %v5 = load <4 x i32>, ptr addrspace(3) %ptr5, align 16
  %ptr6 = getelementptr i8, ptr addrspace(3) %lds_base, i32 192
  %v6 = load <4 x i32>, ptr addrspace(3) %ptr6, align 16
  %ptr7 = getelementptr i8, ptr addrspace(3) %lds_base, i32 224
  %v7 = load <4 x i32>, ptr addrspace(3) %ptr7, align 16
  %sum01_t0 = add <4 x i32> %v0, %v1
  %sum01_t1 = add <4 x i32> %sum01_t0, %v1
  %sum01_t2 = add <4 x i32> %sum01_t1, %v1
  %sum01_t3 = add <4 x i32> %sum01_t2, %v1
  %sum01_t4 = add <4 x i32> %sum01_t3, %v1
  %sum01_t5 = add <4 x i32> %sum01_t4, %v1
  %sum01_t6 = add <4 x i32> %sum01_t5, %v1
  %sum01_t7 = add <4 x i32> %sum01_t6, %v1
  %sum01_t8 = add <4 x i32> %sum01_t7, %v1
  %sum01_t9 = add <4 x i32> %sum01_t8, %v1
  %sum01 = add <4 x i32> %sum01_t9, %v1
  %sum23 = add <4 x i32> %v2, %v3
  %sum45 = add <4 x i32> %v4, %v5
  %sum67 = add <4 x i32> %v6, %v7
  %sum0123 = add <4 x i32> %sum01, %sum23
  %sum4567 = add <4 x i32> %sum45, %sum67
  %sum_all = add <4 x i32> %sum0123, %sum4567
  fence syncscope("workgroup") release
  tail call void @llvm.amdgcn.s.barrier()
  fence syncscope("workgroup") acquire
  tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %src_desc, <8 x i32> %tdesc, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  store <4 x i32> %sum_all, ptr addrspace(1) %global_ptr, align 16
  ret void
}

declare void @llvm.amdgcn.s.barrier()
declare void @llvm.amdgcn.tensor.load.to.lds(<4 x i32>, <8 x i32>, <4 x i32>, <4 x i32>, <8 x i32>, i32)

attributes #0 = { "amdgpu-flat-work-group-size"="1,128" "amdgpu-waves-per-eu"="1,1" }