llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -o - %s | FileCheck -check-prefix=GFX12 %s

define amdgpu_ps half @fmed3_s16_uniform(half inreg %a, half inreg %b, half inreg %c) {
; GFX9-LABEL: fmed3_s16_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v0, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    v_med3_f16 v0, s0, v0, v1
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: fmed3_s16_uniform:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_med3_num_f16 v0, s0, s1, v0
; GFX12-NEXT:    ; return to shader part epilog
  %result = call half @llvm.amdgcn.fmed3.f16(half %a, half %b, half %c)
  ret half %result
}

define amdgpu_ps half @fmed3_s16_uniform_salu_use(half inreg %a, half inreg %b, half inreg %c, half inreg %d) {
; GFX9-LABEL: fmed3_s16_uniform_salu_use:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v0, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    v_med3_f16 v0, s0, v0, v1
; GFX9-NEXT:    v_add_f16_e32 v0, s3, v0
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: fmed3_s16_uniform_salu_use:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_med3_num_f16 v0, s0, s1, v0
; GFX12-NEXT:    v_readfirstlane_b32 s0, v0
; GFX12-NEXT:    s_add_f16 s0, s0, s3
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-NEXT:    ; return to shader part epilog
  %result = call half @llvm.amdgcn.fmed3.f16(half %a, half %b, half %c)
  %add = fadd half %result, %d
  ret half %add
}

define amdgpu_ps half @fmed3_s16_div(half %a, half %b, half %c) {
; GFX9-LABEL: fmed3_s16_div:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_med3_f16 v0, v0, v1, v2
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: fmed3_s16_div:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_med3_num_f16 v0, v0, v1, v2
; GFX12-NEXT:    ; return to shader part epilog
  %result = call half @llvm.amdgcn.fmed3.f16(half %a, half %b, half %c)
  ret half %result
}

define amdgpu_ps float @fmed3_s32_uniform(float inreg %a, float inreg %b, float inreg %c) {
; GFX9-LABEL: fmed3_s32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v0, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    v_med3_f32 v0, s0, v0, v1
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: fmed3_s32_uniform:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_med3_num_f32 v0, s0, s1, v0
; GFX12-NEXT:    ; return to shader part epilog
  %result = call float @llvm.amdgcn.fmed3.f32(float %a, float %b, float %c)
  ret float %result
}

define amdgpu_ps float @fmed3_s32_uniform_salu_use(float inreg %a, float inreg %b, float inreg %c, float inreg %d) {
; GFX9-LABEL: fmed3_s32_uniform_salu_use:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v0, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    v_med3_f32 v0, s0, v0, v1
; GFX9-NEXT:    v_add_f32_e32 v0, s3, v0
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: fmed3_s32_uniform_salu_use:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_mov_b32_e32 v0, s2
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_med3_num_f32 v0, s0, s1, v0
; GFX12-NEXT:    v_readfirstlane_b32 s0, v0
; GFX12-NEXT:    s_add_f32 s0, s0, s3
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
; GFX12-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-NEXT:    ; return to shader part epilog
  %result = call float @llvm.amdgcn.fmed3.f32(float %a, float %b, float %c)
  %add = fadd float %result, %d
  ret float %add
}

define amdgpu_ps float @fmed3_s32_div(float %a, float %b, float %c) {
; GFX9-LABEL: fmed3_s32_div:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_med3_f32 v0, v0, v1, v2
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX12-LABEL: fmed3_s32_div:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_med3_num_f32 v0, v0, v1, v2
; GFX12-NEXT:    ; return to shader part epilog
  %result = call float @llvm.amdgcn.fmed3.f32(float %a, float %b, float %c)
  ret float %result
}

declare half @llvm.amdgcn.fmed3.f16(half, half, half)
declare float @llvm.amdgcn.fmed3.f32(float, float, float)