llvm/test/CodeGen/AArch64/reduce-load-width-freeze.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin < %s | FileCheck %s

define i32 @and_freeze_load_i32_to_i8(ptr %p) {
; CHECK-LABEL: and_freeze_load_i32_to_i8:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 255
  ret i32 %masked
}

define i32 @and_freeze_load_i32_to_i16(ptr %p) {
; CHECK-LABEL: and_freeze_load_i32_to_i16:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrh w0, [x0]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 65535
  ret i32 %masked
}

define i64 @and_freeze_load_i64_to_i8(ptr %p) {
; CHECK-LABEL: and_freeze_load_i64_to_i8:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %masked = and i64 %freeze, 255
  ret i64 %masked
}

define i64 @and_freeze_load_i64_to_i16(ptr %p) {
; CHECK-LABEL: and_freeze_load_i64_to_i16:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrh w0, [x0]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %masked = and i64 %freeze, 65535
  ret i64 %masked
}

define i64 @and_freeze_load_i64_to_i32(ptr %p) {
; CHECK-LABEL: and_freeze_load_i64_to_i32:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w0, [x0]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %masked = and i64 %freeze, 4294967295
  ret i64 %masked
}

define i32 @and_freeze_load_shifted_mask(ptr %p) {
; CHECK-LABEL: and_freeze_load_shifted_mask:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w8, [x0, #1]
; CHECK-NEXT:    lsl w0, w8, #8
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 65280
  ret i32 %masked
}

define i8 @trunc_freeze_load_i16_to_i8(ptr %p) {
; CHECK-LABEL: trunc_freeze_load_i16_to_i8:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i16, ptr %p, align 2
  %freeze = freeze i16 %load
  %trunc = trunc i16 %freeze to i8
  ret i8 %trunc
}

define i8 @trunc_freeze_load_i32_to_i8(ptr %p) {
; CHECK-LABEL: trunc_freeze_load_i32_to_i8:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w0, [x0]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %trunc = trunc i32 %freeze to i8
  ret i8 %trunc
}

define i8 @trunc_freeze_load_i64_to_i8(ptr %p) {
; CHECK-LABEL: trunc_freeze_load_i64_to_i8:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %trunc = trunc i64 %freeze to i8
  ret i8 %trunc
}

define i16 @trunc_freeze_load_i64_to_i16(ptr %p) {
; CHECK-LABEL: trunc_freeze_load_i64_to_i16:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrh w0, [x0]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %trunc = trunc i64 %freeze to i16
  ret i16 %trunc
}

define i16 @trunc_freeze_load_i32_to_i16(ptr %p) {
; CHECK-LABEL: trunc_freeze_load_i32_to_i16:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w0, [x0]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %trunc = trunc i32 %freeze to i16
  ret i16 %trunc
}

define i32 @sext_inreg_freeze_load_i8(ptr %p) {
; CHECK-LABEL: sext_inreg_freeze_load_i8:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrsb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %shl = shl i32 %freeze, 24
  %ashr = ashr i32 %shl, 24
  ret i32 %ashr
}

define i32 @sext_inreg_freeze_load_i16(ptr %p) {
; CHECK-LABEL: sext_inreg_freeze_load_i16:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrsh w0, [x0]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %shl = shl i32 %freeze, 16
  %ashr = ashr i32 %shl, 16
  ret i32 %ashr
}

define i32 @zext_trunc_freeze_load(ptr %p) {
; CHECK-LABEL: zext_trunc_freeze_load:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %trunc = trunc i64 %freeze to i8
  %zext = zext i8 %trunc to i32
  ret i32 %zext
}

define i32 @sext_trunc_freeze_load(ptr %p) {
; CHECK-LABEL: sext_trunc_freeze_load:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrsb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %trunc = trunc i64 %freeze to i8
  %sext = sext i8 %trunc to i32
  ret i32 %sext
}

define i32 @trunc_freeze_load_store(ptr %p, ptr %q) {
; CHECK-LABEL: trunc_freeze_load_store:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w8, [x0]
; CHECK-NEXT:    mov w0, wzr
; CHECK-NEXT:    strb w8, [x1]
; CHECK-NEXT:    ret
  %load = load i16, ptr %p, align 4
  %freeze = freeze i16 %load
  %trunc = trunc i16 %freeze to i8
  store i8 %trunc, ptr %q, align 1
  ret i32 0
}

define i32 @and_freeze_load_unaligned(ptr %p) {
; CHECK-LABEL: and_freeze_load_unaligned:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w0, [x0]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 1
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 255
  ret i32 %masked
}

define i32 @and_freeze_volatile_load(ptr %p) {
; CHECK-LABEL: and_freeze_volatile_load:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w8, [x0]
; CHECK-NEXT:    and w0, w8, #0xff
; CHECK-NEXT:    ret
  %load = load volatile i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 255
  ret i32 %masked
}

define i32 @and_freeze_atomic_load(ptr %p) {
; CHECK-LABEL: and_freeze_atomic_load:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldar w8, [x0]
; CHECK-NEXT:    and w0, w8, #0xff
; CHECK-NEXT:    ret
  %load = load atomic i32, ptr %p seq_cst, align 4
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 255
  ret i32 %masked
}

define i32 @and_freeze_non_contiguous_mask(ptr %p) {
; CHECK-LABEL: and_freeze_non_contiguous_mask:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w8, [x0]
; CHECK-NEXT:    mov w9, #170 ; =0xaa
; CHECK-NEXT:    and w0, w8, w9
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 170
  ret i32 %masked
}

define i32 @and_freeze_variable_mask(ptr %p, i32 %mask) {
; CHECK-LABEL: and_freeze_variable_mask:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w8, [x0]
; CHECK-NEXT:    and w0, w8, w1
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, %mask
  ret i32 %masked
}

define i32 @and_multiuse_freeze_extload_no_narrow(ptr %p) {
; CHECK-LABEL: and_multiuse_freeze_extload_no_narrow:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldrb w8, [x0]
; CHECK-NEXT:    cmp w8, #42
; CHECK-NEXT:    csel w0, w8, wzr, eq
; CHECK-NEXT:    ret
  %load = load i8, ptr %p
  %freeze = freeze i8 %load
  %zext = zext i8 %freeze to i32
  %cmp = icmp eq i8 %freeze, 42
  %sel = select i1 %cmp, i32 %zext, i32 0
  ret i32 %sel
}

define i32 @and_multiuse_freeze_narrowing(ptr %p, ptr %q) {
; CHECK-LABEL: and_multiuse_freeze_narrowing:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w8, [x0]
; CHECK-NEXT:    and w0, w8, #0xff
; CHECK-NEXT:    str w8, [x1]
; CHECK-NEXT:    ret
  %load = load i32, ptr %p
  %freeze = freeze i32 %load
  %masked = and i32 %freeze, 255
  store i32 %freeze, ptr %q
  ret i32 %masked
}

define i64 @and_multiuse_freeze_i64_narrowing(ptr %p, ptr %q) {
; CHECK-LABEL: and_multiuse_freeze_i64_narrowing:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr x8, [x0]
; CHECK-NEXT:    and x0, x8, #0xff
; CHECK-NEXT:    str x8, [x1]
; CHECK-NEXT:    ret
  %load = load i64, ptr %p
  %freeze = freeze i64 %load
  %masked = and i64 %freeze, 255
  store i64 %freeze, ptr %q
  ret i64 %masked
}

; SRL/SRA through freeze are not yet folded because the freeze peek-through
; happens after the SRL early-return in reduceLoadWidth.

define i32 @srl_freeze_load_i32(ptr %p) {
; CHECK-LABEL: srl_freeze_load_i32:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w8, [x0]
; CHECK-NEXT:    lsr w0, w8, #8
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %srl = lshr i32 %freeze, 8
  ret i32 %srl
}

define i32 @sra_freeze_load_i32(ptr %p) {
; CHECK-LABEL: sra_freeze_load_i32:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w8, [x0]
; CHECK-NEXT:    asr w0, w8, #8
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %sra = ashr i32 %freeze, 8
  ret i32 %sra
}

define i8 @trunc_srl_freeze_load(ptr %p) {
; CHECK-LABEL: trunc_srl_freeze_load:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr w8, [x0]
; CHECK-NEXT:    lsr w0, w8, #8
; CHECK-NEXT:    ret
  %load = load i32, ptr %p, align 4
  %freeze = freeze i32 %load
  %srl = lshr i32 %freeze, 8
  %trunc = trunc i32 %srl to i8
  ret i8 %trunc
}

define i16 @srl_freeze_load_i64_to_i16(ptr %p) {
; CHECK-LABEL: srl_freeze_load_i64_to_i16:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ldr x8, [x0]
; CHECK-NEXT:    lsr x0, x8, #16
; CHECK-NEXT:    ; kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT:    ret
  %load = load i64, ptr %p, align 8
  %freeze = freeze i64 %load
  %srl = lshr i64 %freeze, 16
  %trunc = trunc i64 %srl to i16
  ret i16 %trunc
}