llvm/test/CodeGen/AArch64/read-reg-non-entry.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64 -fast-isel=0 -global-isel=false -verify-machineinstrs < %s | FileCheck %s

define double @getRegFp_d5_branch(i1 %c) {
; CHECK-LABEL: getRegFp_d5_branch:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi d0, #0000000000000000
; CHECK-NEXT:    tbz w0, #0, .LBB0_2
; CHECK-NEXT:  // %bb.1: // %then
; CHECK-NEXT:    fmov d0, d5
; CHECK-NEXT:  .LBB0_2: // %common.ret
; CHECK-NEXT:    ret
entry:
  br i1 %c, label %then, label %else
then:
  %0 = call i64 @llvm.read_volatile_register.i64(metadata !0)
  %1 = bitcast i64 %0 to double
  ret double %1
else:
  ret double 0.0
}

define i64 @getReg_x5_branch(i1 %c) {
; CHECK-LABEL: getReg_x5_branch:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    tbz w0, #0, .LBB1_2
; CHECK-NEXT:  // %bb.1: // %then
; CHECK-NEXT:    mov x0, x5
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB1_2:
; CHECK-NEXT:    mov x0, xzr
; CHECK-NEXT:    ret
entry:
  br i1 %c, label %then, label %else
then:
  %0 = call i64 @llvm.read_volatile_register.i64(metadata !1)
  ret i64 %0
else:
  ret i64 0
}

declare i64 @llvm.read_volatile_register.i64(metadata)

!0 = !{!"d5"}
!1 = !{!"x5"}