llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
; CHECK-SD-LABEL: vector_deinterleave_v2f16_v4f16:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    dup v1.2s, v0.s[1]
; CHECK-SD-NEXT:    zip1 v2.4h, v0.4h, v1.4h
; CHECK-SD-NEXT:    trn2 v1.4h, v0.4h, v1.4h
; CHECK-SD-NEXT:    fmov d0, d2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: vector_deinterleave_v2f16_v4f16:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    uzp1 v2.4h, v0.4h, v0.4h
; CHECK-GI-NEXT:    uzp2 v1.4h, v0.4h, v0.4h
; CHECK-GI-NEXT:    fmov d0, d2
; CHECK-GI-NEXT:    ret
  %retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec)
  ret {<2 x half>, <2 x half>}   %retval
}

define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.8h, v0.8h, v0.8h
; CHECK-NEXT:    uzp2 v1.8h, v0.8h, v0.8h
; CHECK-NEXT:    // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT:    fmov d0, d2
; CHECK-NEXT:    ret
  %retval = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec)
  ret {<4 x half>, <4 x half>}   %retval
}

define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp2 v1.8h, v0.8h, v1.8h
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %retval = call {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half> %vec)
  ret {<8 x half>, <8 x half>}   %retval
}

define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
; CHECK-SD-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
; CHECK-SD-NEXT:    zip1 v2.2s, v0.2s, v1.2s
; CHECK-SD-NEXT:    zip2 v1.2s, v0.2s, v1.2s
; CHECK-SD-NEXT:    fmov d0, d2
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: vector_deinterleave_v2f32_v4f32:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    uzp1 v2.4s, v0.4s, v0.4s
; CHECK-GI-NEXT:    uzp2 v1.4s, v0.4s, v0.4s
; CHECK-GI-NEXT:    // kill: def $d1 killed $d1 killed $q1
; CHECK-GI-NEXT:    fmov d0, d2
; CHECK-GI-NEXT:    ret
  %retval = call {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float> %vec)
  ret {<2 x float>, <2 x float>}   %retval
}

define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp2 v1.4s, v0.4s, v1.4s
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %retval = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %vec)
ret  {<4 x float>, <4 x float>}   %retval
}

define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    zip1 v2.2d, v0.2d, v1.2d
; CHECK-NEXT:    zip2 v1.2d, v0.2d, v1.2d
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
  ret {<2 x double>, <2 x double>}   %retval
}

; Integers

define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.16b, v0.16b, v1.16b
; CHECK-NEXT:    uzp2 v1.16b, v0.16b, v1.16b
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %retval = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec)
  ret {<16 x i8>, <16 x i8>}   %retval
}

define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {
; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp2 v1.8h, v0.8h, v1.8h
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %retval = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec)
  ret {<8 x i16>, <8 x i16>}   %retval
}

define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_v8i32(<8 x i32> %vec) {
; CHECK-LABEL: vector_deinterleave_v4i32_v8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp2 v1.4s, v0.4s, v1.4s
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %retval = call {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32> %vec)
  ret {<4 x i32>, <4 x i32>}   %retval
}

define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    zip1 v2.2d, v0.2d, v1.2d
; CHECK-NEXT:    zip2 v1.2d, v0.2d, v1.2d
; CHECK-NEXT:    mov v0.16b, v2.16b
; CHECK-NEXT:    ret
  %retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
  ret {<2 x i64>, <2 x i64>}   %retval
}

define {<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>} @vector_deinterleave4_v8i8_v32i8(<32 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave4_v8i8_v32i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp2 v2.16b, v1.16b, v0.16b
; CHECK-NEXT:    uzp1 v3.16b, v0.16b, v1.16b
; CHECK-NEXT:    uzp2 v4.16b, v0.16b, v0.16b
; CHECK-NEXT:    xtn v5.8b, v1.8h
; CHECK-NEXT:    xtn v6.8b, v0.8h
; CHECK-NEXT:    xtn v0.8b, v3.8h
; CHECK-NEXT:    uzp1 v1.8b, v4.8b, v2.8b
; CHECK-NEXT:    uzp2 v3.8b, v4.8b, v2.8b
; CHECK-NEXT:    uzp2 v2.8b, v6.8b, v5.8b
; CHECK-NEXT:    ret
  %retval = call {<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>} @llvm.vector.deinterleave4.v32i8(<32 x i8> %vec)
  ret {<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>} %retval
}

define {<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>} @vector_deinterleave4_v16i8_v64i8(<64 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave4_v16i8_v64i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.16b, v2.16b, v3.16b
; CHECK-NEXT:    uzp1 v5.16b, v0.16b, v1.16b
; CHECK-NEXT:    uzp2 v3.16b, v2.16b, v3.16b
; CHECK-NEXT:    uzp2 v6.16b, v0.16b, v1.16b
; CHECK-NEXT:    uzp1 v0.16b, v5.16b, v4.16b
; CHECK-NEXT:    uzp2 v2.16b, v5.16b, v4.16b
; CHECK-NEXT:    uzp1 v1.16b, v6.16b, v3.16b
; CHECK-NEXT:    uzp2 v3.16b, v6.16b, v3.16b
; CHECK-NEXT:    ret
  %retval = call {<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>} @llvm.vector.deinterleave4.v64i8(<64 x i8> %vec)
  ret {<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>} %retval
}

define {<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>} @vector_deinterleave4_v4i16_v16i16(<16 x i16> %vec) {
; CHECK-LABEL: vector_deinterleave4_v4i16_v16i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp2 v2.8h, v1.8h, v0.8h
; CHECK-NEXT:    uzp1 v3.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp2 v4.8h, v0.8h, v0.8h
; CHECK-NEXT:    xtn v5.4h, v1.4s
; CHECK-NEXT:    xtn v6.4h, v0.4s
; CHECK-NEXT:    xtn v0.4h, v3.4s
; CHECK-NEXT:    uzp1 v1.4h, v4.4h, v2.4h
; CHECK-NEXT:    uzp2 v3.4h, v4.4h, v2.4h
; CHECK-NEXT:    uzp2 v2.4h, v6.4h, v5.4h
; CHECK-NEXT:    ret
  %retval = call {<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>} @llvm.vector.deinterleave4.v16i16(<16 x i16> %vec)
  ret {<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>} %retval
}

define {<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>} @vector_deinterleave4_v8i16_v32i16(<32 x i16> %vec) {
; CHECK-LABEL: vector_deinterleave4_v8i16_v32i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.8h, v2.8h, v3.8h
; CHECK-NEXT:    uzp1 v5.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp2 v3.8h, v2.8h, v3.8h
; CHECK-NEXT:    uzp2 v6.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp1 v0.8h, v5.8h, v4.8h
; CHECK-NEXT:    uzp2 v2.8h, v5.8h, v4.8h
; CHECK-NEXT:    uzp1 v1.8h, v6.8h, v3.8h
; CHECK-NEXT:    uzp2 v3.8h, v6.8h, v3.8h
; CHECK-NEXT:    ret
  %retval = call {<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>} @llvm.vector.deinterleave4.v32i16(<32 x i16> %vec)
  ret {<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>} %retval
}

define {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @vector_deinterleave4_v2i32_v8i32(<8 x i32> %vec) {
; CHECK-LABEL: vector_deinterleave4_v2i32_v8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp2 v2.4s, v1.4s, v0.4s
; CHECK-NEXT:    uzp1 v3.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp2 v4.4s, v0.4s, v0.4s
; CHECK-NEXT:    xtn v5.2s, v1.2d
; CHECK-NEXT:    xtn v6.2s, v0.2d
; CHECK-NEXT:    xtn v0.2s, v3.2d
; CHECK-NEXT:    uzp1 v1.2s, v4.2s, v2.2s
; CHECK-NEXT:    uzp2 v3.2s, v4.2s, v2.2s
; CHECK-NEXT:    uzp2 v2.2s, v6.2s, v5.2s
; CHECK-NEXT:    ret
  %retval = call {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @llvm.vector.deinterleave4.v8i32(<8 x i32> %vec)
  ret {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} %retval
}

define {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @vector_deinterleave4_v4i32_v16i32(<16 x i32> %vec) {
; CHECK-LABEL: vector_deinterleave4_v4i32_v16i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.4s, v2.4s, v3.4s
; CHECK-NEXT:    uzp1 v5.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp2 v3.4s, v2.4s, v3.4s
; CHECK-NEXT:    uzp2 v6.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp1 v0.4s, v5.4s, v4.4s
; CHECK-NEXT:    uzp2 v2.4s, v5.4s, v4.4s
; CHECK-NEXT:    uzp1 v1.4s, v6.4s, v3.4s
; CHECK-NEXT:    uzp2 v3.4s, v6.4s, v3.4s
; CHECK-NEXT:    ret
  %retval = call {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} @llvm.vector.deinterleave4.v16i32(<16 x i32> %vec)
  ret {<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>} %retval
}

define {<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>} @vector_deinterleave4_v1i64_v4i64(<4 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave4_v1i64_v4i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov v2.16b, v1.16b
; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT:    // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT:    ext v3.16b, v2.16b, v2.16b, #8
; CHECK-NEXT:    // kill: def $d2 killed $d2 killed $q2
; CHECK-NEXT:    // kill: def $d3 killed $d3 killed $q3
; CHECK-NEXT:    ret
  %retval = call {<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>} @llvm.vector.deinterleave4.v4i64(<4 x i64> %vec)
  ret {<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>} %retval
}

define {<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>} @vector_deinterleave4_v2i64_v8i64(<8 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave4_v2i64_v8i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.2d, v2.2d, v3.2d
; CHECK-NEXT:    uzp1 v5.2d, v0.2d, v1.2d
; CHECK-NEXT:    uzp2 v3.2d, v2.2d, v3.2d
; CHECK-NEXT:    uzp2 v6.2d, v0.2d, v1.2d
; CHECK-NEXT:    uzp1 v0.2d, v5.2d, v4.2d
; CHECK-NEXT:    uzp2 v2.2d, v5.2d, v4.2d
; CHECK-NEXT:    uzp1 v1.2d, v6.2d, v3.2d
; CHECK-NEXT:    uzp2 v3.2d, v6.2d, v3.2d
; CHECK-NEXT:    ret
  %retval = call {<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>} @llvm.vector.deinterleave4.v8i64(<8 x i64> %vec)
  ret {<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>} %retval
}

define {<4 x half>, <4 x half>, <4 x half>, <4 x half>} @vector_deinterleave4_v4f16_v16f16(<16 x half> %vec) {
; CHECK-LABEL: vector_deinterleave4_v4f16_v16f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.8h, v1.8h, v0.8h
; CHECK-NEXT:    uzp1 v3.8h, v0.8h, v0.8h
; CHECK-NEXT:    uzp2 v4.8h, v1.8h, v0.8h
; CHECK-NEXT:    uzp2 v5.8h, v0.8h, v0.8h
; CHECK-NEXT:    uzp1 v0.4h, v3.4h, v2.4h
; CHECK-NEXT:    uzp2 v2.4h, v3.4h, v2.4h
; CHECK-NEXT:    uzp1 v1.4h, v5.4h, v4.4h
; CHECK-NEXT:    uzp2 v3.4h, v5.4h, v4.4h
; CHECK-NEXT:    ret
  %retval = call {<4 x half>, <4 x half>, <4 x half>, <4 x half>} @llvm.vector.deinterleave4.v16f16(<16 x half> %vec)
  ret {<4 x half>, <4 x half>, <4 x half>, <4 x half>} %retval
}

define {<8 x half>, <8 x half>, <8 x half>, <8 x half>} @vector_deinterleave4_v8f16_v32f16(<32 x half> %vec) {
; CHECK-LABEL: vector_deinterleave4_v8f16_v32f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.8h, v2.8h, v3.8h
; CHECK-NEXT:    uzp1 v5.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp2 v3.8h, v2.8h, v3.8h
; CHECK-NEXT:    uzp2 v6.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp1 v0.8h, v5.8h, v4.8h
; CHECK-NEXT:    uzp2 v2.8h, v5.8h, v4.8h
; CHECK-NEXT:    uzp1 v1.8h, v6.8h, v3.8h
; CHECK-NEXT:    uzp2 v3.8h, v6.8h, v3.8h
; CHECK-NEXT:    ret
  %retval = call {<8 x half>, <8 x half>, <8 x half>, <8 x half>} @llvm.vector.deinterleave4.v32f16(<32 x half> %vec)
  ret {<8 x half>, <8 x half>, <8 x half>, <8 x half>} %retval
}

define {<2 x float>, <2 x float>, <2 x float>, <2 x float>} @vector_deinterleave4_v2f32_v8f32(<8 x float> %vec) {
; CHECK-LABEL: vector_deinterleave4_v2f32_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ext v2.16b, v1.16b, v1.16b, #8
; CHECK-NEXT:    ext v3.16b, v0.16b, v0.16b, #8
; CHECK-NEXT:    uzp1 v4.2s, v1.2s, v2.2s
; CHECK-NEXT:    uzp1 v5.2s, v0.2s, v3.2s
; CHECK-NEXT:    uzp2 v6.2s, v1.2s, v2.2s
; CHECK-NEXT:    uzp2 v3.2s, v0.2s, v3.2s
; CHECK-NEXT:    uzp1 v0.2s, v5.2s, v4.2s
; CHECK-NEXT:    uzp2 v2.2s, v5.2s, v4.2s
; CHECK-NEXT:    uzp1 v1.2s, v3.2s, v6.2s
; CHECK-NEXT:    uzp2 v3.2s, v3.2s, v6.2s
; CHECK-NEXT:    ret
  %retval = call {<2 x float>, <2 x float>, <2 x float>, <2 x float>} @llvm.vector.deinterleave4.v8f32(<8 x float> %vec)
  ret {<2 x float>, <2 x float>, <2 x float>, <2 x float>} %retval
}

define {<4 x float>, <4 x float>, <4 x float>, <4 x float>} @vector_deinterleave4_v4f32_v16f32(<16 x float> %vec) {
; CHECK-LABEL: vector_deinterleave4_v4f32_v16f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.4s, v2.4s, v3.4s
; CHECK-NEXT:    uzp1 v5.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp2 v3.4s, v2.4s, v3.4s
; CHECK-NEXT:    uzp2 v6.4s, v0.4s, v1.4s
; CHECK-NEXT:    uzp1 v0.4s, v5.4s, v4.4s
; CHECK-NEXT:    uzp2 v2.4s, v5.4s, v4.4s
; CHECK-NEXT:    uzp1 v1.4s, v6.4s, v3.4s
; CHECK-NEXT:    uzp2 v3.4s, v6.4s, v3.4s
; CHECK-NEXT:    ret
  %retval = call {<4 x float>, <4 x float>, <4 x float>, <4 x float>} @llvm.vector.deinterleave4.v16f32(<16 x float> %vec)
  ret {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %retval
}

define {<1 x double>, <1 x double>, <1 x double>, <1 x double>} @vector_deinterleave4_v1f64_v4f64(<4 x double> %vec) {
; CHECK-LABEL: vector_deinterleave4_v1f64_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov v2.16b, v1.16b
; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT:    // kill: def $d1 killed $d1 killed $q1
; CHECK-NEXT:    ext v3.16b, v2.16b, v2.16b, #8
; CHECK-NEXT:    // kill: def $d2 killed $d2 killed $q2
; CHECK-NEXT:    // kill: def $d3 killed $d3 killed $q3
; CHECK-NEXT:    ret
  %retval = call {<1 x double>, <1 x double>, <1 x double>, <1 x double>} @llvm.vector.deinterleave4.v4f64(<4 x double> %vec)
  ret {<1 x double>, <1 x double>, <1 x double>, <1 x double>} %retval
}

define {<2 x double>, <2 x double>, <2 x double>, <2 x double>} @vector_deinterleave4_v2f64_v8f64(<8 x double> %vec) {
; CHECK-LABEL: vector_deinterleave4_v2f64_v8f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.2d, v2.2d, v3.2d
; CHECK-NEXT:    uzp1 v5.2d, v0.2d, v1.2d
; CHECK-NEXT:    uzp2 v3.2d, v2.2d, v3.2d
; CHECK-NEXT:    uzp2 v6.2d, v0.2d, v1.2d
; CHECK-NEXT:    uzp1 v0.2d, v5.2d, v4.2d
; CHECK-NEXT:    uzp2 v2.2d, v5.2d, v4.2d
; CHECK-NEXT:    uzp1 v1.2d, v6.2d, v3.2d
; CHECK-NEXT:    uzp2 v3.2d, v6.2d, v3.2d
; CHECK-NEXT:    ret
  %retval = call {<2 x double>, <2 x double>, <2 x double>, <2 x double>} @llvm.vector.deinterleave4.v8f64(<8 x double> %vec)
  ret {<2 x double>, <2 x double>, <2 x double>, <2 x double>} %retval
}

define {<4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>} @vector_deinterleave4_v4bf16_v16bf16(<16 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave4_v4bf16_v16bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v2.8h, v1.8h, v0.8h
; CHECK-NEXT:    uzp1 v3.8h, v0.8h, v0.8h
; CHECK-NEXT:    uzp2 v4.8h, v1.8h, v0.8h
; CHECK-NEXT:    uzp2 v5.8h, v0.8h, v0.8h
; CHECK-NEXT:    uzp1 v0.4h, v3.4h, v2.4h
; CHECK-NEXT:    uzp2 v2.4h, v3.4h, v2.4h
; CHECK-NEXT:    uzp1 v1.4h, v5.4h, v4.4h
; CHECK-NEXT:    uzp2 v3.4h, v5.4h, v4.4h
; CHECK-NEXT:    ret
  %retval = call {<4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>} @llvm.vector.deinterleave4.v16bf16(<16 x bfloat> %vec)
  ret {<4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat>} %retval
}

define {<8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>} @vector_deinterleave4_v8bf16_v32bf16(<32 x bfloat> %vec) {
; CHECK-LABEL: vector_deinterleave4_v8bf16_v32bf16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uzp1 v4.8h, v2.8h, v3.8h
; CHECK-NEXT:    uzp1 v5.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp2 v3.8h, v2.8h, v3.8h
; CHECK-NEXT:    uzp2 v6.8h, v0.8h, v1.8h
; CHECK-NEXT:    uzp1 v0.8h, v5.8h, v4.8h
; CHECK-NEXT:    uzp2 v2.8h, v5.8h, v4.8h
; CHECK-NEXT:    uzp1 v1.8h, v6.8h, v3.8h
; CHECK-NEXT:    uzp2 v3.8h, v6.8h, v3.8h
; CHECK-NEXT:    ret
  %retval = call {<8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>} @llvm.vector.deinterleave4.v32bf16(<32 x bfloat> %vec)
  ret {<8 x bfloat>, <8 x bfloat>, <8 x bfloat>, <8 x bfloat>} %retval
}