| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 |
| # RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s |
| --- | |
| define i32 @test01() nounwind { |
| entry: |
| %0 = select i1 true, i32 1, i32 0 |
| %1 = and i32 %0, 65535 |
| %2 = icmp sgt i32 %1, 0 |
| br i1 %2, label %if.then, label %if.end |
| |
| if.then: ; preds = %entry |
| ret i32 1 |
| |
| if.end: ; preds = %entry |
| ret i32 0 |
| } |
| ... |
| --- |
| name: test01 |
| registers: |
| - { id: 0, class: gpr32 } |
| - { id: 1, class: gpr32common } |
| body: | |
| ; CHECK-LABEL: name: test01 |
| ; CHECK: bb.0.entry: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 |
| ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32common = ANDSWri killed [[ANDSWri]], 15, implicit-def $nzcv |
| ; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1.if.then: |
| ; CHECK-NEXT: $w0 = MOVi32imm 1 |
| ; CHECK-NEXT: RET_ReallyLR implicit $w0 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2.if.end: |
| ; CHECK-NEXT: $w0 = MOVi32imm 0 |
| ; CHECK-NEXT: RET_ReallyLR implicit $w0 |
| bb.0.entry: |
| successors: %bb.2.if.end, %bb.1.if.then |
| |
| %0 = MOVi32imm 1 |
| %1 = ANDWri killed %1, 15 |
| $wzr = SUBSWri killed %1, 0, 0, implicit-def $nzcv |
| Bcc 12, %bb.2.if.end, implicit $nzcv |
| |
| bb.1.if.then: |
| $w0 = MOVi32imm 1 |
| RET_ReallyLR implicit $w0 |
| |
| bb.2.if.end: |
| $w0 = MOVi32imm 0 |
| RET_ReallyLR implicit $w0 |
| |
| ... |
