llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @cmpxchg_i32(ptr %addr) { ret void }
  define void @cmpxchg_i64(ptr %addr) { ret void }
...

---
name:            cmpxchg_i32
legalized:       true
regBankSelected: true

body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: cmpxchg_i32
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
    ; CHECK-NEXT: [[CASW:%[0-9]+]]:gpr32 = CASW [[COPY1]], [[MOVi32imm]], [[COPY]] :: (load store monotonic (i32) on %ir.addr)
    ; CHECK-NEXT: $w0 = COPY [[CASW]]
    %0:gpr(p0) = COPY $x0
    %1:gpr(i32) = G_CONSTANT i32 0
    %2:gpr(i32) = G_CONSTANT i32 1
    %3:gpr(i32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (i32) on %ir.addr)
    $w0 = COPY %3(i32)
...

---
name:            cmpxchg_i64
legalized:       true
regBankSelected: true

body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: cmpxchg_i64
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
    ; CHECK-NEXT: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY1]], [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (i64) on %ir.addr)
    ; CHECK-NEXT: $x0 = COPY [[CASX]]
    %0:gpr(p0) = COPY $x0
    %1:gpr(i64) = G_CONSTANT i64 0
    %2:gpr(i64) = G_CONSTANT i64 1
    %3:gpr(i64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (i64) on %ir.addr)
    $x0 = COPY %3(i64)
...