llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 -O0 %s -o - | FileCheck %s
---
name:            test_freeze_s64
body: |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: test_freeze_s64
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %x0:_(i64) = COPY $x0
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(i64) = G_FREEZE %x0
    ; CHECK-NEXT: $x0 = COPY [[FREEZE]](i64)
    %x0:_(i64) = COPY $x0
    %1:_(i64) = G_FREEZE %x0
    $x0 = COPY %1(i64)
...
---
name: test_freeze_v4s32
body: |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_freeze_v4s32
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %q0:_(<4 x i32>) = COPY $q0
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x i32>) = G_FREEZE %q0
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x i32>), [[UV1:%[0-9]+]]:_(<2 x i32>) = G_UNMERGE_VALUES [[FREEZE]](<4 x i32>)
    ; CHECK-NEXT: $x0 = COPY [[UV]](<2 x i32>)
    ; CHECK-NEXT: $x1 = COPY [[UV1]](<2 x i32>)
    %q0:_(<4 x i32>) = COPY $q0
    %0:_(<4 x i32>) = G_FREEZE %q0
    %1:_(<2 x i32> ), %2:_(<2 x i32>) = G_UNMERGE_VALUES %0
    $x0 = COPY %1
    $x1 = COPY %2
...
---
name: test_freeze_v4s64
body: |
  bb.0:

    ; CHECK-LABEL: name: test_freeze_v4s64
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x i64>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x i64>) = G_FREEZE [[DEF]]
    ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(<2 x i64>) = G_FREEZE [[DEF]]
    ; CHECK-NEXT: $q0 = COPY [[FREEZE]](<2 x i64>)
    ; CHECK-NEXT: $q1 = COPY [[FREEZE1]](<2 x i64>)
    %undef:_(<4 x i64>) = G_IMPLICIT_DEF
    %0:_(<4 x i64>) = G_FREEZE %undef
    %1:_(<2 x i64> ), %2:_(<2 x i64>) = G_UNMERGE_VALUES %0
    $q0 = COPY %1
    $q1 = COPY %2
...
---
name: test_freeze_v2s32
body: |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_freeze_v2s32
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %d0:_(<2 x i32>) = COPY $d0
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<2 x i32>) = G_FREEZE %d0
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[FREEZE]](<2 x i32>)
    ; CHECK-NEXT: $w0 = COPY [[UV]](i32)
    ; CHECK-NEXT: $w1 = COPY [[UV1]](i32)
    %d0:_(<2 x i32>) = COPY $d0
    %0:_(<2 x i32>) = G_FREEZE %d0
    %1:_(i32), %2:_(i32) = G_UNMERGE_VALUES %0
    $w0 = COPY %1
    $w1 = COPY %2
...
---
name: test_freeze_v8s8
body: |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_freeze_v8s8
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %d0:_(<8 x i8>) = COPY $d0
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<8 x i8>) = G_FREEZE %d0
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x i8>), [[UV1:%[0-9]+]]:_(<4 x i8>) = G_UNMERGE_VALUES [[FREEZE]](<8 x i8>)
    ; CHECK-NEXT: $w0 = COPY [[UV]](<4 x i8>)
    ; CHECK-NEXT: $w1 = COPY [[UV1]](<4 x i8>)
    %d0:_(<8 x i8>) = COPY $d0
    %0:_(<8 x i8>) = G_FREEZE %d0
    %1:_(<4 x i8>), %2:_(<4 x i8>) = G_UNMERGE_VALUES %0
    $w0 = COPY %1
    $w1 = COPY %2
...
---
name:            test_freeze_s1
body: |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: test_freeze_s1
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(i8) = G_FREEZE [[DEF]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[FREEZE]](i8)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 1
    ; CHECK-NEXT: %ext:_(i64) = G_AND [[ANYEXT]], [[C]]
    ; CHECK-NEXT: $x0 = COPY %ext(i64)
    %x:_(i1) = G_IMPLICIT_DEF
    %freeze:_(i1) = G_FREEZE %x
    %ext:_(i64) = G_ZEXT %freeze
    $x0 = COPY %ext(i64)
...
---
name:            test_freeze_s2
body: |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: test_freeze_s2
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i8) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(i8) = G_FREEZE [[DEF]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(i64) = G_ANYEXT [[FREEZE]](i8)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i64) = G_CONSTANT i64 3
    ; CHECK-NEXT: %ext:_(i64) = G_AND [[ANYEXT]], [[C]]
    ; CHECK-NEXT: $x0 = COPY %ext(i64)
    %x:_(i2) = G_IMPLICIT_DEF
    %freeze:_(i2) = G_FREEZE %x
    %ext:_(i64) = G_ZEXT %freeze
    $x0 = COPY %ext(i64)
...
---
name:            test_freeze_v4s1
body: |
  bb.0.entry:
    liveins: $q0
    ; CHECK-LABEL: name: test_freeze_v4s1
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x i16>) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x i16>) = G_FREEZE [[DEF]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x i32>) = G_ANYEXT [[FREEZE]](<4 x i16>)
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C]](i32), [[C]](i32), [[C]](i32), [[C]](i32)
    ; CHECK-NEXT: %ext:_(<4 x i32>) = G_AND [[ANYEXT]], [[BUILD_VECTOR]]
    ; CHECK-NEXT: $q0 = COPY %ext(<4 x i32>)
    %x:_(<4 x i1>) = G_IMPLICIT_DEF
    %freeze:_(<4 x i1>) = G_FREEZE %x
    %ext:_(<4 x i32>) = G_ZEXT %freeze
    $q0 = COPY %ext(<4 x i32>)
...
---
name:            test_freeze_v3s8
body: |
  bb.0.entry:
    liveins: $q0
    ; CHECK-LABEL: name: test_freeze_v3s8
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i16>) = G_BUILD_VECTOR [[DEF]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16), [[DEF]](i16)
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x i8>) = G_TRUNC [[BUILD_VECTOR]](<8 x i16>)
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x i8>), [[UV1:%[0-9]+]]:_(<4 x i8>) = G_UNMERGE_VALUES [[TRUNC]](<8 x i8>)
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x i8>) = G_FREEZE [[UV]]
    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i8), [[UV3:%[0-9]+]]:_(i8), [[UV4:%[0-9]+]]:_(i8), [[UV5:%[0-9]+]]:_(i8) = G_UNMERGE_VALUES [[FREEZE]](<4 x i8>)
    ; CHECK-NEXT: %undef:_(i32) = G_IMPLICIT_DEF
    ; CHECK-NEXT: %ext0:_(i32) = G_ZEXT [[UV2]](i8)
    ; CHECK-NEXT: %ext1:_(i32) = G_ZEXT [[UV3]](i8)
    ; CHECK-NEXT: %ext2:_(i32) = G_ZEXT [[UV4]](i8)
    ; CHECK-NEXT: %res:_(<4 x i32>) = G_BUILD_VECTOR %ext0(i32), %ext1(i32), %ext2(i32), %undef(i32)
    ; CHECK-NEXT: $q0 = COPY %res(<4 x i32>)
    %x:_(<3 x i8>) = G_IMPLICIT_DEF
    %freeze:_(<3 x i8>) = G_FREEZE %x
    %ext:_(<3 x i32>) = G_ZEXT %freeze
    %undef:_(i32) = G_IMPLICIT_DEF
    %ext0:_(i32), %ext1:_(i32), %ext2:_(i32) = G_UNMERGE_VALUES %ext
    %res:_(<4 x i32>) = G_BUILD_VECTOR %ext0, %ext1, %ext2, %undef
    $q0 = COPY %res(<4 x i32>)
...
---
name:            test_freeze_v4s1_select
body: |
  bb.0.entry:
    liveins: $q0, $q1
    ; CHECK-LABEL: name: test_freeze_v4s1_select
    ; CHECK: liveins: $q0, $q1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x f32>) = COPY $q0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x f32>) = COPY $q1
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(f32) = G_FCONSTANT float 0.000000e+00
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[C]](f32), [[C]](f32), [[C]](f32), [[C]](f32)
    ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x i32>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(olt), [[COPY]](<4 x f32>), [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(<4 x i32>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(ogt), [[COPY1]](<4 x f32>), [[COPY]]
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x i16>) = G_TRUNC [[FCMP1]](<4 x i32>)
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<4 x i16>) = G_FREEZE [[TRUNC]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x i16>) = G_TRUNC [[FCMP]](<4 x i32>)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x i16>) = G_AND [[TRUNC1]], [[FREEZE]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x i32>) = G_ANYEXT [[AND]](<4 x i16>)
    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[C1]](i32), [[C1]](i32), [[C1]](i32), [[C1]](i32)
    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x i32>) = G_AND [[ANYEXT]], [[BUILD_VECTOR1]]
    ; CHECK-NEXT: $q0 = COPY [[AND1]](<4 x i32>)
    %1:_(<4 x f32>) = COPY $q0
    %2:_(<4 x f32>) = COPY $q1
    %3:_(f32) = G_FCONSTANT float 0.0
    %4:_(<4 x f32>) = G_BUILD_VECTOR %3, %3, %3, %3
    %5:_(i1) = G_CONSTANT i1 false
    %6:_(<4 x i1>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(olt), %1:_(<4 x f32>), %4:_
    %7:_(<4 x i1>) = nnan ninf nsz arcp contract afn reassoc G_FCMP floatpred(ogt), %2:_(<4 x f32>), %1:_
    %8:_(<4 x i1>) = G_FREEZE %7
    %9:_(<4 x i1>) = G_AND %6, %8
    %10:_(<4 x i32>) = G_ZEXT %9
    $q0 = COPY %10