llvm/test/CodeGen/AArch64/GlobalISel/compute-known-bits-bitcast-assertion.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-unknown-linux -global-isel -global-isel-abort=1 < %s | FileCheck %s

define <2 x i8> @test_bitcast_assertion(<4 x i32> %vqaddq_v2.i.i, ptr %BS_VAR_0) {
; CHECK-LABEL: test_bitcast_assertion:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    mov x8, sp
; CHECK-NEXT:    mov w9, #4 // =0x4
; CHECK-NEXT:  .LBB0_1: // %for.cond
; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    umov w10, v1.h[0]
; CHECK-NEXT:    str q0, [sp]
; CHECK-NEXT:    and x10, x10, #0x3
; CHECK-NEXT:    umull x10, w10, w9
; CHECK-NEXT:    ldrh w10, [x8, x10]
; CHECK-NEXT:    stp q1, q1, [x0, #32]
; CHECK-NEXT:    stp q1, q1, [x0, #64]
; CHECK-NEXT:    fmov d2, x10
; CHECK-NEXT:    stp q1, q1, [x0, #96]
; CHECK-NEXT:    mov v2.d[1], xzr
; CHECK-NEXT:    stp q2, q1, [x0]
; CHECK-NEXT:    b .LBB0_1
entry:
  br label %for.cond

for.cond:                                         ; preds = %for.cond, %entry
  %vec_wide = phi <64 x i16> [ %bitcasted_vec, %for.cond ], [ zeroinitializer, %entry ]
  %conv = extractelement <64 x i16> %vec_wide, i64 0
  %vecext.i = extractelement <4 x i32> %vqaddq_v2.i.i, i16 %conv
  %masked_val = and i32 %vecext.i, 65535
  %val_i64 = zext i32 %masked_val to i64
  %vecinit16 = insertelement <16 x i64> zeroinitializer, i64 %val_i64, i64 0
  store <16 x i64> %vecinit16, ptr %BS_VAR_0, align 16
  %bitcasted_vec = bitcast <16 x i64> zeroinitializer to <64 x i16>
  br label %for.cond
}