clang/test/CodeGenHIP/builtins-amdgcn-mfma-gfx908.hip

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
// REQUIRES: amdgpu-registered-target
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx908 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s --check-prefix=CHECK-GFX908

#define __device__ __attribute__((device))

typedef float    v4f   __attribute__((ext_vector_type(4)));
typedef float    v16f  __attribute__((ext_vector_type(16)));
typedef float    v32f  __attribute__((ext_vector_type(32)));
typedef _Float16 v4h   __attribute__((ext_vector_type(4)));
typedef _Float16 v8h   __attribute__((ext_vector_type(8)));
typedef _Float16 v16h  __attribute__((ext_vector_type(16)));

// CHECK-GFX908-LABEL: define dso_local void @_Z28test_mfma_f32_32x32x4f16_hipPDv32_fDv4_DF16_S1_S_(
// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <32 x float> noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-GFX908-NEXT:  [[ENTRY:.*:]]
// CHECK-GFX908-NEXT:    [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[C_ADDR:%.*]] = alloca <32 x float>, align 128, addrspace(5)
// CHECK-GFX908-NEXT:    [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr
// CHECK-GFX908-NEXT:    store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <32 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 128
// CHECK-GFX908-NEXT:    [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP2:%.*]] = load <32 x float>, ptr [[C_ADDR_ASCAST]], align 128
// CHECK-GFX908-NEXT:    [[TMP3:%.*]] = call contract <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <32 x float> [[TMP2]], i32 0, i32 0, i32 0)
// CHECK-GFX908-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <32 x float> [[TMP3]], ptr [[TMP4]], align 128
// CHECK-GFX908-NEXT:    ret void
//
__device__ void test_mfma_f32_32x32x4f16_hip(v32f* out, v4h a, v4h b, v32f c) {
  *out = __builtin_amdgcn_mfma_f32_32x32x4f16(a, b, c, 0, 0, 0);
}

// CHECK-GFX908-LABEL: define dso_local void @_Z28test_mfma_f32_16x16x4f16_hipPDv16_fDv4_DF16_S1_S_(
// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <16 x float> noundef [[C:%.*]]) #[[ATTR0]] {
// CHECK-GFX908-NEXT:  [[ENTRY:.*:]]
// CHECK-GFX908-NEXT:    [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[C_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5)
// CHECK-GFX908-NEXT:    [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr
// CHECK-GFX908-NEXT:    store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <16 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 64
// CHECK-GFX908-NEXT:    [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP2:%.*]] = load <16 x float>, ptr [[C_ADDR_ASCAST]], align 64
// CHECK-GFX908-NEXT:    [[TMP3:%.*]] = call contract <16 x float> @llvm.amdgcn.mfma.f32.16x16x4f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <16 x float> [[TMP2]], i32 0, i32 0, i32 0)
// CHECK-GFX908-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <16 x float> [[TMP3]], ptr [[TMP4]], align 64
// CHECK-GFX908-NEXT:    ret void
//
__device__ void test_mfma_f32_16x16x4f16_hip(v16f* out, v4h a, v4h b, v16f c) {
  *out = __builtin_amdgcn_mfma_f32_16x16x4f16(a, b, c, 0, 0, 0);
}

// CHECK-GFX908-LABEL: define dso_local void @_Z26test_mfma_f32_4x4x4f16_hipPDv4_fDv4_DF16_S1_S_(
// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] {
// CHECK-GFX908-NEXT:  [[ENTRY:.*:]]
// CHECK-GFX908-NEXT:    [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[C_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5)
// CHECK-GFX908-NEXT:    [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr
// CHECK-GFX908-NEXT:    store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 16
// CHECK-GFX908-NEXT:    [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP2:%.*]] = load <4 x float>, ptr [[C_ADDR_ASCAST]], align 16
// CHECK-GFX908-NEXT:    [[TMP3:%.*]] = call contract <4 x float> @llvm.amdgcn.mfma.f32.4x4x4f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <4 x float> [[TMP2]], i32 0, i32 0, i32 0)
// CHECK-GFX908-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x float> [[TMP3]], ptr [[TMP4]], align 16
// CHECK-GFX908-NEXT:    ret void
//
__device__ void test_mfma_f32_4x4x4f16_hip(v4f* out, v4h a, v4h b, v4f c) {
  *out = __builtin_amdgcn_mfma_f32_4x4x4f16(a, b, c, 0, 0, 0);
}

// CHECK-GFX908-LABEL: define dso_local void @_Z28test_mfma_f32_32x32x8f16_hipPDv16_fDv4_DF16_S1_S_(
// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <16 x float> noundef [[C:%.*]]) #[[ATTR0]] {
// CHECK-GFX908-NEXT:  [[ENTRY:.*:]]
// CHECK-GFX908-NEXT:    [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[C_ADDR:%.*]] = alloca <16 x float>, align 64, addrspace(5)
// CHECK-GFX908-NEXT:    [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr
// CHECK-GFX908-NEXT:    store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <16 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 64
// CHECK-GFX908-NEXT:    [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP2:%.*]] = load <16 x float>, ptr [[C_ADDR_ASCAST]], align 64
// CHECK-GFX908-NEXT:    [[TMP3:%.*]] = call contract <16 x float> @llvm.amdgcn.mfma.f32.32x32x8f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <16 x float> [[TMP2]], i32 0, i32 0, i32 0)
// CHECK-GFX908-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <16 x float> [[TMP3]], ptr [[TMP4]], align 64
// CHECK-GFX908-NEXT:    ret void
//
__device__ void test_mfma_f32_32x32x8f16_hip(v16f* out, v4h a, v4h b, v16f c) {
  *out = __builtin_amdgcn_mfma_f32_32x32x8f16(a, b, c, 0, 0, 0);
}

// CHECK-GFX908-LABEL: define dso_local void @_Z29test_mfma_f32_16x16x16f16_hipPDv4_fDv4_DF16_S1_S_(
// CHECK-GFX908-SAME: ptr noundef [[OUT:%.*]], <4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], <4 x float> noundef [[C:%.*]]) #[[ATTR0]] {
// CHECK-GFX908-NEXT:  [[ENTRY:.*:]]
// CHECK-GFX908-NEXT:    [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[A_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[B_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5)
// CHECK-GFX908-NEXT:    [[C_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5)
// CHECK-GFX908-NEXT:    [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
// CHECK-GFX908-NEXT:    [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr
// CHECK-GFX908-NEXT:    store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x float> [[C]], ptr [[C_ADDR_ASCAST]], align 16
// CHECK-GFX908-NEXT:    [[TMP0:%.*]] = load <4 x half>, ptr [[A_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP1:%.*]] = load <4 x half>, ptr [[B_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    [[TMP2:%.*]] = load <4 x float>, ptr [[C_ADDR_ASCAST]], align 16
// CHECK-GFX908-NEXT:    [[TMP3:%.*]] = call contract <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> [[TMP0]], <4 x half> [[TMP1]], <4 x float> [[TMP2]], i32 0, i32 0, i32 0)
// CHECK-GFX908-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
// CHECK-GFX908-NEXT:    store <4 x float> [[TMP3]], ptr [[TMP4]], align 16
// CHECK-GFX908-NEXT:    ret void
//
__device__ void test_mfma_f32_16x16x16f16_hip(v4f* out, v4h a, v4h b, v4f c) {
  *out = __builtin_amdgcn_mfma_f32_16x16x16f16(a, b, c, 0, 0, 0);
}