| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s |
| |
| // REQUIRES: aarch64-registered-target || arm-registered-target |
| |
| #include <arm_neon.h> |
| |
| // CHECK-LABEL: @test_vcreate_bf16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat> |
| // CHECK-NEXT: ret <4 x bfloat> [[TMP0]] |
| // |
| bfloat16x4_t test_vcreate_bf16(uint64_t a) { |
| return vcreate_bf16(a); |
| } |
| |
| // CHECK-LABEL: @test_vcombine_bf16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> |
| // CHECK-NEXT: ret <8 x bfloat> [[SHUFFLE_I]] |
| // |
| bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) { |
| return vcombine_bf16(low, high); |
| } |
| |
| // CHECK-LABEL: @test_vset_lane_bf16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1 |
| // CHECK-NEXT: ret <4 x bfloat> [[VSET_LANE]] |
| // |
| bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) { |
| return vset_lane_bf16(a, v, 1); |
| } |
| |
| // CHECK-LABEL: @test_vsetq_lane_bf16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7 |
| // CHECK-NEXT: ret <8 x bfloat> [[VSET_LANE]] |
| // |
| bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) { |
| return vsetq_lane_bf16(a, v, 7); |
| } |
