llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=x86_64-- -run-pass=register-coalescer -enable-subreg-liveness -verify-coalescing -o - %s | FileCheck %s


# FIXME: Need to handle subrange updates when coalescing with subreg_to_reg
# This will fail if x86 enables subregister liveness.
---
name: requires_new_subrange_coalesce_subreg_to_reg
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: requires_new_subrange_coalesce_subreg_to_reg
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK-NEXT:   liveins: $eax
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   undef %a.sub_32bit:gr64_with_sub_8bit = COPY $eax
  ; CHECK-NEXT:   %b:gr32 = IMPLICIT_DEF
  ; CHECK-NEXT:   %c:gr64 = INSERT_SUBREG %a, %b, %subreg.sub_32bit
  ; CHECK-NEXT:   JCC_1 %bb.2, 4, implicit undef $eflags
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   undef %a.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
  ; CHECK-NEXT:   %c.sub_32bit:gr64 = COPY %a
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   %c.sub_32bit:gr64 = SUBREG_TO_REG %a, %b, %subreg.sub_32bit
  ; CHECK-NEXT:   RET 0, implicit %c
  bb.0:
    liveins: $eax
    %init_eax:gr32 = COPY $eax
    %a:gr64 = SUBREG_TO_REG 0, %init_eax, %subreg.sub_32bit
    %b:gr32 = IMPLICIT_DEF
    %c:gr64 = INSERT_SUBREG %a, %b, %subreg.sub_32bit
    JCC_1 %bb.2, 4, implicit undef $eflags

  bb.1:
    %imm0:gr32 = MOV32r0 implicit-def dead $eflags
    %a = SUBREG_TO_REG 0, %imm0, %subreg.sub_32bit
    %c.sub_32bit = COPY %a

  bb.2:
    %c.sub_32bit = SUBREG_TO_REG %a, %b, %subreg.sub_32bit
    RET 0, implicit %c

...