llvm/test/CodeGen/Xtensa/inline-asm-mem-constraint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=xtensa < %s | FileCheck %s --check-prefix=XTENSA

define i32 @m_offset_0(ptr %p) nounwind {
; XTENSA-LABEL: m_offset_0:
; XTENSA:         #APP
; XTENSA-NEXT:    l32i a2, a2, 0
; XTENSA-NEXT:    #NO_APP
; XTENSA-NEXT:    ret
  %1 = call i32 asm "l32i $0, $1", "=r,*m"(ptr elementtype(i32) %p)
  ret i32 %1
}

define i32 @m_offset_1020(ptr %p) nounwind {
; XTENSA-LABEL: m_offset_1020:
; XTENSA:         #APP
; XTENSA-NEXT:    l32i a2, a2, 1020
; XTENSA-NEXT:    #NO_APP
; XTENSA-NEXT:    ret
  %1 = getelementptr inbounds i8, ptr %p, i32 1020
  %2 = call i32 asm "l32i $0, $1", "=r,*m"(ptr elementtype(i32) %1)
  ret i32 %2
}

define i8 @m_i8_offset_7(ptr %p) nounwind {
; XTENSA-LABEL: m_i8_offset_7:
; XTENSA:         addi a8, a2, 7
; XTENSA-NEXT:    #APP
; XTENSA-NEXT:    l8ui a2, a8, 0
; XTENSA-NEXT:    #NO_APP
; XTENSA-NEXT:    ret
  %1 = getelementptr inbounds i8, ptr %p, i32 7
  %2 = call i8 asm "l8ui $0, $1", "=r,*m"(ptr elementtype(i8) %1)
  ret i8 %2
}

define i16 @m_i16_offset_10(ptr %p) nounwind {
; XTENSA-LABEL: m_i16_offset_10:
; XTENSA:         #APP
; XTENSA-NEXT:    l16si a2, a2, 20
; XTENSA-NEXT:    #NO_APP
; XTENSA-NEXT:    ret
  %1 = getelementptr inbounds i16, ptr %p, i32 10
  %2 = call i16 asm "l16si $0, $1", "=r,*m"(ptr elementtype(i16) %1)
  ret i16 %2
}