llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=pwr7 < %s | FileCheck %s

; This piece of IR is expanded from memcmp.
define i1 @cmp(ptr %a, ptr %b) {
; CHECK-LABEL: cmp:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lwz 5, 4(3)
; CHECK-NEXT:    lwz 7, 0(3)
; CHECK-NEXT:    lwz 6, 4(4)
; CHECK-NEXT:    lwz 8, 0(4)
; CHECK-NEXT:    xor 9, 7, 8
; CHECK-NEXT:    xor 10, 5, 6
; CHECK-NEXT:    or. 9, 10, 9
; CHECK-NEXT:    bne 0, .LBB0_2
; CHECK-NEXT:  # %bb.1: # %loadbb1
; CHECK-NEXT:    lbz 3, 8(3)
; CHECK-NEXT:    lbz 4, 8(4)
; CHECK-NEXT:    sub 3, 3, 4
; CHECK-NEXT:    srwi 3, 3, 31
; CHECK-NEXT:    blr
; CHECK-NEXT:  .LBB0_2: # %res_block
; CHECK-NEXT:    cmplw 7, 8
; CHECK-NEXT:    cmplw 1, 5, 6
; CHECK-NEXT:    li 3, 1
; CHECK-NEXT:    li 4, -1
; CHECK-NEXT:    crandc 20, 0, 2
; CHECK-NEXT:    crand 21, 2, 4
; CHECK-NEXT:    cror 20, 21, 20
; CHECK-NEXT:    isel 3, 4, 3, 20
; CHECK-NEXT:    srwi 3, 3, 31
; CHECK-NEXT:    blr
entry:
  br label %loadbb

res_block:
  %0 = icmp ult i64 %4, %5
  %1 = select i1 %0, i32 -1, i32 1
  br label %endblock

loadbb:
  %2 = bitcast ptr %a to ptr
  %3 = bitcast ptr %b to ptr
  %4 = load i64, ptr %2, align 1
  %5 = load i64, ptr %3, align 1
  %6 = icmp eq i64 %4, %5
  br i1 %6, label %loadbb1, label %res_block

loadbb1:
  %7 = getelementptr i8, ptr %a, i64 8
  %8 = getelementptr i8, ptr %b, i64 8
  %9 = load i8, ptr %7, align 1
  %10 = load i8, ptr %8, align 1
  %11 = zext i8 %9 to i32
  %12 = zext i8 %10 to i32
  %13 = sub i32 %11, %12
  br label %endblock

endblock:
  %phi.res = phi i32 [ %13, %loadbb1 ], [ %1, %res_block ]
  %icmp = icmp slt i32 %phi.res, 0
  ret i1 %icmp
}