llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -mtriple=powerpc-unknown-unknown -run-pass=machine-cse -verify-machineinstrs | FileCheck %s
# RUN: llc %s -o - -mtriple=powerpc-unknown-unknown -passes=machine-cse | FileCheck %s
--- |
  define void @can_pre() {
  entry:
    br label %for.body

  for.body:
    br i1 undef, label %if.then, label %if.else

  if.then:
    br label %if.end

  if.else:
    br label %if.end

  if.end:
    br label %for.body
  }

  define void @cannot_pre() {
  entry:
    br label %for.body

  for.body:
    br i1 undef, label %if.then, label %if.else

  if.then:
    br label %if.end

  if.else:
    br label %if.end

  if.end:
    br label %for.body
  }
...
---
name: can_pre
registers:
  - { id: 0, class: f8rc, preferred-register: '' }
  - { id: 1, class: f8rc, preferred-register: '' }
  - { id: 2, class: gprc, preferred-register: '' }
  - { id: 3, class: gprc, preferred-register: '' }
  - { id: 4, class: f8rc, preferred-register: '' }
  - { id: 5, class: f8rc, preferred-register: '' }
liveins:
  - { reg: '$r1', virtual-reg: '%2' }
  - { reg: '$r2', virtual-reg: '%3' }
  - { reg: '$f1', virtual-reg: '%4' }
  - { reg: '$f2', virtual-reg: '%5' }
body:             |
  ; CHECK-LABEL: name: can_pre
  ; CHECK: bb.0.for.body:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $r1, $r2, $f1, $f2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:f8rc = COPY $f2
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:f8rc = COPY $f1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gprc = COPY $r2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gprc = COPY $r1
  ; CHECK-NEXT:   $cr0 = CMPLWI [[COPY3]], 0
  ; CHECK-NEXT:   %6:f8rc = nofpexcept FDIV [[COPY1]], [[COPY]], implicit $rm
  ; CHECK-NEXT:   BCC 44, $cr0, %bb.1
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.if.then:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.if.else:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3.if.end:
  ; CHECK-NEXT:   BLR implicit $lr, implicit $rm
  bb.0.for.body:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $r1, $r2, $f1, $f2

    %5:f8rc = COPY $f2
    %4:f8rc = COPY $f1
    %3:gprc = COPY $r2
    %2:gprc = COPY $r1
    $cr0 = CMPLWI %2, 0
    BCC 44, $cr0, %bb.1
    B %bb.2

  bb.1.if.then:
    successors: %bb.3(0x80000000)

    %0:f8rc = nofpexcept FDIV %4, %5, implicit $rm
    B %bb.3

  bb.2.if.else:
    successors: %bb.3(0x80000000)

    %1:f8rc = nofpexcept FDIV %4, %5, implicit $rm

  bb.3.if.end:
    BLR implicit $lr, implicit $rm
...
---
name: cannot_pre
registers:
  - { id: 0, class: f8rc, preferred-register: '' }
  - { id: 1, class: f8rc, preferred-register: '' }
  - { id: 2, class: gprc, preferred-register: '' }
  - { id: 3, class: gprc, preferred-register: '' }
  - { id: 4, class: f8rc, preferred-register: '' }
  - { id: 5, class: f8rc, preferred-register: '' }
  - { id: 6, class: f8rc, preferred-register: '' }
liveins:
  - { reg: '$r1', virtual-reg: '%2' }
  - { reg: '$r2', virtual-reg: '%3' }
  - { reg: '$f1', virtual-reg: '%4' }
  - { reg: '$f2', virtual-reg: '%5' }
body:             |
  ; CHECK-LABEL: name: cannot_pre
  ; CHECK: bb.0.for.body:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $r1, $r2, $f1, $f2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:f8rc = COPY $f2
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:f8rc = COPY $f1
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gprc = COPY $r2
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gprc = COPY $r1
  ; CHECK-NEXT:   $cr0 = CMPLWI [[COPY3]], 0
  ; CHECK-NEXT:   BCC 44, $cr0, %bb.1
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.if.then:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[SETRND:%[0-9]+]]:f8rc = SETRND [[COPY2]], implicit-def $rm, implicit $rm
  ; CHECK-NEXT:   %0:f8rc = nofpexcept FDIV [[COPY1]], [[COPY]], implicit $rm
  ; CHECK-NEXT:   B %bb.3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.if.else:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   %1:f8rc = nofpexcept FDIV [[COPY1]], [[COPY]], implicit $rm
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3.if.end:
  ; CHECK-NEXT:   BLR implicit $lr, implicit $rm
  bb.0.for.body:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $r1, $r2, $f1, $f2

    %5:f8rc = COPY $f2
    %4:f8rc = COPY $f1
    %3:gprc = COPY $r2
    %2:gprc = COPY $r1
    $cr0 = CMPLWI %2, 0
    BCC 44, $cr0, %bb.1
    B %bb.2

  bb.1.if.then:
    successors: %bb.3(0x80000000)

    %6:f8rc = SETRND %3, implicit-def $rm, implicit $rm
    %0:f8rc = nofpexcept FDIV %4, %5, implicit $rm
    B %bb.3

  bb.2.if.else:
    successors: %bb.3(0x80000000)

    %1:f8rc = nofpexcept FDIV %4, %5, implicit $rm

  bb.3.if.end:
    BLR implicit $lr, implicit $rm
...