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llvm/llvm-project/refs/heads/users/arsenm/codegen/remove-targetoptions-loopalignment/./llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
blob: ddee91e20f7dd080b6b43288421a4a441acb535c [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=SI %s
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefix=VI %s
; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define <24 x float> @bitcast_v24i32_to_v24f32(<24 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v24f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB0_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: .LBB0_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v24f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB0_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v23, vcc, 3, v23
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_add_u32_e32 v21, vcc, 3, v21
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_add_u32_e32 v19, vcc, 3, v19
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: .LBB0_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v24f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB0_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: .LBB0_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v24f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB0_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB0_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define inreg <24 x float> @bitcast_v24i32_to_v24f32_scalar(<24 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v24f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s7, v8
; SI-NEXT: v_readfirstlane_b32 s8, v7
; SI-NEXT: v_readfirstlane_b32 s9, v6
; SI-NEXT: v_readfirstlane_b32 s10, v5
; SI-NEXT: v_readfirstlane_b32 s11, v4
; SI-NEXT: v_readfirstlane_b32 s12, v3
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s15, v0
; SI-NEXT: s_cbranch_scc0 .LBB1_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB1_3
; SI-NEXT: .LBB1_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB1_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB1_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_add_i32 s7, s7, 3
; SI-NEXT: s_add_i32 s8, s8, 3
; SI-NEXT: s_add_i32 s9, s9, 3
; SI-NEXT: s_add_i32 s10, s10, 3
; SI-NEXT: s_add_i32 s11, s11, 3
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_add_i32 s14, s14, 3
; SI-NEXT: s_add_i32 s15, s15, 3
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: .LBB1_5: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s15
; SI-NEXT: v_mov_b32_e32 v15, s14
; SI-NEXT: v_mov_b32_e32 v16, s13
; SI-NEXT: v_mov_b32_e32 v17, s12
; SI-NEXT: v_mov_b32_e32 v18, s11
; SI-NEXT: v_mov_b32_e32 v19, s10
; SI-NEXT: v_mov_b32_e32 v20, s9
; SI-NEXT: v_mov_b32_e32 v21, s8
; SI-NEXT: v_mov_b32_e32 v22, s7
; SI-NEXT: v_mov_b32_e32 v23, s6
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v24f32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB1_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB1_3
; VI-NEXT: .LBB1_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB1_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB1_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s6, s6, 3
; VI-NEXT: s_add_i32 s7, s7, 3
; VI-NEXT: s_add_i32 s8, s8, 3
; VI-NEXT: s_add_i32 s9, s9, 3
; VI-NEXT: s_add_i32 s10, s10, 3
; VI-NEXT: s_add_i32 s11, s11, 3
; VI-NEXT: s_add_i32 s12, s12, 3
; VI-NEXT: s_add_i32 s13, s13, 3
; VI-NEXT: s_add_i32 s14, s14, 3
; VI-NEXT: s_add_i32 s15, s15, 3
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: .LBB1_5: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v24f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB1_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB1_3
; GFX9-NEXT: .LBB1_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB1_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB1_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s6, s6, 3
; GFX9-NEXT: s_add_i32 s7, s7, 3
; GFX9-NEXT: s_add_i32 s8, s8, 3
; GFX9-NEXT: s_add_i32 s9, s9, 3
; GFX9-NEXT: s_add_i32 s10, s10, 3
; GFX9-NEXT: s_add_i32 s11, s11, 3
; GFX9-NEXT: s_add_i32 s12, s12, 3
; GFX9-NEXT: s_add_i32 s13, s13, 3
; GFX9-NEXT: s_add_i32 s14, s14, 3
; GFX9-NEXT: s_add_i32 s15, s15, 3
; GFX9-NEXT: s_add_i32 s29, s29, 3
; GFX9-NEXT: s_add_i32 s28, s28, 3
; GFX9-NEXT: s_add_i32 s27, s27, 3
; GFX9-NEXT: s_add_i32 s26, s26, 3
; GFX9-NEXT: s_add_i32 s25, s25, 3
; GFX9-NEXT: s_add_i32 s24, s24, 3
; GFX9-NEXT: s_add_i32 s23, s23, 3
; GFX9-NEXT: s_add_i32 s22, s22, 3
; GFX9-NEXT: s_add_i32 s21, s21, 3
; GFX9-NEXT: s_add_i32 s20, s20, 3
; GFX9-NEXT: s_add_i32 s19, s19, 3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
; GFX9-NEXT: .LBB1_5: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v24f32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s10, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB1_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s10, -1
; GFX11-NEXT: .LBB1_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s10, s10, exec_lo
; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s10, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB1_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: s_add_i32 s4, s4, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
; GFX11-NEXT: s_add_i32 s6, s6, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s8, s8, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s29, s29, 3
; GFX11-NEXT: s_add_i32 s28, s28, 3
; GFX11-NEXT: s_add_i32 s27, s27, 3
; GFX11-NEXT: s_add_i32 s26, s26, 3
; GFX11-NEXT: s_add_i32 s25, s25, 3
; GFX11-NEXT: s_add_i32 s24, s24, 3
; GFX11-NEXT: s_add_i32 s23, s23, 3
; GFX11-NEXT: s_add_i32 s22, s22, 3
; GFX11-NEXT: s_add_i32 s21, s21, 3
; GFX11-NEXT: s_add_i32 s20, s20, 3
; GFX11-NEXT: s_add_i32 s19, s19, 3
; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s17, s17, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
; GFX11-NEXT: s_add_i32 s3, s3, 3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
; GFX11-NEXT: .LBB1_4: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define <24 x i32> @bitcast_v24f32_to_v24i32(<24 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v24i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB2_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v23, 1.0, v23
; SI-NEXT: v_add_f32_e32 v22, 1.0, v22
; SI-NEXT: v_add_f32_e32 v21, 1.0, v21
; SI-NEXT: v_add_f32_e32 v20, 1.0, v20
; SI-NEXT: v_add_f32_e32 v19, 1.0, v19
; SI-NEXT: v_add_f32_e32 v18, 1.0, v18
; SI-NEXT: v_add_f32_e32 v17, 1.0, v17
; SI-NEXT: v_add_f32_e32 v16, 1.0, v16
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
; SI-NEXT: .LBB2_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v24i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB2_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v23, 1.0, v23
; VI-NEXT: v_add_f32_e32 v22, 1.0, v22
; VI-NEXT: v_add_f32_e32 v21, 1.0, v21
; VI-NEXT: v_add_f32_e32 v20, 1.0, v20
; VI-NEXT: v_add_f32_e32 v19, 1.0, v19
; VI-NEXT: v_add_f32_e32 v18, 1.0, v18
; VI-NEXT: v_add_f32_e32 v17, 1.0, v17
; VI-NEXT: v_add_f32_e32 v16, 1.0, v16
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: .LBB2_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v24i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB2_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v23, 1.0, v23
; GFX9-NEXT: v_add_f32_e32 v22, 1.0, v22
; GFX9-NEXT: v_add_f32_e32 v21, 1.0, v21
; GFX9-NEXT: v_add_f32_e32 v20, 1.0, v20
; GFX9-NEXT: v_add_f32_e32 v19, 1.0, v19
; GFX9-NEXT: v_add_f32_e32 v18, 1.0, v18
; GFX9-NEXT: v_add_f32_e32 v17, 1.0, v17
; GFX9-NEXT: v_add_f32_e32 v16, 1.0, v16
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: .LBB2_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24f32_to_v24i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB2_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: .LBB2_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define inreg <24 x i32> @bitcast_v24f32_to_v24i32_scalar(<24 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v24i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s36, 0
; SI-NEXT: v_writelane_b32 v32, s37, 1
; SI-NEXT: v_writelane_b32 v32, s38, 2
; SI-NEXT: v_writelane_b32 v32, s39, 3
; SI-NEXT: v_writelane_b32 v32, s48, 4
; SI-NEXT: v_writelane_b32 v32, s49, 5
; SI-NEXT: v_writelane_b32 v32, s50, 6
; SI-NEXT: v_writelane_b32 v32, s51, 7
; SI-NEXT: v_writelane_b32 v32, s52, 8
; SI-NEXT: v_writelane_b32 v32, s53, 9
; SI-NEXT: v_writelane_b32 v32, s54, 10
; SI-NEXT: v_writelane_b32 v32, s55, 11
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_mov_b32 s49, s29
; SI-NEXT: s_mov_b32 s48, s28
; SI-NEXT: s_mov_b32 s47, s27
; SI-NEXT: s_mov_b32 s46, s26
; SI-NEXT: s_mov_b32 s45, s25
; SI-NEXT: s_mov_b32 s44, s24
; SI-NEXT: s_mov_b32 s43, s23
; SI-NEXT: s_mov_b32 s42, s22
; SI-NEXT: s_mov_b32 s41, s21
; SI-NEXT: s_mov_b32 s40, s20
; SI-NEXT: s_mov_b32 s39, s19
; SI-NEXT: s_mov_b32 s38, s18
; SI-NEXT: s_mov_b32 s37, s17
; SI-NEXT: s_mov_b32 s36, s16
; SI-NEXT: v_readfirstlane_b32 s59, v9
; SI-NEXT: v_readfirstlane_b32 s58, v8
; SI-NEXT: v_readfirstlane_b32 s57, v7
; SI-NEXT: v_readfirstlane_b32 s56, v6
; SI-NEXT: v_readfirstlane_b32 s55, v5
; SI-NEXT: v_readfirstlane_b32 s54, v4
; SI-NEXT: v_readfirstlane_b32 s53, v3
; SI-NEXT: v_readfirstlane_b32 s52, v2
; SI-NEXT: v_readfirstlane_b32 s51, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s50, v0
; SI-NEXT: s_cbranch_scc0 .LBB3_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB3_3
; SI-NEXT: .LBB3_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB3_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB3_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f32_e64 v23, s59, 1.0
; SI-NEXT: v_add_f32_e64 v22, s58, 1.0
; SI-NEXT: v_add_f32_e64 v21, s57, 1.0
; SI-NEXT: v_add_f32_e64 v20, s56, 1.0
; SI-NEXT: v_add_f32_e64 v19, s55, 1.0
; SI-NEXT: v_add_f32_e64 v18, s54, 1.0
; SI-NEXT: v_add_f32_e64 v17, s53, 1.0
; SI-NEXT: v_add_f32_e64 v16, s52, 1.0
; SI-NEXT: v_add_f32_e64 v15, s51, 1.0
; SI-NEXT: v_add_f32_e64 v14, s50, 1.0
; SI-NEXT: v_add_f32_e64 v13, s49, 1.0
; SI-NEXT: v_add_f32_e64 v12, s48, 1.0
; SI-NEXT: v_add_f32_e64 v11, s47, 1.0
; SI-NEXT: v_add_f32_e64 v10, s46, 1.0
; SI-NEXT: v_add_f32_e64 v9, s45, 1.0
; SI-NEXT: v_add_f32_e64 v8, s44, 1.0
; SI-NEXT: v_add_f32_e64 v7, s43, 1.0
; SI-NEXT: v_add_f32_e64 v6, s42, 1.0
; SI-NEXT: v_add_f32_e64 v5, s41, 1.0
; SI-NEXT: v_add_f32_e64 v4, s40, 1.0
; SI-NEXT: v_add_f32_e64 v3, s39, 1.0
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
; SI-NEXT: s_branch .LBB3_6
; SI-NEXT: .LBB3_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB3_6: ; %end
; SI-NEXT: v_readlane_b32 s55, v32, 11
; SI-NEXT: v_readlane_b32 s54, v32, 10
; SI-NEXT: v_readlane_b32 s53, v32, 9
; SI-NEXT: v_readlane_b32 s52, v32, 8
; SI-NEXT: v_readlane_b32 s51, v32, 7
; SI-NEXT: v_readlane_b32 s50, v32, 6
; SI-NEXT: v_readlane_b32 s49, v32, 5
; SI-NEXT: v_readlane_b32 s48, v32, 4
; SI-NEXT: v_readlane_b32 s39, v32, 3
; SI-NEXT: v_readlane_b32 s38, v32, 2
; SI-NEXT: v_readlane_b32 s37, v32, 1
; SI-NEXT: v_readlane_b32 s36, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v24i32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s36, 0
; VI-NEXT: v_writelane_b32 v32, s37, 1
; VI-NEXT: v_writelane_b32 v32, s38, 2
; VI-NEXT: v_writelane_b32 v32, s39, 3
; VI-NEXT: v_writelane_b32 v32, s48, 4
; VI-NEXT: v_writelane_b32 v32, s49, 5
; VI-NEXT: v_writelane_b32 v32, s50, 6
; VI-NEXT: v_writelane_b32 v32, s51, 7
; VI-NEXT: v_writelane_b32 v32, s52, 8
; VI-NEXT: v_writelane_b32 v32, s53, 9
; VI-NEXT: v_writelane_b32 v32, s54, 10
; VI-NEXT: v_writelane_b32 v32, s55, 11
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_mov_b32 s49, s29
; VI-NEXT: s_mov_b32 s48, s28
; VI-NEXT: s_mov_b32 s47, s27
; VI-NEXT: s_mov_b32 s46, s26
; VI-NEXT: s_mov_b32 s45, s25
; VI-NEXT: s_mov_b32 s44, s24
; VI-NEXT: s_mov_b32 s43, s23
; VI-NEXT: s_mov_b32 s42, s22
; VI-NEXT: s_mov_b32 s41, s21
; VI-NEXT: s_mov_b32 s40, s20
; VI-NEXT: s_mov_b32 s39, s19
; VI-NEXT: s_mov_b32 s38, s18
; VI-NEXT: s_mov_b32 s37, s17
; VI-NEXT: s_mov_b32 s36, s16
; VI-NEXT: v_readfirstlane_b32 s59, v9
; VI-NEXT: v_readfirstlane_b32 s58, v8
; VI-NEXT: v_readfirstlane_b32 s57, v7
; VI-NEXT: v_readfirstlane_b32 s56, v6
; VI-NEXT: v_readfirstlane_b32 s55, v5
; VI-NEXT: v_readfirstlane_b32 s54, v4
; VI-NEXT: v_readfirstlane_b32 s53, v3
; VI-NEXT: v_readfirstlane_b32 s52, v2
; VI-NEXT: v_readfirstlane_b32 s51, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s50, v0
; VI-NEXT: s_cbranch_scc0 .LBB3_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB3_3
; VI-NEXT: .LBB3_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB3_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB3_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f32_e64 v23, s59, 1.0
; VI-NEXT: v_add_f32_e64 v22, s58, 1.0
; VI-NEXT: v_add_f32_e64 v21, s57, 1.0
; VI-NEXT: v_add_f32_e64 v20, s56, 1.0
; VI-NEXT: v_add_f32_e64 v19, s55, 1.0
; VI-NEXT: v_add_f32_e64 v18, s54, 1.0
; VI-NEXT: v_add_f32_e64 v17, s53, 1.0
; VI-NEXT: v_add_f32_e64 v16, s52, 1.0
; VI-NEXT: v_add_f32_e64 v15, s51, 1.0
; VI-NEXT: v_add_f32_e64 v14, s50, 1.0
; VI-NEXT: v_add_f32_e64 v13, s49, 1.0
; VI-NEXT: v_add_f32_e64 v12, s48, 1.0
; VI-NEXT: v_add_f32_e64 v11, s47, 1.0
; VI-NEXT: v_add_f32_e64 v10, s46, 1.0
; VI-NEXT: v_add_f32_e64 v9, s45, 1.0
; VI-NEXT: v_add_f32_e64 v8, s44, 1.0
; VI-NEXT: v_add_f32_e64 v7, s43, 1.0
; VI-NEXT: v_add_f32_e64 v6, s42, 1.0
; VI-NEXT: v_add_f32_e64 v5, s41, 1.0
; VI-NEXT: v_add_f32_e64 v4, s40, 1.0
; VI-NEXT: v_add_f32_e64 v3, s39, 1.0
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
; VI-NEXT: s_branch .LBB3_6
; VI-NEXT: .LBB3_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB3_6: ; %end
; VI-NEXT: v_readlane_b32 s55, v32, 11
; VI-NEXT: v_readlane_b32 s54, v32, 10
; VI-NEXT: v_readlane_b32 s53, v32, 9
; VI-NEXT: v_readlane_b32 s52, v32, 8
; VI-NEXT: v_readlane_b32 s51, v32, 7
; VI-NEXT: v_readlane_b32 s50, v32, 6
; VI-NEXT: v_readlane_b32 s49, v32, 5
; VI-NEXT: v_readlane_b32 s48, v32, 4
; VI-NEXT: v_readlane_b32 s39, v32, 3
; VI-NEXT: v_readlane_b32 s38, v32, 2
; VI-NEXT: v_readlane_b32 s37, v32, 1
; VI-NEXT: v_readlane_b32 s36, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v24i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_mov_b32 s49, s29
; GFX9-NEXT: s_mov_b32 s48, s28
; GFX9-NEXT: s_mov_b32 s47, s27
; GFX9-NEXT: s_mov_b32 s46, s26
; GFX9-NEXT: s_mov_b32 s45, s25
; GFX9-NEXT: s_mov_b32 s44, s24
; GFX9-NEXT: s_mov_b32 s43, s23
; GFX9-NEXT: s_mov_b32 s42, s22
; GFX9-NEXT: s_mov_b32 s41, s21
; GFX9-NEXT: s_mov_b32 s40, s20
; GFX9-NEXT: s_mov_b32 s39, s19
; GFX9-NEXT: s_mov_b32 s38, s18
; GFX9-NEXT: s_mov_b32 s37, s17
; GFX9-NEXT: s_mov_b32 s36, s16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s55, v5
; GFX9-NEXT: v_readfirstlane_b32 s54, v4
; GFX9-NEXT: v_readfirstlane_b32 s53, v3
; GFX9-NEXT: v_readfirstlane_b32 s52, v2
; GFX9-NEXT: v_readfirstlane_b32 s51, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s50, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB3_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB3_3
; GFX9-NEXT: .LBB3_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB3_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB3_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e64 v23, s59, 1.0
; GFX9-NEXT: v_add_f32_e64 v22, s58, 1.0
; GFX9-NEXT: v_add_f32_e64 v21, s57, 1.0
; GFX9-NEXT: v_add_f32_e64 v20, s56, 1.0
; GFX9-NEXT: v_add_f32_e64 v19, s55, 1.0
; GFX9-NEXT: v_add_f32_e64 v18, s54, 1.0
; GFX9-NEXT: v_add_f32_e64 v17, s53, 1.0
; GFX9-NEXT: v_add_f32_e64 v16, s52, 1.0
; GFX9-NEXT: v_add_f32_e64 v15, s51, 1.0
; GFX9-NEXT: v_add_f32_e64 v14, s50, 1.0
; GFX9-NEXT: v_add_f32_e64 v13, s49, 1.0
; GFX9-NEXT: v_add_f32_e64 v12, s48, 1.0
; GFX9-NEXT: v_add_f32_e64 v11, s47, 1.0
; GFX9-NEXT: v_add_f32_e64 v10, s46, 1.0
; GFX9-NEXT: v_add_f32_e64 v9, s45, 1.0
; GFX9-NEXT: v_add_f32_e64 v8, s44, 1.0
; GFX9-NEXT: v_add_f32_e64 v7, s43, 1.0
; GFX9-NEXT: v_add_f32_e64 v6, s42, 1.0
; GFX9-NEXT: v_add_f32_e64 v5, s41, 1.0
; GFX9-NEXT: v_add_f32_e64 v4, s40, 1.0
; GFX9-NEXT: v_add_f32_e64 v3, s39, 1.0
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
; GFX9-NEXT: s_branch .LBB3_6
; GFX9-NEXT: .LBB3_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB3_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24f32_to_v24i32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: v_writelane_b32 v32, s39, 3
; GFX11-NEXT: v_writelane_b32 v32, s48, 4
; GFX11-NEXT: v_writelane_b32 v32, s49, 5
; GFX11-NEXT: v_writelane_b32 v32, s50, 6
; GFX11-NEXT: v_writelane_b32 v32, s51, 7
; GFX11-NEXT: v_writelane_b32 v32, s52, 8
; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_writelane_b32 v32, s54, 10
; GFX11-NEXT: v_writelane_b32 v32, s55, 11
; GFX11-NEXT: s_mov_b32 s36, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
; GFX11-NEXT: v_readfirstlane_b32 s59, v5
; GFX11-NEXT: v_readfirstlane_b32 s58, v4
; GFX11-NEXT: v_readfirstlane_b32 s57, v3
; GFX11-NEXT: v_readfirstlane_b32 s56, v2
; GFX11-NEXT: v_readfirstlane_b32 s55, v1
; GFX11-NEXT: v_readfirstlane_b32 s54, v0
; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_mov_b32 s52, s28
; GFX11-NEXT: s_mov_b32 s51, s27
; GFX11-NEXT: s_mov_b32 s50, s26
; GFX11-NEXT: s_mov_b32 s49, s25
; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
; GFX11-NEXT: s_mov_b32 s40, s16
; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB3_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: .LBB3_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB3_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_f32_e64 v23, s59, 1.0
; GFX11-NEXT: v_add_f32_e64 v22, s58, 1.0
; GFX11-NEXT: v_add_f32_e64 v21, s57, 1.0
; GFX11-NEXT: v_add_f32_e64 v20, s56, 1.0
; GFX11-NEXT: v_add_f32_e64 v19, s55, 1.0
; GFX11-NEXT: v_add_f32_e64 v18, s54, 1.0
; GFX11-NEXT: v_add_f32_e64 v17, s53, 1.0
; GFX11-NEXT: v_add_f32_e64 v16, s52, 1.0
; GFX11-NEXT: v_add_f32_e64 v15, s51, 1.0
; GFX11-NEXT: v_add_f32_e64 v14, s50, 1.0
; GFX11-NEXT: v_add_f32_e64 v13, s49, 1.0
; GFX11-NEXT: v_add_f32_e64 v12, s48, 1.0
; GFX11-NEXT: v_add_f32_e64 v11, s47, 1.0
; GFX11-NEXT: v_add_f32_e64 v10, s46, 1.0
; GFX11-NEXT: v_add_f32_e64 v9, s45, 1.0
; GFX11-NEXT: v_add_f32_e64 v8, s44, 1.0
; GFX11-NEXT: v_add_f32_e64 v7, s43, 1.0
; GFX11-NEXT: v_add_f32_e64 v6, s42, 1.0
; GFX11-NEXT: v_add_f32_e64 v5, s41, 1.0
; GFX11-NEXT: v_add_f32_e64 v4, s40, 1.0
; GFX11-NEXT: v_add_f32_e64 v3, s39, 1.0
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
; GFX11-NEXT: s_branch .LBB3_5
; GFX11-NEXT: .LBB3_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v1, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v3, s39
; GFX11-NEXT: v_dual_mov_b32 v4, s40 :: v_dual_mov_b32 v5, s41
; GFX11-NEXT: v_dual_mov_b32 v6, s42 :: v_dual_mov_b32 v7, s43
; GFX11-NEXT: v_dual_mov_b32 v8, s44 :: v_dual_mov_b32 v9, s45
; GFX11-NEXT: v_dual_mov_b32 v10, s46 :: v_dual_mov_b32 v11, s47
; GFX11-NEXT: v_dual_mov_b32 v12, s48 :: v_dual_mov_b32 v13, s49
; GFX11-NEXT: v_dual_mov_b32 v14, s50 :: v_dual_mov_b32 v15, s51
; GFX11-NEXT: v_dual_mov_b32 v16, s52 :: v_dual_mov_b32 v17, s53
; GFX11-NEXT: v_dual_mov_b32 v18, s54 :: v_dual_mov_b32 v19, s55
; GFX11-NEXT: v_dual_mov_b32 v20, s56 :: v_dual_mov_b32 v21, s57
; GFX11-NEXT: v_dual_mov_b32 v22, s58 :: v_dual_mov_b32 v23, s59
; GFX11-NEXT: v_dual_mov_b32 v24, s60 :: v_dual_mov_b32 v25, s61
; GFX11-NEXT: v_dual_mov_b32 v26, s62 :: v_dual_mov_b32 v27, s63
; GFX11-NEXT: v_dual_mov_b32 v28, s64 :: v_dual_mov_b32 v29, s65
; GFX11-NEXT: v_dual_mov_b32 v30, s66 :: v_dual_mov_b32 v31, s67
; GFX11-NEXT: .LBB3_5: ; %end
; GFX11-NEXT: v_readlane_b32 s55, v32, 11
; GFX11-NEXT: v_readlane_b32 s54, v32, 10
; GFX11-NEXT: v_readlane_b32 s53, v32, 9
; GFX11-NEXT: v_readlane_b32 s52, v32, 8
; GFX11-NEXT: v_readlane_b32 s51, v32, 7
; GFX11-NEXT: v_readlane_b32 s50, v32, 6
; GFX11-NEXT: v_readlane_b32 s49, v32, 5
; GFX11-NEXT: v_readlane_b32 s48, v32, 4
; GFX11-NEXT: v_readlane_b32 s39, v32, 3
; GFX11-NEXT: v_readlane_b32 s38, v32, 2
; GFX11-NEXT: v_readlane_b32 s37, v32, 1
; GFX11-NEXT: v_readlane_b32 s36, v32, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v32, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define <12 x i64> @bitcast_v24i32_to_v12i64(<24 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v12i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB4_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: .LBB4_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v12i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB4_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v23, vcc, 3, v23
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_add_u32_e32 v21, vcc, 3, v21
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_add_u32_e32 v19, vcc, 3, v19
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: .LBB4_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v12i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB4_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: .LBB4_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v12i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB4_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB4_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define inreg <12 x i64> @bitcast_v24i32_to_v12i64_scalar(<24 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v12i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s7, v8
; SI-NEXT: v_readfirstlane_b32 s8, v7
; SI-NEXT: v_readfirstlane_b32 s9, v6
; SI-NEXT: v_readfirstlane_b32 s10, v5
; SI-NEXT: v_readfirstlane_b32 s11, v4
; SI-NEXT: v_readfirstlane_b32 s12, v3
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s15, v0
; SI-NEXT: s_cbranch_scc0 .LBB5_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB5_3
; SI-NEXT: .LBB5_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB5_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB5_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_add_i32 s7, s7, 3
; SI-NEXT: s_add_i32 s8, s8, 3
; SI-NEXT: s_add_i32 s9, s9, 3
; SI-NEXT: s_add_i32 s10, s10, 3
; SI-NEXT: s_add_i32 s11, s11, 3
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_add_i32 s14, s14, 3
; SI-NEXT: s_add_i32 s15, s15, 3
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: .LBB5_5: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s15
; SI-NEXT: v_mov_b32_e32 v15, s14
; SI-NEXT: v_mov_b32_e32 v16, s13
; SI-NEXT: v_mov_b32_e32 v17, s12
; SI-NEXT: v_mov_b32_e32 v18, s11
; SI-NEXT: v_mov_b32_e32 v19, s10
; SI-NEXT: v_mov_b32_e32 v20, s9
; SI-NEXT: v_mov_b32_e32 v21, s8
; SI-NEXT: v_mov_b32_e32 v22, s7
; SI-NEXT: v_mov_b32_e32 v23, s6
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v12i64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB5_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB5_3
; VI-NEXT: .LBB5_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB5_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB5_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s6, s6, 3
; VI-NEXT: s_add_i32 s7, s7, 3
; VI-NEXT: s_add_i32 s8, s8, 3
; VI-NEXT: s_add_i32 s9, s9, 3
; VI-NEXT: s_add_i32 s10, s10, 3
; VI-NEXT: s_add_i32 s11, s11, 3
; VI-NEXT: s_add_i32 s12, s12, 3
; VI-NEXT: s_add_i32 s13, s13, 3
; VI-NEXT: s_add_i32 s14, s14, 3
; VI-NEXT: s_add_i32 s15, s15, 3
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: .LBB5_5: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v12i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB5_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB5_3
; GFX9-NEXT: .LBB5_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB5_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB5_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s6, s6, 3
; GFX9-NEXT: s_add_i32 s7, s7, 3
; GFX9-NEXT: s_add_i32 s8, s8, 3
; GFX9-NEXT: s_add_i32 s9, s9, 3
; GFX9-NEXT: s_add_i32 s10, s10, 3
; GFX9-NEXT: s_add_i32 s11, s11, 3
; GFX9-NEXT: s_add_i32 s12, s12, 3
; GFX9-NEXT: s_add_i32 s13, s13, 3
; GFX9-NEXT: s_add_i32 s14, s14, 3
; GFX9-NEXT: s_add_i32 s15, s15, 3
; GFX9-NEXT: s_add_i32 s29, s29, 3
; GFX9-NEXT: s_add_i32 s28, s28, 3
; GFX9-NEXT: s_add_i32 s27, s27, 3
; GFX9-NEXT: s_add_i32 s26, s26, 3
; GFX9-NEXT: s_add_i32 s25, s25, 3
; GFX9-NEXT: s_add_i32 s24, s24, 3
; GFX9-NEXT: s_add_i32 s23, s23, 3
; GFX9-NEXT: s_add_i32 s22, s22, 3
; GFX9-NEXT: s_add_i32 s21, s21, 3
; GFX9-NEXT: s_add_i32 s20, s20, 3
; GFX9-NEXT: s_add_i32 s19, s19, 3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
; GFX9-NEXT: .LBB5_5: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v12i64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s10, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB5_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s10, -1
; GFX11-NEXT: .LBB5_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s10, s10, exec_lo
; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s10, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB5_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: s_add_i32 s4, s4, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
; GFX11-NEXT: s_add_i32 s6, s6, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s8, s8, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s29, s29, 3
; GFX11-NEXT: s_add_i32 s28, s28, 3
; GFX11-NEXT: s_add_i32 s27, s27, 3
; GFX11-NEXT: s_add_i32 s26, s26, 3
; GFX11-NEXT: s_add_i32 s25, s25, 3
; GFX11-NEXT: s_add_i32 s24, s24, 3
; GFX11-NEXT: s_add_i32 s23, s23, 3
; GFX11-NEXT: s_add_i32 s22, s22, 3
; GFX11-NEXT: s_add_i32 s21, s21, 3
; GFX11-NEXT: s_add_i32 s20, s20, 3
; GFX11-NEXT: s_add_i32 s19, s19, 3
; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s17, s17, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
; GFX11-NEXT: s_add_i32 s3, s3, 3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
; GFX11-NEXT: .LBB5_4: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define <24 x i32> @bitcast_v12i64_to_v24i32(<12 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v24i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB6_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: .LBB6_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v24i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB6_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: .LBB6_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v24i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB6_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, 3, v22
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v23, vcc
; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, 3, v20
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, 3, v18
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, 3, v16
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: .LBB6_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v24i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB6_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
; GFX11-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: .LBB6_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define inreg <24 x i32> @bitcast_v12i64_to_v24i32_scalar(<12 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v24i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s7, v8
; SI-NEXT: v_readfirstlane_b32 s8, v7
; SI-NEXT: v_readfirstlane_b32 s9, v6
; SI-NEXT: v_readfirstlane_b32 s10, v5
; SI-NEXT: v_readfirstlane_b32 s11, v4
; SI-NEXT: v_readfirstlane_b32 s12, v3
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s15, v0
; SI-NEXT: s_cbranch_scc0 .LBB7_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB7_3
; SI-NEXT: .LBB7_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB7_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB7_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
; SI-NEXT: s_add_u32 s9, s9, 3
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s11, s11, 3
; SI-NEXT: s_addc_u32 s10, s10, 0
; SI-NEXT: s_add_u32 s13, s13, 3
; SI-NEXT: s_addc_u32 s12, s12, 0
; SI-NEXT: s_add_u32 s15, s15, 3
; SI-NEXT: s_addc_u32 s14, s14, 0
; SI-NEXT: s_add_u32 s28, s28, 3
; SI-NEXT: s_addc_u32 s29, s29, 0
; SI-NEXT: s_add_u32 s26, s26, 3
; SI-NEXT: s_addc_u32 s27, s27, 0
; SI-NEXT: s_add_u32 s24, s24, 3
; SI-NEXT: s_addc_u32 s25, s25, 0
; SI-NEXT: s_add_u32 s22, s22, 3
; SI-NEXT: s_addc_u32 s23, s23, 0
; SI-NEXT: s_add_u32 s20, s20, 3
; SI-NEXT: s_addc_u32 s21, s21, 0
; SI-NEXT: s_add_u32 s18, s18, 3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
; SI-NEXT: .LBB7_5: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s15
; SI-NEXT: v_mov_b32_e32 v15, s14
; SI-NEXT: v_mov_b32_e32 v16, s13
; SI-NEXT: v_mov_b32_e32 v17, s12
; SI-NEXT: v_mov_b32_e32 v18, s11
; SI-NEXT: v_mov_b32_e32 v19, s10
; SI-NEXT: v_mov_b32_e32 v20, s9
; SI-NEXT: v_mov_b32_e32 v21, s8
; SI-NEXT: v_mov_b32_e32 v22, s7
; SI-NEXT: v_mov_b32_e32 v23, s6
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v24i32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB7_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB7_3
; VI-NEXT: .LBB7_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB7_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB7_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
; VI-NEXT: s_add_u32 s9, s9, 3
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s11, s11, 3
; VI-NEXT: s_addc_u32 s10, s10, 0
; VI-NEXT: s_add_u32 s13, s13, 3
; VI-NEXT: s_addc_u32 s12, s12, 0
; VI-NEXT: s_add_u32 s15, s15, 3
; VI-NEXT: s_addc_u32 s14, s14, 0
; VI-NEXT: s_add_u32 s28, s28, 3
; VI-NEXT: s_addc_u32 s29, s29, 0
; VI-NEXT: s_add_u32 s26, s26, 3
; VI-NEXT: s_addc_u32 s27, s27, 0
; VI-NEXT: s_add_u32 s24, s24, 3
; VI-NEXT: s_addc_u32 s25, s25, 0
; VI-NEXT: s_add_u32 s22, s22, 3
; VI-NEXT: s_addc_u32 s23, s23, 0
; VI-NEXT: s_add_u32 s20, s20, 3
; VI-NEXT: s_addc_u32 s21, s21, 0
; VI-NEXT: s_add_u32 s18, s18, 3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
; VI-NEXT: .LBB7_5: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v24i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB7_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB7_3
; GFX9-NEXT: .LBB7_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB7_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB7_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
; GFX9-NEXT: s_add_u32 s9, s9, 3
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s11, s11, 3
; GFX9-NEXT: s_addc_u32 s10, s10, 0
; GFX9-NEXT: s_add_u32 s13, s13, 3
; GFX9-NEXT: s_addc_u32 s12, s12, 0
; GFX9-NEXT: s_add_u32 s15, s15, 3
; GFX9-NEXT: s_addc_u32 s14, s14, 0
; GFX9-NEXT: s_add_u32 s28, s28, 3
; GFX9-NEXT: s_addc_u32 s29, s29, 0
; GFX9-NEXT: s_add_u32 s26, s26, 3
; GFX9-NEXT: s_addc_u32 s27, s27, 0
; GFX9-NEXT: s_add_u32 s24, s24, 3
; GFX9-NEXT: s_addc_u32 s25, s25, 0
; GFX9-NEXT: s_add_u32 s22, s22, 3
; GFX9-NEXT: s_addc_u32 s23, s23, 0
; GFX9-NEXT: s_add_u32 s20, s20, 3
; GFX9-NEXT: s_addc_u32 s21, s21, 0
; GFX9-NEXT: s_add_u32 s18, s18, 3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
; GFX9-NEXT: .LBB7_5: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v24i32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s10, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB7_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s10, -1
; GFX11-NEXT: .LBB7_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s10, s10, exec_lo
; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s10, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB7_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
; GFX11-NEXT: s_add_u32 s7, s7, 3
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s9, s9, 3
; GFX11-NEXT: s_addc_u32 s8, s8, 0
; GFX11-NEXT: s_add_u32 s28, s28, 3
; GFX11-NEXT: s_addc_u32 s29, s29, 0
; GFX11-NEXT: s_add_u32 s26, s26, 3
; GFX11-NEXT: s_addc_u32 s27, s27, 0
; GFX11-NEXT: s_add_u32 s24, s24, 3
; GFX11-NEXT: s_addc_u32 s25, s25, 0
; GFX11-NEXT: s_add_u32 s22, s22, 3
; GFX11-NEXT: s_addc_u32 s23, s23, 0
; GFX11-NEXT: s_add_u32 s20, s20, 3
; GFX11-NEXT: s_addc_u32 s21, s21, 0
; GFX11-NEXT: s_add_u32 s18, s18, 3
; GFX11-NEXT: s_addc_u32 s19, s19, 0
; GFX11-NEXT: s_add_u32 s16, s16, 3
; GFX11-NEXT: s_addc_u32 s17, s17, 0
; GFX11-NEXT: s_add_u32 s2, s2, 3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: .LBB7_4: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define <12 x double> @bitcast_v24i32_to_v12f64(<24 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v12f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB8_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: .LBB8_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v12f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB8_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v23, vcc, 3, v23
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_add_u32_e32 v21, vcc, 3, v21
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_add_u32_e32 v19, vcc, 3, v19
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: .LBB8_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v12f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB8_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: .LBB8_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v12f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB8_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-NEXT: .LBB8_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define inreg <12 x double> @bitcast_v24i32_to_v12f64_scalar(<24 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v12f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s7, v8
; SI-NEXT: v_readfirstlane_b32 s8, v7
; SI-NEXT: v_readfirstlane_b32 s9, v6
; SI-NEXT: v_readfirstlane_b32 s10, v5
; SI-NEXT: v_readfirstlane_b32 s11, v4
; SI-NEXT: v_readfirstlane_b32 s12, v3
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s15, v0
; SI-NEXT: s_cbranch_scc0 .LBB9_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB9_3
; SI-NEXT: .LBB9_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB9_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB9_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_add_i32 s7, s7, 3
; SI-NEXT: s_add_i32 s8, s8, 3
; SI-NEXT: s_add_i32 s9, s9, 3
; SI-NEXT: s_add_i32 s10, s10, 3
; SI-NEXT: s_add_i32 s11, s11, 3
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_add_i32 s14, s14, 3
; SI-NEXT: s_add_i32 s15, s15, 3
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: .LBB9_5: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s15
; SI-NEXT: v_mov_b32_e32 v15, s14
; SI-NEXT: v_mov_b32_e32 v16, s13
; SI-NEXT: v_mov_b32_e32 v17, s12
; SI-NEXT: v_mov_b32_e32 v18, s11
; SI-NEXT: v_mov_b32_e32 v19, s10
; SI-NEXT: v_mov_b32_e32 v20, s9
; SI-NEXT: v_mov_b32_e32 v21, s8
; SI-NEXT: v_mov_b32_e32 v22, s7
; SI-NEXT: v_mov_b32_e32 v23, s6
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v12f64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB9_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB9_3
; VI-NEXT: .LBB9_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB9_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB9_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s6, s6, 3
; VI-NEXT: s_add_i32 s7, s7, 3
; VI-NEXT: s_add_i32 s8, s8, 3
; VI-NEXT: s_add_i32 s9, s9, 3
; VI-NEXT: s_add_i32 s10, s10, 3
; VI-NEXT: s_add_i32 s11, s11, 3
; VI-NEXT: s_add_i32 s12, s12, 3
; VI-NEXT: s_add_i32 s13, s13, 3
; VI-NEXT: s_add_i32 s14, s14, 3
; VI-NEXT: s_add_i32 s15, s15, 3
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: .LBB9_5: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v12f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB9_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB9_3
; GFX9-NEXT: .LBB9_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB9_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB9_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s6, s6, 3
; GFX9-NEXT: s_add_i32 s7, s7, 3
; GFX9-NEXT: s_add_i32 s8, s8, 3
; GFX9-NEXT: s_add_i32 s9, s9, 3
; GFX9-NEXT: s_add_i32 s10, s10, 3
; GFX9-NEXT: s_add_i32 s11, s11, 3
; GFX9-NEXT: s_add_i32 s12, s12, 3
; GFX9-NEXT: s_add_i32 s13, s13, 3
; GFX9-NEXT: s_add_i32 s14, s14, 3
; GFX9-NEXT: s_add_i32 s15, s15, 3
; GFX9-NEXT: s_add_i32 s29, s29, 3
; GFX9-NEXT: s_add_i32 s28, s28, 3
; GFX9-NEXT: s_add_i32 s27, s27, 3
; GFX9-NEXT: s_add_i32 s26, s26, 3
; GFX9-NEXT: s_add_i32 s25, s25, 3
; GFX9-NEXT: s_add_i32 s24, s24, 3
; GFX9-NEXT: s_add_i32 s23, s23, 3
; GFX9-NEXT: s_add_i32 s22, s22, 3
; GFX9-NEXT: s_add_i32 s21, s21, 3
; GFX9-NEXT: s_add_i32 s20, s20, 3
; GFX9-NEXT: s_add_i32 s19, s19, 3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
; GFX9-NEXT: .LBB9_5: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v12f64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s10, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB9_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s10, -1
; GFX11-NEXT: .LBB9_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s10, s10, exec_lo
; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s10, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB9_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: s_add_i32 s4, s4, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
; GFX11-NEXT: s_add_i32 s6, s6, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s8, s8, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s29, s29, 3
; GFX11-NEXT: s_add_i32 s28, s28, 3
; GFX11-NEXT: s_add_i32 s27, s27, 3
; GFX11-NEXT: s_add_i32 s26, s26, 3
; GFX11-NEXT: s_add_i32 s25, s25, 3
; GFX11-NEXT: s_add_i32 s24, s24, 3
; GFX11-NEXT: s_add_i32 s23, s23, 3
; GFX11-NEXT: s_add_i32 s22, s22, 3
; GFX11-NEXT: s_add_i32 s21, s21, 3
; GFX11-NEXT: s_add_i32 s20, s20, 3
; GFX11-NEXT: s_add_i32 s19, s19, 3
; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s17, s17, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
; GFX11-NEXT: s_add_i32 s3, s3, 3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
; GFX11-NEXT: .LBB9_4: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define <24 x i32> @bitcast_v12f64_to_v24i32(<12 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v24i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB10_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT: .LBB10_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v24i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB10_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: .LBB10_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v24i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB10_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: .LBB10_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12f64_to_v24i32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB10_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: .LBB10_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define inreg <24 x i32> @bitcast_v12f64_to_v24i32_scalar(<12 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v24i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s36, 0
; SI-NEXT: v_writelane_b32 v32, s37, 1
; SI-NEXT: v_writelane_b32 v32, s38, 2
; SI-NEXT: v_writelane_b32 v32, s39, 3
; SI-NEXT: v_writelane_b32 v32, s48, 4
; SI-NEXT: v_writelane_b32 v32, s49, 5
; SI-NEXT: v_writelane_b32 v32, s50, 6
; SI-NEXT: v_writelane_b32 v32, s51, 7
; SI-NEXT: v_writelane_b32 v32, s52, 8
; SI-NEXT: v_writelane_b32 v32, s53, 9
; SI-NEXT: v_writelane_b32 v32, s54, 10
; SI-NEXT: v_writelane_b32 v32, s55, 11
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_mov_b32 s49, s29
; SI-NEXT: s_mov_b32 s48, s28
; SI-NEXT: s_mov_b32 s47, s27
; SI-NEXT: s_mov_b32 s46, s26
; SI-NEXT: s_mov_b32 s45, s25
; SI-NEXT: s_mov_b32 s44, s24
; SI-NEXT: s_mov_b32 s43, s23
; SI-NEXT: s_mov_b32 s42, s22
; SI-NEXT: s_mov_b32 s41, s21
; SI-NEXT: s_mov_b32 s40, s20
; SI-NEXT: s_mov_b32 s39, s19
; SI-NEXT: s_mov_b32 s38, s18
; SI-NEXT: s_mov_b32 s37, s17
; SI-NEXT: s_mov_b32 s36, s16
; SI-NEXT: v_readfirstlane_b32 s59, v9
; SI-NEXT: v_readfirstlane_b32 s58, v8
; SI-NEXT: v_readfirstlane_b32 s57, v7
; SI-NEXT: v_readfirstlane_b32 s56, v6
; SI-NEXT: v_readfirstlane_b32 s55, v5
; SI-NEXT: v_readfirstlane_b32 s54, v4
; SI-NEXT: v_readfirstlane_b32 s53, v3
; SI-NEXT: v_readfirstlane_b32 s52, v2
; SI-NEXT: v_readfirstlane_b32 s51, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s50, v0
; SI-NEXT: s_cbranch_scc0 .LBB11_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB11_3
; SI-NEXT: .LBB11_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB11_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB11_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; SI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; SI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; SI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; SI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; SI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; SI-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; SI-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; SI-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; SI-NEXT: s_branch .LBB11_6
; SI-NEXT: .LBB11_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB11_6: ; %end
; SI-NEXT: v_readlane_b32 s55, v32, 11
; SI-NEXT: v_readlane_b32 s54, v32, 10
; SI-NEXT: v_readlane_b32 s53, v32, 9
; SI-NEXT: v_readlane_b32 s52, v32, 8
; SI-NEXT: v_readlane_b32 s51, v32, 7
; SI-NEXT: v_readlane_b32 s50, v32, 6
; SI-NEXT: v_readlane_b32 s49, v32, 5
; SI-NEXT: v_readlane_b32 s48, v32, 4
; SI-NEXT: v_readlane_b32 s39, v32, 3
; SI-NEXT: v_readlane_b32 s38, v32, 2
; SI-NEXT: v_readlane_b32 s37, v32, 1
; SI-NEXT: v_readlane_b32 s36, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v24i32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s36, 0
; VI-NEXT: v_writelane_b32 v32, s37, 1
; VI-NEXT: v_writelane_b32 v32, s38, 2
; VI-NEXT: v_writelane_b32 v32, s39, 3
; VI-NEXT: v_writelane_b32 v32, s48, 4
; VI-NEXT: v_writelane_b32 v32, s49, 5
; VI-NEXT: v_writelane_b32 v32, s50, 6
; VI-NEXT: v_writelane_b32 v32, s51, 7
; VI-NEXT: v_writelane_b32 v32, s52, 8
; VI-NEXT: v_writelane_b32 v32, s53, 9
; VI-NEXT: v_writelane_b32 v32, s54, 10
; VI-NEXT: v_writelane_b32 v32, s55, 11
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_mov_b32 s49, s29
; VI-NEXT: s_mov_b32 s48, s28
; VI-NEXT: s_mov_b32 s47, s27
; VI-NEXT: s_mov_b32 s46, s26
; VI-NEXT: s_mov_b32 s45, s25
; VI-NEXT: s_mov_b32 s44, s24
; VI-NEXT: s_mov_b32 s43, s23
; VI-NEXT: s_mov_b32 s42, s22
; VI-NEXT: s_mov_b32 s41, s21
; VI-NEXT: s_mov_b32 s40, s20
; VI-NEXT: s_mov_b32 s39, s19
; VI-NEXT: s_mov_b32 s38, s18
; VI-NEXT: s_mov_b32 s37, s17
; VI-NEXT: s_mov_b32 s36, s16
; VI-NEXT: v_readfirstlane_b32 s59, v9
; VI-NEXT: v_readfirstlane_b32 s58, v8
; VI-NEXT: v_readfirstlane_b32 s57, v7
; VI-NEXT: v_readfirstlane_b32 s56, v6
; VI-NEXT: v_readfirstlane_b32 s55, v5
; VI-NEXT: v_readfirstlane_b32 s54, v4
; VI-NEXT: v_readfirstlane_b32 s53, v3
; VI-NEXT: v_readfirstlane_b32 s52, v2
; VI-NEXT: v_readfirstlane_b32 s51, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s50, v0
; VI-NEXT: s_cbranch_scc0 .LBB11_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB11_3
; VI-NEXT: .LBB11_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB11_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB11_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; VI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; VI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; VI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; VI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; VI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; VI-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; VI-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; VI-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; VI-NEXT: s_branch .LBB11_6
; VI-NEXT: .LBB11_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB11_6: ; %end
; VI-NEXT: v_readlane_b32 s55, v32, 11
; VI-NEXT: v_readlane_b32 s54, v32, 10
; VI-NEXT: v_readlane_b32 s53, v32, 9
; VI-NEXT: v_readlane_b32 s52, v32, 8
; VI-NEXT: v_readlane_b32 s51, v32, 7
; VI-NEXT: v_readlane_b32 s50, v32, 6
; VI-NEXT: v_readlane_b32 s49, v32, 5
; VI-NEXT: v_readlane_b32 s48, v32, 4
; VI-NEXT: v_readlane_b32 s39, v32, 3
; VI-NEXT: v_readlane_b32 s38, v32, 2
; VI-NEXT: v_readlane_b32 s37, v32, 1
; VI-NEXT: v_readlane_b32 s36, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v24i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_mov_b32 s49, s29
; GFX9-NEXT: s_mov_b32 s48, s28
; GFX9-NEXT: s_mov_b32 s47, s27
; GFX9-NEXT: s_mov_b32 s46, s26
; GFX9-NEXT: s_mov_b32 s45, s25
; GFX9-NEXT: s_mov_b32 s44, s24
; GFX9-NEXT: s_mov_b32 s43, s23
; GFX9-NEXT: s_mov_b32 s42, s22
; GFX9-NEXT: s_mov_b32 s41, s21
; GFX9-NEXT: s_mov_b32 s40, s20
; GFX9-NEXT: s_mov_b32 s39, s19
; GFX9-NEXT: s_mov_b32 s38, s18
; GFX9-NEXT: s_mov_b32 s37, s17
; GFX9-NEXT: s_mov_b32 s36, s16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s55, v5
; GFX9-NEXT: v_readfirstlane_b32 s54, v4
; GFX9-NEXT: v_readfirstlane_b32 s53, v3
; GFX9-NEXT: v_readfirstlane_b32 s52, v2
; GFX9-NEXT: v_readfirstlane_b32 s51, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s50, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB11_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB11_3
; GFX9-NEXT: .LBB11_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB11_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB11_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; GFX9-NEXT: s_branch .LBB11_6
; GFX9-NEXT: .LBB11_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB11_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12f64_to_v24i32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: v_writelane_b32 v32, s39, 3
; GFX11-NEXT: v_writelane_b32 v32, s48, 4
; GFX11-NEXT: v_writelane_b32 v32, s49, 5
; GFX11-NEXT: v_writelane_b32 v32, s50, 6
; GFX11-NEXT: v_writelane_b32 v32, s51, 7
; GFX11-NEXT: v_writelane_b32 v32, s52, 8
; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_writelane_b32 v32, s54, 10
; GFX11-NEXT: v_writelane_b32 v32, s55, 11
; GFX11-NEXT: s_mov_b32 s36, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
; GFX11-NEXT: v_readfirstlane_b32 s59, v5
; GFX11-NEXT: v_readfirstlane_b32 s58, v4
; GFX11-NEXT: v_readfirstlane_b32 s57, v3
; GFX11-NEXT: v_readfirstlane_b32 s56, v2
; GFX11-NEXT: v_readfirstlane_b32 s55, v1
; GFX11-NEXT: v_readfirstlane_b32 s54, v0
; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_mov_b32 s52, s28
; GFX11-NEXT: s_mov_b32 s51, s27
; GFX11-NEXT: s_mov_b32 s50, s26
; GFX11-NEXT: s_mov_b32 s49, s25
; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
; GFX11-NEXT: s_mov_b32 s40, s16
; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB11_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: .LBB11_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB11_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; GFX11-NEXT: s_branch .LBB11_5
; GFX11-NEXT: .LBB11_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v1, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v3, s39
; GFX11-NEXT: v_dual_mov_b32 v4, s40 :: v_dual_mov_b32 v5, s41
; GFX11-NEXT: v_dual_mov_b32 v6, s42 :: v_dual_mov_b32 v7, s43
; GFX11-NEXT: v_dual_mov_b32 v8, s44 :: v_dual_mov_b32 v9, s45
; GFX11-NEXT: v_dual_mov_b32 v10, s46 :: v_dual_mov_b32 v11, s47
; GFX11-NEXT: v_dual_mov_b32 v12, s48 :: v_dual_mov_b32 v13, s49
; GFX11-NEXT: v_dual_mov_b32 v14, s50 :: v_dual_mov_b32 v15, s51
; GFX11-NEXT: v_dual_mov_b32 v16, s52 :: v_dual_mov_b32 v17, s53
; GFX11-NEXT: v_dual_mov_b32 v18, s54 :: v_dual_mov_b32 v19, s55
; GFX11-NEXT: v_dual_mov_b32 v20, s56 :: v_dual_mov_b32 v21, s57
; GFX11-NEXT: v_dual_mov_b32 v22, s58 :: v_dual_mov_b32 v23, s59
; GFX11-NEXT: v_dual_mov_b32 v24, s60 :: v_dual_mov_b32 v25, s61
; GFX11-NEXT: v_dual_mov_b32 v26, s62 :: v_dual_mov_b32 v27, s63
; GFX11-NEXT: v_dual_mov_b32 v28, s64 :: v_dual_mov_b32 v29, s65
; GFX11-NEXT: v_dual_mov_b32 v30, s66 :: v_dual_mov_b32 v31, s67
; GFX11-NEXT: .LBB11_5: ; %end
; GFX11-NEXT: v_readlane_b32 s55, v32, 11
; GFX11-NEXT: v_readlane_b32 s54, v32, 10
; GFX11-NEXT: v_readlane_b32 s53, v32, 9
; GFX11-NEXT: v_readlane_b32 s52, v32, 8
; GFX11-NEXT: v_readlane_b32 s51, v32, 7
; GFX11-NEXT: v_readlane_b32 s50, v32, 6
; GFX11-NEXT: v_readlane_b32 s49, v32, 5
; GFX11-NEXT: v_readlane_b32 s48, v32, 4
; GFX11-NEXT: v_readlane_b32 s39, v32, 3
; GFX11-NEXT: v_readlane_b32 s38, v32, 2
; GFX11-NEXT: v_readlane_b32 s37, v32, 1
; GFX11-NEXT: v_readlane_b32 s36, v32, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v32, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define <48 x i16> @bitcast_v24i32_to_v48i16(<24 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB12_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB12_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB12_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB12_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v38
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v33
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: v_or_b32_e32 v1, v1, v49
; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v33
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v48i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB12_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB12_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB12_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v23, vcc, 3, v23
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_add_u32_e32 v21, vcc, 3, v21
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_add_u32_e32 v19, vcc, 3, v19
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB12_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v48i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB12_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB12_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB12_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB12_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v24i32_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB12_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-TRUE16-NEXT: .LBB12_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24i32_to_v48i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB12_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB12_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB12_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB12_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define inreg <48 x i16> @bitcast_v24i32_to_v48i16_scalar(<24 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v48i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v24, s30, 0
; SI-NEXT: v_writelane_b32 v24, s31, 1
; SI-NEXT: v_readfirstlane_b32 s12, v10
; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_readfirstlane_b32 s4, v8
; SI-NEXT: v_readfirstlane_b32 s7, v7
; SI-NEXT: v_readfirstlane_b32 s6, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s11, v3
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_readfirstlane_b32 s13, v1
; SI-NEXT: s_cmp_lg_u32 s12, 0
; SI-NEXT: v_readfirstlane_b32 s12, v0
; SI-NEXT: s_cbranch_scc0 .LBB13_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s19, 16
; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16
; SI-NEXT: s_lshr_b32 s88, s5, 16
; SI-NEXT: s_lshr_b32 s89, s7, 16
; SI-NEXT: s_lshr_b32 s90, s9, 16
; SI-NEXT: s_lshr_b32 s91, s11, 16
; SI-NEXT: s_lshr_b32 s92, s13, 16
; SI-NEXT: s_lshr_b32 s93, s29, 16
; SI-NEXT: s_lshr_b32 s94, s27, 16
; SI-NEXT: s_lshr_b32 s95, s25, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s21, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_mov_b32 s15, s40
; SI-NEXT: s_lshr_b64 s[40:41], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB13_3
; SI-NEXT: .LBB13_2:
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $vcc_hi
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: .LBB13_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: s_cbranch_scc1 .LBB13_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s5, s5, 3
; SI-NEXT: s_add_i32 s4, s4, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_add_i32 s11, s11, 3
; SI-NEXT: s_add_i32 s10, s10, 3
; SI-NEXT: s_add_i32 s9, s9, 3
; SI-NEXT: s_add_i32 s8, s8, 3
; SI-NEXT: s_add_i32 s7, s7, 3
; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16
; SI-NEXT: s_lshr_b64 s[40:41], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b32 s88, s5, 16
; SI-NEXT: s_lshr_b32 s89, s7, 16
; SI-NEXT: s_lshr_b32 s90, s9, 16
; SI-NEXT: s_lshr_b32 s91, s11, 16
; SI-NEXT: s_lshr_b32 s92, s13, 16
; SI-NEXT: s_lshr_b32 s93, s29, 16
; SI-NEXT: s_lshr_b32 s94, s27, 16
; SI-NEXT: s_lshr_b32 s95, s25, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s21, 16
; SI-NEXT: s_lshr_b32 s15, s19, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: .LBB13_5: ; %end
; SI-NEXT: s_and_b32 s19, s19, 0xffff
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_or_b32 s15, s19, s15
; SI-NEXT: s_lshl_b32 s19, s72, 16
; SI-NEXT: s_and_b32 s20, s20, 0xffff
; SI-NEXT: s_or_b32 s19, s20, s19
; SI-NEXT: s_and_b32 s20, s21, 0xffff
; SI-NEXT: s_lshl_b32 s21, vcc_hi, 16
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s22, 0xffff
; SI-NEXT: s_lshl_b32 s22, s62, 16
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s23, 0xffff
; SI-NEXT: s_lshl_b32 s23, vcc_lo, 16
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s24, 0xffff
; SI-NEXT: s_lshl_b32 s24, s60, 16
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s25, 0xffff
; SI-NEXT: s_lshl_b32 s25, s95, 16
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s26, 0xffff
; SI-NEXT: s_lshl_b32 s26, s58, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s27, 0xffff
; SI-NEXT: s_lshl_b32 s27, s94, 16
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s28, 0xffff
; SI-NEXT: s_lshl_b32 s28, s56, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s29, 0xffff
; SI-NEXT: s_lshl_b32 s29, s93, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_lshl_b32 s29, s46, 16
; SI-NEXT: s_or_b32 s12, s12, s29
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s29, s92, 16
; SI-NEXT: s_or_b32 s13, s13, s29
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s29, s44, 16
; SI-NEXT: s_or_b32 s10, s10, s29
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_lshl_b32 s29, s91, 16
; SI-NEXT: s_or_b32 s11, s11, s29
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_lshl_b32 s29, s42, 16
; SI-NEXT: s_lshl_b32 s41, s76, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s8, s8, s29
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s29, s90, 16
; SI-NEXT: s_or_b32 s16, s16, s41
; SI-NEXT: s_and_b32 s17, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s30, 16
; SI-NEXT: s_or_b32 s9, s9, s29
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s29, s40, 16
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_or_b32 s17, s17, s41
; SI-NEXT: s_lshl_b32 s41, s74, 16
; SI-NEXT: s_and_b32 s18, s18, 0xffff
; SI-NEXT: s_or_b32 s6, s6, s29
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s29, s89, 16
; SI-NEXT: s_or_b32 s4, s4, s14
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s14, s88, 16
; SI-NEXT: s_or_b32 s18, s18, s41
; SI-NEXT: s_or_b32 s7, s7, s29
; SI-NEXT: s_or_b32 s5, s5, s14
; SI-NEXT: v_readlane_b32 s30, v24, 0
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s15
; SI-NEXT: v_mov_b32_e32 v4, s19
; SI-NEXT: v_mov_b32_e32 v5, s20
; SI-NEXT: v_mov_b32_e32 v6, s21
; SI-NEXT: v_mov_b32_e32 v7, s22
; SI-NEXT: v_mov_b32_e32 v8, s23
; SI-NEXT: v_mov_b32_e32 v9, s24
; SI-NEXT: v_mov_b32_e32 v10, s25
; SI-NEXT: v_mov_b32_e32 v11, s26
; SI-NEXT: v_mov_b32_e32 v12, s27
; SI-NEXT: v_mov_b32_e32 v13, s28
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v15, s13
; SI-NEXT: v_mov_b32_e32 v16, s10
; SI-NEXT: v_mov_b32_e32 v17, s11
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v20, s6
; SI-NEXT: v_mov_b32_e32 v21, s7
; SI-NEXT: v_mov_b32_e32 v22, s4
; SI-NEXT: v_mov_b32_e32 v23, s5
; SI-NEXT: v_readlane_b32 s31, v24, 1
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v48i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB13_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB13_3
; VI-NEXT: .LBB13_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB13_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB13_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s6, s6, 3
; VI-NEXT: s_add_i32 s7, s7, 3
; VI-NEXT: s_add_i32 s8, s8, 3
; VI-NEXT: s_add_i32 s9, s9, 3
; VI-NEXT: s_add_i32 s10, s10, 3
; VI-NEXT: s_add_i32 s11, s11, 3
; VI-NEXT: s_add_i32 s12, s12, 3
; VI-NEXT: s_add_i32 s13, s13, 3
; VI-NEXT: s_add_i32 s14, s14, 3
; VI-NEXT: s_add_i32 s15, s15, 3
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: .LBB13_5: ; %end
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s16, s78, 16
; VI-NEXT: s_or_b32 s5, s5, s16
; VI-NEXT: s_and_b32 s16, 0xffff, s18
; VI-NEXT: s_lshl_b32 s17, s77, 16
; VI-NEXT: s_or_b32 s16, s16, s17
; VI-NEXT: s_and_b32 s17, 0xffff, s19
; VI-NEXT: s_lshl_b32 s18, s76, 16
; VI-NEXT: s_or_b32 s17, s17, s18
; VI-NEXT: s_and_b32 s18, 0xffff, s20
; VI-NEXT: s_lshl_b32 s19, s75, 16
; VI-NEXT: s_or_b32 s18, s18, s19
; VI-NEXT: s_and_b32 s19, 0xffff, s21
; VI-NEXT: s_lshl_b32 s20, s74, 16
; VI-NEXT: s_or_b32 s19, s19, s20
; VI-NEXT: s_and_b32 s20, 0xffff, s22
; VI-NEXT: s_lshl_b32 s21, s73, 16
; VI-NEXT: s_or_b32 s20, s20, s21
; VI-NEXT: s_and_b32 s21, 0xffff, s23
; VI-NEXT: s_lshl_b32 s22, s72, 16
; VI-NEXT: s_or_b32 s21, s21, s22
; VI-NEXT: s_and_b32 s22, 0xffff, s24
; VI-NEXT: s_lshl_b32 s23, s63, 16
; VI-NEXT: s_or_b32 s22, s22, s23
; VI-NEXT: s_and_b32 s23, 0xffff, s25
; VI-NEXT: s_lshl_b32 s24, s62, 16
; VI-NEXT: s_or_b32 s23, s23, s24
; VI-NEXT: s_and_b32 s24, 0xffff, s26
; VI-NEXT: s_lshl_b32 s25, s61, 16
; VI-NEXT: s_or_b32 s24, s24, s25
; VI-NEXT: s_and_b32 s25, 0xffff, s27
; VI-NEXT: s_lshl_b32 s26, s60, 16
; VI-NEXT: s_or_b32 s25, s25, s26
; VI-NEXT: s_and_b32 s26, 0xffff, s28
; VI-NEXT: s_lshl_b32 s27, s59, 16
; VI-NEXT: s_or_b32 s26, s26, s27
; VI-NEXT: s_and_b32 s27, 0xffff, s29
; VI-NEXT: s_lshl_b32 s28, s58, 16
; VI-NEXT: s_or_b32 s27, s27, s28
; VI-NEXT: s_and_b32 s15, 0xffff, s15
; VI-NEXT: s_lshl_b32 s28, s57, 16
; VI-NEXT: s_or_b32 s15, s15, s28
; VI-NEXT: s_and_b32 s14, 0xffff, s14
; VI-NEXT: s_lshl_b32 s28, s56, 16
; VI-NEXT: s_or_b32 s14, s14, s28
; VI-NEXT: s_and_b32 s13, 0xffff, s13
; VI-NEXT: s_lshl_b32 s28, s47, 16
; VI-NEXT: s_or_b32 s13, s13, s28
; VI-NEXT: s_and_b32 s12, 0xffff, s12
; VI-NEXT: s_lshl_b32 s28, s46, 16
; VI-NEXT: s_or_b32 s12, s12, s28
; VI-NEXT: s_and_b32 s11, 0xffff, s11
; VI-NEXT: s_lshl_b32 s28, s45, 16
; VI-NEXT: s_or_b32 s11, s11, s28
; VI-NEXT: s_and_b32 s10, 0xffff, s10
; VI-NEXT: s_lshl_b32 s28, s44, 16
; VI-NEXT: s_or_b32 s10, s10, s28
; VI-NEXT: s_and_b32 s9, 0xffff, s9
; VI-NEXT: s_lshl_b32 s28, s43, 16
; VI-NEXT: s_or_b32 s9, s9, s28
; VI-NEXT: s_and_b32 s8, 0xffff, s8
; VI-NEXT: s_lshl_b32 s28, s42, 16
; VI-NEXT: s_or_b32 s8, s8, s28
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s28, s41, 16
; VI-NEXT: s_or_b32 s7, s7, s28
; VI-NEXT: s_and_b32 s6, 0xffff, s6
; VI-NEXT: s_lshl_b32 s28, s40, 16
; VI-NEXT: s_or_b32 s6, s6, s28
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s17
; VI-NEXT: v_mov_b32_e32 v4, s18
; VI-NEXT: v_mov_b32_e32 v5, s19
; VI-NEXT: v_mov_b32_e32 v6, s20
; VI-NEXT: v_mov_b32_e32 v7, s21
; VI-NEXT: v_mov_b32_e32 v8, s22
; VI-NEXT: v_mov_b32_e32 v9, s23
; VI-NEXT: v_mov_b32_e32 v10, s24
; VI-NEXT: v_mov_b32_e32 v11, s25
; VI-NEXT: v_mov_b32_e32 v12, s26
; VI-NEXT: v_mov_b32_e32 v13, s27
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v48i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB13_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB13_3
; GFX9-NEXT: .LBB13_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB13_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB13_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s6, s6, 3
; GFX9-NEXT: s_add_i32 s7, s7, 3
; GFX9-NEXT: s_add_i32 s8, s8, 3
; GFX9-NEXT: s_add_i32 s9, s9, 3
; GFX9-NEXT: s_add_i32 s10, s10, 3
; GFX9-NEXT: s_add_i32 s11, s11, 3
; GFX9-NEXT: s_add_i32 s12, s12, 3
; GFX9-NEXT: s_add_i32 s13, s13, 3
; GFX9-NEXT: s_add_i32 s14, s14, 3
; GFX9-NEXT: s_add_i32 s15, s15, 3
; GFX9-NEXT: s_add_i32 s29, s29, 3
; GFX9-NEXT: s_add_i32 s28, s28, 3
; GFX9-NEXT: s_add_i32 s27, s27, 3
; GFX9-NEXT: s_add_i32 s26, s26, 3
; GFX9-NEXT: s_add_i32 s25, s25, 3
; GFX9-NEXT: s_add_i32 s24, s24, 3
; GFX9-NEXT: s_add_i32 s23, s23, 3
; GFX9-NEXT: s_add_i32 s22, s22, 3
; GFX9-NEXT: s_add_i32 s21, s21, 3
; GFX9-NEXT: s_add_i32 s20, s20, 3
; GFX9-NEXT: s_add_i32 s19, s19, 3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: .LBB13_5: ; %end
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s78
; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s76
; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s74
; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s72
; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s60
; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s59
; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s58
; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s57
; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s46
; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s45
; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s44
; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s43
; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s42
; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s41
; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s40
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s17
; GFX9-NEXT: v_mov_b32_e32 v4, s18
; GFX9-NEXT: v_mov_b32_e32 v5, s19
; GFX9-NEXT: v_mov_b32_e32 v6, s20
; GFX9-NEXT: v_mov_b32_e32 v7, s21
; GFX9-NEXT: v_mov_b32_e32 v8, s22
; GFX9-NEXT: v_mov_b32_e32 v9, s23
; GFX9-NEXT: v_mov_b32_e32 v10, s24
; GFX9-NEXT: v_mov_b32_e32 v11, s25
; GFX9-NEXT: v_mov_b32_e32 v12, s26
; GFX9-NEXT: v_mov_b32_e32 v13, s27
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v48i16_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s74, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB13_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: s_branch .LBB13_3
; GFX11-NEXT: .LBB13_2:
; GFX11-NEXT: s_mov_b32 s74, -1
; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr72
; GFX11-NEXT: ; implicit-def: $sgpr63
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr61
; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr59
; GFX11-NEXT: ; implicit-def: $sgpr58
; GFX11-NEXT: ; implicit-def: $sgpr57
; GFX11-NEXT: ; implicit-def: $sgpr56
; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr46
; GFX11-NEXT: ; implicit-def: $sgpr45
; GFX11-NEXT: ; implicit-def: $sgpr44
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: ; implicit-def: $sgpr41
; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: ; implicit-def: $sgpr13
; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: ; implicit-def: $sgpr11
; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB13_3: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB13_5
; GFX11-NEXT: ; %bb.4: ; %cmp.true
; GFX11-NEXT: s_add_i32 s4, s4, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
; GFX11-NEXT: s_add_i32 s6, s6, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s8, s8, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s29, s29, 3
; GFX11-NEXT: s_add_i32 s28, s28, 3
; GFX11-NEXT: s_add_i32 s27, s27, 3
; GFX11-NEXT: s_add_i32 s26, s26, 3
; GFX11-NEXT: s_add_i32 s25, s25, 3
; GFX11-NEXT: s_add_i32 s24, s24, 3
; GFX11-NEXT: s_add_i32 s23, s23, 3
; GFX11-NEXT: s_add_i32 s22, s22, 3
; GFX11-NEXT: s_add_i32 s21, s21, 3
; GFX11-NEXT: s_add_i32 s20, s20, 3
; GFX11-NEXT: s_add_i32 s19, s19, 3
; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s17, s17, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
; GFX11-NEXT: s_add_i32 s3, s3, 3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: .LBB13_5: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s72
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s62
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46
; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44
; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s40
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s10
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define <24 x i32> @bitcast_v48i16_to_v24i32(<48 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v24i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_or_b32_e32 v1, v1, v59
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v58
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v57
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_or_b32_e32 v7, v7, v56
; SI-NEXT: v_or_b32_e32 v8, v8, v63
; SI-NEXT: v_or_b32_e32 v9, v9, v62
; SI-NEXT: v_or_b32_e32 v10, v10, v61
; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB14_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB14_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v57, v5
; SI-NEXT: v_or_b32_e32 v6, v32, v6
; SI-NEXT: v_or_b32_e32 v7, v56, v7
; SI-NEXT: v_or_b32_e32 v8, v63, v8
; SI-NEXT: v_or_b32_e32 v9, v62, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: .LBB14_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v24i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB14_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB14_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB14_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 3
; VI-NEXT: v_add_u16_e32 v0, 3, v47
; VI-NEXT: v_add_u16_sdwa v1, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 3, v46
; VI-NEXT: v_add_u16_sdwa v2, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v45
; VI-NEXT: v_add_u16_sdwa v3, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v44
; VI-NEXT: v_add_u16_sdwa v4, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v43
; VI-NEXT: v_add_u16_sdwa v5, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v42
; VI-NEXT: v_add_u16_sdwa v6, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v41
; VI-NEXT: v_add_u16_sdwa v7, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: v_add_u16_e32 v7, 3, v40
; VI-NEXT: v_add_u16_sdwa v8, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v55
; VI-NEXT: v_add_u16_sdwa v9, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_add_u16_e32 v9, 3, v54
; VI-NEXT: v_add_u16_sdwa v10, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u16_e32 v10, 3, v53
; VI-NEXT: v_add_u16_sdwa v11, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_add_u16_e32 v11, 3, v52
; VI-NEXT: v_add_u16_sdwa v12, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u16_e32 v12, 3, v51
; VI-NEXT: v_add_u16_sdwa v13, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_add_u16_e32 v13, 3, v50
; VI-NEXT: v_add_u16_sdwa v14, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_add_u16_e32 v14, 3, v49
; VI-NEXT: v_add_u16_sdwa v15, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_add_u16_e32 v15, 3, v48
; VI-NEXT: v_add_u16_sdwa v16, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: v_add_u16_e32 v16, 3, v39
; VI-NEXT: v_add_u16_sdwa v17, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: v_add_u16_e32 v17, 3, v38
; VI-NEXT: v_add_u16_sdwa v18, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: v_add_u16_e32 v18, 3, v37
; VI-NEXT: v_add_u16_sdwa v19, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: v_add_u16_e32 v19, 3, v36
; VI-NEXT: v_add_u16_sdwa v20, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: v_add_u16_e32 v20, 3, v35
; VI-NEXT: v_add_u16_sdwa v21, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: v_add_u16_e32 v21, 3, v34
; VI-NEXT: v_add_u16_sdwa v22, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: v_add_u16_e32 v22, 3, v33
; VI-NEXT: v_add_u16_sdwa v24, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v22, v22, v24
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB14_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v24i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB14_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB14_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB14_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB14_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB14_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB14_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v24i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB14_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: .LBB14_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define inreg <24 x i32> @bitcast_v48i16_to_v24i32_scalar(<48 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v24i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v24, s36, 0
; SI-NEXT: v_writelane_b32 v24, s37, 1
; SI-NEXT: v_writelane_b32 v24, s38, 2
; SI-NEXT: v_writelane_b32 v24, s39, 3
; SI-NEXT: v_writelane_b32 v24, s48, 4
; SI-NEXT: v_writelane_b32 v24, s49, 5
; SI-NEXT: v_writelane_b32 v24, s50, 6
; SI-NEXT: v_writelane_b32 v24, s51, 7
; SI-NEXT: v_writelane_b32 v24, s52, 8
; SI-NEXT: v_writelane_b32 v24, s53, 9
; SI-NEXT: v_writelane_b32 v24, s54, 10
; SI-NEXT: v_writelane_b32 v24, s55, 11
; SI-NEXT: v_writelane_b32 v24, s64, 12
; SI-NEXT: v_writelane_b32 v24, s65, 13
; SI-NEXT: v_writelane_b32 v24, s66, 14
; SI-NEXT: v_writelane_b32 v24, s67, 15
; SI-NEXT: v_writelane_b32 v24, s30, 16
; SI-NEXT: v_writelane_b32 v24, s31, 17
; SI-NEXT: v_readfirstlane_b32 s7, v9
; SI-NEXT: v_readfirstlane_b32 s9, v8
; SI-NEXT: v_readfirstlane_b32 s11, v7
; SI-NEXT: v_readfirstlane_b32 s13, v6
; SI-NEXT: v_readfirstlane_b32 s15, v5
; SI-NEXT: v_readfirstlane_b32 s74, v4
; SI-NEXT: v_readfirstlane_b32 s77, v3
; SI-NEXT: v_readfirstlane_b32 s88, v2
; SI-NEXT: v_readfirstlane_b32 s91, v1
; SI-NEXT: v_readfirstlane_b32 s94, v0
; SI-NEXT: s_lshr_b32 s72, s29, 16
; SI-NEXT: s_lshr_b32 s75, s28, 16
; SI-NEXT: s_lshr_b32 s78, s27, 16
; SI-NEXT: s_lshr_b32 s89, s26, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s60, s21, 16
; SI-NEXT: s_lshr_b32 s61, s20, 16
; SI-NEXT: s_lshr_b32 s62, s19, 16
; SI-NEXT: s_lshr_b32 s63, s18, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_lshr_b32 s31, s16, 16
; SI-NEXT: s_lshr_b32 s6, s7, 16
; SI-NEXT: s_lshr_b32 s8, s9, 16
; SI-NEXT: s_lshr_b32 s10, s11, 16
; SI-NEXT: s_lshr_b32 s12, s13, 16
; SI-NEXT: s_lshr_b32 s14, s15, 16
; SI-NEXT: s_lshr_b32 s73, s74, 16
; SI-NEXT: s_lshr_b32 s76, s77, 16
; SI-NEXT: s_lshr_b32 s79, s88, 16
; SI-NEXT: s_lshr_b32 s90, s91, 16
; SI-NEXT: s_lshr_b32 s93, s94, 16
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_cbranch_scc0 .LBB15_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s36, s4, s5
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s37, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s91, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s77, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s15, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s13, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s11, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s9, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB15_3
; SI-NEXT: .LBB15_2:
; SI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v25, s77, 0
; SI-NEXT: v_writelane_b32 v25, s74, 1
; SI-NEXT: v_writelane_b32 v25, s15, 2
; SI-NEXT: v_writelane_b32 v25, s13, 3
; SI-NEXT: s_mov_b32 s13, s11
; SI-NEXT: s_mov_b32 s11, s9
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_mov_b32 s7, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, s95
; SI-NEXT: s_mov_b32 s95, s93
; SI-NEXT: s_mov_b32 s93, s92
; SI-NEXT: s_mov_b32 s92, s90
; SI-NEXT: s_mov_b32 s90, s89
; SI-NEXT: s_mov_b32 s89, s79
; SI-NEXT: s_mov_b32 s79, s78
; SI-NEXT: s_mov_b32 s78, s76
; SI-NEXT: s_mov_b32 s76, s75
; SI-NEXT: s_mov_b32 s75, s73
; SI-NEXT: s_mov_b32 s73, s72
; SI-NEXT: s_mov_b32 s72, s14
; SI-NEXT: s_mov_b32 s14, s12
; SI-NEXT: s_mov_b32 s12, s10
; SI-NEXT: s_mov_b32 s10, s8
; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s6, s60
; SI-NEXT: s_mov_b32 s77, s88
; SI-NEXT: s_mov_b32 s88, s61
; SI-NEXT: s_mov_b32 s74, s91
; SI-NEXT: s_mov_b32 s91, s62
; SI-NEXT: s_mov_b32 s15, s63
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_mov_b32 s63, s15
; SI-NEXT: s_mov_b32 s62, s91
; SI-NEXT: s_mov_b32 s91, s74
; SI-NEXT: s_mov_b32 s61, s88
; SI-NEXT: s_mov_b32 s88, s77
; SI-NEXT: s_mov_b32 s60, s6
; SI-NEXT: s_mov_b32 s6, s8
; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s10, s12
; SI-NEXT: s_mov_b32 s12, s14
; SI-NEXT: s_mov_b32 s14, s72
; SI-NEXT: s_mov_b32 s72, s73
; SI-NEXT: s_mov_b32 s73, s75
; SI-NEXT: s_mov_b32 s75, s76
; SI-NEXT: s_mov_b32 s76, s78
; SI-NEXT: s_mov_b32 s78, s79
; SI-NEXT: s_mov_b32 s79, s89
; SI-NEXT: s_mov_b32 s89, s90
; SI-NEXT: s_mov_b32 s90, s92
; SI-NEXT: s_mov_b32 s92, s93
; SI-NEXT: s_mov_b32 s93, s95
; SI-NEXT: s_mov_b32 s95, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, s7
; SI-NEXT: s_mov_b32 s7, s9
; SI-NEXT: s_mov_b32 s9, s11
; SI-NEXT: s_mov_b32 s11, s13
; SI-NEXT: v_readlane_b32 s13, v25, 3
; SI-NEXT: v_readlane_b32 s15, v25, 2
; SI-NEXT: v_readlane_b32 s74, v25, 1
; SI-NEXT: v_readlane_b32 s77, v25, 0
; SI-NEXT: .LBB15_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB15_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s36, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s37, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s38, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s39, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s40, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s41, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s42, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s43, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s44, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s45, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s46, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s47, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s48, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s94, s94, 3
; SI-NEXT: s_add_i32 s49, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s50, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s91, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s51, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s88, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s52, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s77, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s74, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s54, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s15, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s13, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s56, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s11, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s9, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s58, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s7, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
; SI-NEXT: .LBB15_5: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 16
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_readlane_b32 s31, v24, 17
; SI-NEXT: v_readlane_b32 s67, v24, 15
; SI-NEXT: v_readlane_b32 s66, v24, 14
; SI-NEXT: v_readlane_b32 s65, v24, 13
; SI-NEXT: v_readlane_b32 s64, v24, 12
; SI-NEXT: v_readlane_b32 s55, v24, 11
; SI-NEXT: v_readlane_b32 s54, v24, 10
; SI-NEXT: v_readlane_b32 s53, v24, 9
; SI-NEXT: v_readlane_b32 s52, v24, 8
; SI-NEXT: v_readlane_b32 s51, v24, 7
; SI-NEXT: v_readlane_b32 s50, v24, 6
; SI-NEXT: v_readlane_b32 s49, v24, 5
; SI-NEXT: v_readlane_b32 s48, v24, 4
; SI-NEXT: v_readlane_b32 s39, v24, 3
; SI-NEXT: v_readlane_b32 s38, v24, 2
; SI-NEXT: v_readlane_b32 s37, v24, 1
; SI-NEXT: v_readlane_b32 s36, v24, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v24i32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v24, s34, 0
; VI-NEXT: v_writelane_b32 v24, s35, 1
; VI-NEXT: v_writelane_b32 v24, s36, 2
; VI-NEXT: v_writelane_b32 v24, s37, 3
; VI-NEXT: v_writelane_b32 v24, s38, 4
; VI-NEXT: v_writelane_b32 v24, s39, 5
; VI-NEXT: v_writelane_b32 v24, s48, 6
; VI-NEXT: v_writelane_b32 v24, s49, 7
; VI-NEXT: v_writelane_b32 v24, s50, 8
; VI-NEXT: v_writelane_b32 v24, s51, 9
; VI-NEXT: v_writelane_b32 v24, s52, 10
; VI-NEXT: v_writelane_b32 v24, s53, 11
; VI-NEXT: v_writelane_b32 v24, s54, 12
; VI-NEXT: v_writelane_b32 v24, s55, 13
; VI-NEXT: v_writelane_b32 v24, s64, 14
; VI-NEXT: v_writelane_b32 v24, s65, 15
; VI-NEXT: v_writelane_b32 v24, s66, 16
; VI-NEXT: v_writelane_b32 v24, s67, 17
; VI-NEXT: v_writelane_b32 v24, s30, 18
; VI-NEXT: v_writelane_b32 v24, s31, 19
; VI-NEXT: v_readfirstlane_b32 s7, v9
; VI-NEXT: v_readfirstlane_b32 s9, v8
; VI-NEXT: v_readfirstlane_b32 s11, v7
; VI-NEXT: v_readfirstlane_b32 s13, v6
; VI-NEXT: v_readfirstlane_b32 s15, v5
; VI-NEXT: v_readfirstlane_b32 s74, v4
; VI-NEXT: v_readfirstlane_b32 s77, v3
; VI-NEXT: v_readfirstlane_b32 s88, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s60, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s75, s28, 16
; VI-NEXT: s_lshr_b32 s78, s27, 16
; VI-NEXT: s_lshr_b32 s89, s26, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s25, 16
; VI-NEXT: s_lshr_b32 s61, s24, 16
; VI-NEXT: s_lshr_b32 s62, s23, 16
; VI-NEXT: s_lshr_b32 s63, s22, 16
; VI-NEXT: s_lshr_b32 s30, s21, 16
; VI-NEXT: s_lshr_b32 s31, s20, 16
; VI-NEXT: s_lshr_b32 s34, s19, 16
; VI-NEXT: s_lshr_b32 s35, s18, 16
; VI-NEXT: s_lshr_b32 s64, s17, 16
; VI-NEXT: s_lshr_b32 s65, s16, 16
; VI-NEXT: s_lshr_b32 s6, s7, 16
; VI-NEXT: s_lshr_b32 s8, s9, 16
; VI-NEXT: s_lshr_b32 s10, s11, 16
; VI-NEXT: s_lshr_b32 s12, s13, 16
; VI-NEXT: s_lshr_b32 s14, s15, 16
; VI-NEXT: s_lshr_b32 s73, s74, 16
; VI-NEXT: s_lshr_b32 s76, s77, 16
; VI-NEXT: s_lshr_b32 s79, s88, 16
; VI-NEXT: s_lshr_b32 s90, s91, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s60, 16
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: s_cbranch_scc0 .LBB15_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s17
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s60
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s88
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s15
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s13
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s9
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB15_3
; VI-NEXT: .LBB15_2:
; VI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: v_writelane_b32 v25, s77, 0
; VI-NEXT: v_writelane_b32 v25, s74, 1
; VI-NEXT: v_writelane_b32 v25, s15, 2
; VI-NEXT: v_writelane_b32 v25, s13, 3
; VI-NEXT: v_writelane_b32 v25, s11, 4
; VI-NEXT: v_writelane_b32 v25, s9, 5
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_mov_b32 s7, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, s90
; VI-NEXT: s_mov_b32 s90, s89
; VI-NEXT: s_mov_b32 s89, s79
; VI-NEXT: s_mov_b32 s79, s78
; VI-NEXT: s_mov_b32 s78, s76
; VI-NEXT: s_mov_b32 s76, s75
; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s12
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s8
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s6, s60
; VI-NEXT: s_mov_b32 s77, s61
; VI-NEXT: s_mov_b32 s74, s88
; VI-NEXT: s_mov_b32 s88, s62
; VI-NEXT: s_mov_b32 s11, s63
; VI-NEXT: s_mov_b32 s15, s91
; VI-NEXT: s_mov_b32 s91, s64
; VI-NEXT: s_mov_b32 s13, s65
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_mov_b32 s65, s13
; VI-NEXT: s_mov_b32 s64, s91
; VI-NEXT: s_mov_b32 s91, s15
; VI-NEXT: s_mov_b32 s63, s11
; VI-NEXT: s_mov_b32 s62, s88
; VI-NEXT: s_mov_b32 s88, s74
; VI-NEXT: s_mov_b32 s61, s77
; VI-NEXT: s_mov_b32 s60, s6
; VI-NEXT: s_mov_b32 s6, s8
; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s12, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s73
; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s76
; VI-NEXT: s_mov_b32 s76, s78
; VI-NEXT: s_mov_b32 s78, s79
; VI-NEXT: s_mov_b32 s79, s89
; VI-NEXT: s_mov_b32 s89, s90
; VI-NEXT: s_mov_b32 s90, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, s7
; VI-NEXT: s_mov_b32 s7, s9
; VI-NEXT: v_readlane_b32 s9, v25, 5
; VI-NEXT: v_readlane_b32 s11, v25, 4
; VI-NEXT: v_readlane_b32 s13, v25, 3
; VI-NEXT: v_readlane_b32 s15, v25, 2
; VI-NEXT: v_readlane_b32 s74, v25, 1
; VI-NEXT: v_readlane_b32 s77, v25, 0
; VI-NEXT: .LBB15_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB15_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s17, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s22, 0xffff
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s42, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s23, 0xffff
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s43, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s24, 0xffff
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s44, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s25, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s45, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s26, 0xffff
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s46, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s27, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s47, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s28, 0xffff
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s48, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s29, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s49, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s60, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s50, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s91, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s51, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s88, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s52, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s77, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s74, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s54, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s15, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s13, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s11, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s9, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s58, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s7, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: .LBB15_5: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_readlane_b32 s31, v24, 19
; VI-NEXT: v_readlane_b32 s67, v24, 17
; VI-NEXT: v_readlane_b32 s66, v24, 16
; VI-NEXT: v_readlane_b32 s65, v24, 15
; VI-NEXT: v_readlane_b32 s64, v24, 14
; VI-NEXT: v_readlane_b32 s55, v24, 13
; VI-NEXT: v_readlane_b32 s54, v24, 12
; VI-NEXT: v_readlane_b32 s53, v24, 11
; VI-NEXT: v_readlane_b32 s52, v24, 10
; VI-NEXT: v_readlane_b32 s51, v24, 9
; VI-NEXT: v_readlane_b32 s50, v24, 8
; VI-NEXT: v_readlane_b32 s49, v24, 7
; VI-NEXT: v_readlane_b32 s48, v24, 6
; VI-NEXT: v_readlane_b32 s39, v24, 5
; VI-NEXT: v_readlane_b32 s38, v24, 4
; VI-NEXT: v_readlane_b32 s37, v24, 3
; VI-NEXT: v_readlane_b32 s36, v24, 2
; VI-NEXT: v_readlane_b32 s35, v24, 1
; VI-NEXT: v_readlane_b32 s34, v24, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v24i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB15_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB15_3
; GFX9-NEXT: .LBB15_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB15_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB15_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v0, s36, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s37, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, s38, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, s39, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, s40, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, s41, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, s42, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, s43, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, s44, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, s45, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, s46, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, s47, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, s48, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, s49, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, s50, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB15_6
; GFX9-NEXT: .LBB15_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB15_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48i16_to_v24i32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB15_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB15_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB15_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB15_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define <48 x half> @bitcast_v24i32_to_v48f16(<24 x i32> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v48f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB16_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB16_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB16_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB16_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v38
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v33
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: v_or_b32_e32 v1, v1, v49
; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v33
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v48f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB16_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB16_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB16_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v23, vcc, 3, v23
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_add_u32_e32 v21, vcc, 3, v21
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_add_u32_e32 v19, vcc, 3, v19
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB16_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v48f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB16_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB16_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB16_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB16_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v24i32_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB16_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-TRUE16-NEXT: .LBB16_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24i32_to_v48f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB16_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB16_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB16_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 3, v23
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 3, v22
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v21
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v18
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 3, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 3, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 3, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB16_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define inreg <48 x half> @bitcast_v24i32_to_v48f16_scalar(<24 x i32> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24i32_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v24, s30, 0
; SI-NEXT: v_writelane_b32 v24, s31, 1
; SI-NEXT: v_readfirstlane_b32 s12, v10
; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_readfirstlane_b32 s4, v8
; SI-NEXT: v_readfirstlane_b32 s7, v7
; SI-NEXT: v_readfirstlane_b32 s6, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s11, v3
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_readfirstlane_b32 s13, v1
; SI-NEXT: s_cmp_lg_u32 s12, 0
; SI-NEXT: v_readfirstlane_b32 s12, v0
; SI-NEXT: s_cbranch_scc0 .LBB17_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s19, 16
; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16
; SI-NEXT: s_lshr_b32 s88, s5, 16
; SI-NEXT: s_lshr_b32 s89, s7, 16
; SI-NEXT: s_lshr_b32 s90, s9, 16
; SI-NEXT: s_lshr_b32 s91, s11, 16
; SI-NEXT: s_lshr_b32 s92, s13, 16
; SI-NEXT: s_lshr_b32 s93, s29, 16
; SI-NEXT: s_lshr_b32 s94, s27, 16
; SI-NEXT: s_lshr_b32 s95, s25, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s21, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_mov_b32 s15, s40
; SI-NEXT: s_lshr_b64 s[40:41], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB17_3
; SI-NEXT: .LBB17_2:
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $vcc_hi
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: .LBB17_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: s_cbranch_scc1 .LBB17_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s5, s5, 3
; SI-NEXT: s_add_i32 s4, s4, 3
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s13, s13, 3
; SI-NEXT: s_add_i32 s12, s12, 3
; SI-NEXT: s_add_i32 s11, s11, 3
; SI-NEXT: s_add_i32 s10, s10, 3
; SI-NEXT: s_add_i32 s9, s9, 3
; SI-NEXT: s_add_i32 s8, s8, 3
; SI-NEXT: s_add_i32 s7, s7, 3
; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16
; SI-NEXT: s_lshr_b64 s[40:41], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b32 s88, s5, 16
; SI-NEXT: s_lshr_b32 s89, s7, 16
; SI-NEXT: s_lshr_b32 s90, s9, 16
; SI-NEXT: s_lshr_b32 s91, s11, 16
; SI-NEXT: s_lshr_b32 s92, s13, 16
; SI-NEXT: s_lshr_b32 s93, s29, 16
; SI-NEXT: s_lshr_b32 s94, s27, 16
; SI-NEXT: s_lshr_b32 s95, s25, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s21, 16
; SI-NEXT: s_lshr_b32 s15, s19, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: .LBB17_5: ; %end
; SI-NEXT: s_and_b32 s19, s19, 0xffff
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_or_b32 s15, s19, s15
; SI-NEXT: s_lshl_b32 s19, s72, 16
; SI-NEXT: s_and_b32 s20, s20, 0xffff
; SI-NEXT: s_or_b32 s19, s20, s19
; SI-NEXT: s_and_b32 s20, s21, 0xffff
; SI-NEXT: s_lshl_b32 s21, vcc_hi, 16
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s22, 0xffff
; SI-NEXT: s_lshl_b32 s22, s62, 16
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s23, 0xffff
; SI-NEXT: s_lshl_b32 s23, vcc_lo, 16
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s24, 0xffff
; SI-NEXT: s_lshl_b32 s24, s60, 16
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s24, s25, 0xffff
; SI-NEXT: s_lshl_b32 s25, s95, 16
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s26, 0xffff
; SI-NEXT: s_lshl_b32 s26, s58, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s27, 0xffff
; SI-NEXT: s_lshl_b32 s27, s94, 16
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s28, 0xffff
; SI-NEXT: s_lshl_b32 s28, s56, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s29, 0xffff
; SI-NEXT: s_lshl_b32 s29, s93, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_lshl_b32 s29, s46, 16
; SI-NEXT: s_or_b32 s12, s12, s29
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s29, s92, 16
; SI-NEXT: s_or_b32 s13, s13, s29
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s29, s44, 16
; SI-NEXT: s_or_b32 s10, s10, s29
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_lshl_b32 s29, s91, 16
; SI-NEXT: s_or_b32 s11, s11, s29
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_lshl_b32 s29, s42, 16
; SI-NEXT: s_lshl_b32 s41, s76, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s8, s8, s29
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s29, s90, 16
; SI-NEXT: s_or_b32 s16, s16, s41
; SI-NEXT: s_and_b32 s17, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s30, 16
; SI-NEXT: s_or_b32 s9, s9, s29
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s29, s40, 16
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_or_b32 s17, s17, s41
; SI-NEXT: s_lshl_b32 s41, s74, 16
; SI-NEXT: s_and_b32 s18, s18, 0xffff
; SI-NEXT: s_or_b32 s6, s6, s29
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s29, s89, 16
; SI-NEXT: s_or_b32 s4, s4, s14
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s14, s88, 16
; SI-NEXT: s_or_b32 s18, s18, s41
; SI-NEXT: s_or_b32 s7, s7, s29
; SI-NEXT: s_or_b32 s5, s5, s14
; SI-NEXT: v_readlane_b32 s30, v24, 0
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s15
; SI-NEXT: v_mov_b32_e32 v4, s19
; SI-NEXT: v_mov_b32_e32 v5, s20
; SI-NEXT: v_mov_b32_e32 v6, s21
; SI-NEXT: v_mov_b32_e32 v7, s22
; SI-NEXT: v_mov_b32_e32 v8, s23
; SI-NEXT: v_mov_b32_e32 v9, s24
; SI-NEXT: v_mov_b32_e32 v10, s25
; SI-NEXT: v_mov_b32_e32 v11, s26
; SI-NEXT: v_mov_b32_e32 v12, s27
; SI-NEXT: v_mov_b32_e32 v13, s28
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v15, s13
; SI-NEXT: v_mov_b32_e32 v16, s10
; SI-NEXT: v_mov_b32_e32 v17, s11
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v20, s6
; SI-NEXT: v_mov_b32_e32 v21, s7
; SI-NEXT: v_mov_b32_e32 v22, s4
; SI-NEXT: v_mov_b32_e32 v23, s5
; SI-NEXT: v_readlane_b32 s31, v24, 1
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24i32_to_v48f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB17_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB17_3
; VI-NEXT: .LBB17_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB17_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB17_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s6, s6, 3
; VI-NEXT: s_add_i32 s7, s7, 3
; VI-NEXT: s_add_i32 s8, s8, 3
; VI-NEXT: s_add_i32 s9, s9, 3
; VI-NEXT: s_add_i32 s10, s10, 3
; VI-NEXT: s_add_i32 s11, s11, 3
; VI-NEXT: s_add_i32 s12, s12, 3
; VI-NEXT: s_add_i32 s13, s13, 3
; VI-NEXT: s_add_i32 s14, s14, 3
; VI-NEXT: s_add_i32 s15, s15, 3
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: .LBB17_5: ; %end
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s16, s78, 16
; VI-NEXT: s_or_b32 s5, s5, s16
; VI-NEXT: s_and_b32 s16, 0xffff, s18
; VI-NEXT: s_lshl_b32 s17, s77, 16
; VI-NEXT: s_or_b32 s16, s16, s17
; VI-NEXT: s_and_b32 s17, 0xffff, s19
; VI-NEXT: s_lshl_b32 s18, s76, 16
; VI-NEXT: s_or_b32 s17, s17, s18
; VI-NEXT: s_and_b32 s18, 0xffff, s20
; VI-NEXT: s_lshl_b32 s19, s75, 16
; VI-NEXT: s_or_b32 s18, s18, s19
; VI-NEXT: s_and_b32 s19, 0xffff, s21
; VI-NEXT: s_lshl_b32 s20, s74, 16
; VI-NEXT: s_or_b32 s19, s19, s20
; VI-NEXT: s_and_b32 s20, 0xffff, s22
; VI-NEXT: s_lshl_b32 s21, s73, 16
; VI-NEXT: s_or_b32 s20, s20, s21
; VI-NEXT: s_and_b32 s21, 0xffff, s23
; VI-NEXT: s_lshl_b32 s22, s72, 16
; VI-NEXT: s_or_b32 s21, s21, s22
; VI-NEXT: s_and_b32 s22, 0xffff, s24
; VI-NEXT: s_lshl_b32 s23, s63, 16
; VI-NEXT: s_or_b32 s22, s22, s23
; VI-NEXT: s_and_b32 s23, 0xffff, s25
; VI-NEXT: s_lshl_b32 s24, s62, 16
; VI-NEXT: s_or_b32 s23, s23, s24
; VI-NEXT: s_and_b32 s24, 0xffff, s26
; VI-NEXT: s_lshl_b32 s25, s61, 16
; VI-NEXT: s_or_b32 s24, s24, s25
; VI-NEXT: s_and_b32 s25, 0xffff, s27
; VI-NEXT: s_lshl_b32 s26, s60, 16
; VI-NEXT: s_or_b32 s25, s25, s26
; VI-NEXT: s_and_b32 s26, 0xffff, s28
; VI-NEXT: s_lshl_b32 s27, s59, 16
; VI-NEXT: s_or_b32 s26, s26, s27
; VI-NEXT: s_and_b32 s27, 0xffff, s29
; VI-NEXT: s_lshl_b32 s28, s58, 16
; VI-NEXT: s_or_b32 s27, s27, s28
; VI-NEXT: s_and_b32 s15, 0xffff, s15
; VI-NEXT: s_lshl_b32 s28, s57, 16
; VI-NEXT: s_or_b32 s15, s15, s28
; VI-NEXT: s_and_b32 s14, 0xffff, s14
; VI-NEXT: s_lshl_b32 s28, s56, 16
; VI-NEXT: s_or_b32 s14, s14, s28
; VI-NEXT: s_and_b32 s13, 0xffff, s13
; VI-NEXT: s_lshl_b32 s28, s47, 16
; VI-NEXT: s_or_b32 s13, s13, s28
; VI-NEXT: s_and_b32 s12, 0xffff, s12
; VI-NEXT: s_lshl_b32 s28, s46, 16
; VI-NEXT: s_or_b32 s12, s12, s28
; VI-NEXT: s_and_b32 s11, 0xffff, s11
; VI-NEXT: s_lshl_b32 s28, s45, 16
; VI-NEXT: s_or_b32 s11, s11, s28
; VI-NEXT: s_and_b32 s10, 0xffff, s10
; VI-NEXT: s_lshl_b32 s28, s44, 16
; VI-NEXT: s_or_b32 s10, s10, s28
; VI-NEXT: s_and_b32 s9, 0xffff, s9
; VI-NEXT: s_lshl_b32 s28, s43, 16
; VI-NEXT: s_or_b32 s9, s9, s28
; VI-NEXT: s_and_b32 s8, 0xffff, s8
; VI-NEXT: s_lshl_b32 s28, s42, 16
; VI-NEXT: s_or_b32 s8, s8, s28
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s28, s41, 16
; VI-NEXT: s_or_b32 s7, s7, s28
; VI-NEXT: s_and_b32 s6, 0xffff, s6
; VI-NEXT: s_lshl_b32 s28, s40, 16
; VI-NEXT: s_or_b32 s6, s6, s28
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s17
; VI-NEXT: v_mov_b32_e32 v4, s18
; VI-NEXT: v_mov_b32_e32 v5, s19
; VI-NEXT: v_mov_b32_e32 v6, s20
; VI-NEXT: v_mov_b32_e32 v7, s21
; VI-NEXT: v_mov_b32_e32 v8, s22
; VI-NEXT: v_mov_b32_e32 v9, s23
; VI-NEXT: v_mov_b32_e32 v10, s24
; VI-NEXT: v_mov_b32_e32 v11, s25
; VI-NEXT: v_mov_b32_e32 v12, s26
; VI-NEXT: v_mov_b32_e32 v13, s27
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24i32_to_v48f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB17_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB17_3
; GFX9-NEXT: .LBB17_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB17_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB17_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s6, s6, 3
; GFX9-NEXT: s_add_i32 s7, s7, 3
; GFX9-NEXT: s_add_i32 s8, s8, 3
; GFX9-NEXT: s_add_i32 s9, s9, 3
; GFX9-NEXT: s_add_i32 s10, s10, 3
; GFX9-NEXT: s_add_i32 s11, s11, 3
; GFX9-NEXT: s_add_i32 s12, s12, 3
; GFX9-NEXT: s_add_i32 s13, s13, 3
; GFX9-NEXT: s_add_i32 s14, s14, 3
; GFX9-NEXT: s_add_i32 s15, s15, 3
; GFX9-NEXT: s_add_i32 s29, s29, 3
; GFX9-NEXT: s_add_i32 s28, s28, 3
; GFX9-NEXT: s_add_i32 s27, s27, 3
; GFX9-NEXT: s_add_i32 s26, s26, 3
; GFX9-NEXT: s_add_i32 s25, s25, 3
; GFX9-NEXT: s_add_i32 s24, s24, 3
; GFX9-NEXT: s_add_i32 s23, s23, 3
; GFX9-NEXT: s_add_i32 s22, s22, 3
; GFX9-NEXT: s_add_i32 s21, s21, 3
; GFX9-NEXT: s_add_i32 s20, s20, 3
; GFX9-NEXT: s_add_i32 s19, s19, 3
; GFX9-NEXT: s_add_i32 s18, s18, 3
; GFX9-NEXT: s_add_i32 s17, s17, 3
; GFX9-NEXT: s_add_i32 s16, s16, 3
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: .LBB17_5: ; %end
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s78
; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s76
; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s74
; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s72
; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s60
; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s59
; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s58
; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s57
; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s46
; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s45
; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s44
; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s43
; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s42
; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s41
; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s40
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s17
; GFX9-NEXT: v_mov_b32_e32 v4, s18
; GFX9-NEXT: v_mov_b32_e32 v5, s19
; GFX9-NEXT: v_mov_b32_e32 v6, s20
; GFX9-NEXT: v_mov_b32_e32 v7, s21
; GFX9-NEXT: v_mov_b32_e32 v8, s22
; GFX9-NEXT: v_mov_b32_e32 v9, s23
; GFX9-NEXT: v_mov_b32_e32 v10, s24
; GFX9-NEXT: v_mov_b32_e32 v11, s25
; GFX9-NEXT: v_mov_b32_e32 v12, s26
; GFX9-NEXT: v_mov_b32_e32 v13, s27
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24i32_to_v48f16_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s74, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB17_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: s_branch .LBB17_3
; GFX11-NEXT: .LBB17_2:
; GFX11-NEXT: s_mov_b32 s74, -1
; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr72
; GFX11-NEXT: ; implicit-def: $sgpr63
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr61
; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr59
; GFX11-NEXT: ; implicit-def: $sgpr58
; GFX11-NEXT: ; implicit-def: $sgpr57
; GFX11-NEXT: ; implicit-def: $sgpr56
; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr46
; GFX11-NEXT: ; implicit-def: $sgpr45
; GFX11-NEXT: ; implicit-def: $sgpr44
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: ; implicit-def: $sgpr41
; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: ; implicit-def: $sgpr13
; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: ; implicit-def: $sgpr11
; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB17_3: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB17_5
; GFX11-NEXT: ; %bb.4: ; %cmp.true
; GFX11-NEXT: s_add_i32 s4, s4, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
; GFX11-NEXT: s_add_i32 s6, s6, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s8, s8, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s29, s29, 3
; GFX11-NEXT: s_add_i32 s28, s28, 3
; GFX11-NEXT: s_add_i32 s27, s27, 3
; GFX11-NEXT: s_add_i32 s26, s26, 3
; GFX11-NEXT: s_add_i32 s25, s25, 3
; GFX11-NEXT: s_add_i32 s24, s24, 3
; GFX11-NEXT: s_add_i32 s23, s23, 3
; GFX11-NEXT: s_add_i32 s22, s22, 3
; GFX11-NEXT: s_add_i32 s21, s21, 3
; GFX11-NEXT: s_add_i32 s20, s20, 3
; GFX11-NEXT: s_add_i32 s19, s19, 3
; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s17, s17, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
; GFX11-NEXT: s_add_i32 s3, s3, 3
; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s1, s1, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: .LBB17_5: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s72
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s62
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46
; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44
; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s40
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s10
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <24 x i32> %a, splat (i32 3)
%a2 = bitcast <24 x i32> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <24 x i32> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define <24 x i32> @bitcast_v48f16_to_v24i32(<48 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v24i32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB18_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v58
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v33
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v57
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB18_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB18_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v59
; SI-NEXT: v_cvt_f32_f16_e32 v2, v35
; SI-NEXT: v_cvt_f32_f16_e32 v1, v47
; SI-NEXT: v_cvt_f32_f16_e32 v3, v46
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_or_b32_e32 v1, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, v34
; SI-NEXT: v_cvt_f32_f16_e32 v3, v45
; SI-NEXT: v_cvt_f32_f16_e32 v4, v44
; SI-NEXT: v_cvt_f32_f16_e32 v5, v43
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v3, v58
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v42
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v7, v41
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, v33
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v40
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v9, v55
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_cvt_f32_f16_e32 v5, v57
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v54
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v11, v53
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v32
; SI-NEXT: v_cvt_f32_f16_e32 v12, v60
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f32_f16_e32 v13, v52
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_cvt_f32_f16_e32 v7, v56
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f32_f16_e32 v14, v51
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v16, v49
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v63
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v17, v48
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v19, v38
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_cvt_f32_f16_e32 v9, v62
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_cvt_f32_f16_e32 v20, v37
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v61
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_cvt_f32_f16_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, v50
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, v39
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, v36
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: .LBB18_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v24i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB18_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB18_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB18_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_add_f16_sdwa v0, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v47
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_add_f16_sdwa v1, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v46
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_f16_sdwa v2, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v45
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_add_f16_sdwa v3, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v44
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_add_f16_sdwa v4, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v43
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_add_f16_sdwa v5, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v42
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_add_f16_sdwa v6, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v41
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_add_f16_sdwa v7, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, 0x200, v40
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_f16_sdwa v8, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, 0x200, v55
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_add_f16_sdwa v9, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, 0x200, v54
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_add_f16_sdwa v10, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, 0x200, v53
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_add_f16_sdwa v11, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, 0x200, v52
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_add_f16_sdwa v12, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, 0x200, v51
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_add_f16_sdwa v13, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v50
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_add_f16_sdwa v14, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, 0x200, v49
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_add_f16_sdwa v15, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, 0x200, v48
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_add_f16_sdwa v16, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, 0x200, v39
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_add_f16_sdwa v17, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v38
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_add_f16_sdwa v18, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, 0x200, v37
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_add_f16_sdwa v19, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v36
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_add_f16_sdwa v20, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, 0x200, v35
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_add_f16_sdwa v21, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v34
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_add_f16_sdwa v22, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v33
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB18_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v24i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB18_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB18_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB18_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: s_movk_i32 s7, 0x200
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_f16 v0, v0, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, v14, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, v15, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, v16, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, v17, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, v18, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, v19, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, v20, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB18_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24i32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB18_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB18_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v24i32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB18_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: .LBB18_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define inreg <24 x i32> @bitcast_v48f16_to_v24i32_scalar(<48 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v24i32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s34, 0
; SI-NEXT: v_writelane_b32 v32, s35, 1
; SI-NEXT: v_writelane_b32 v32, s36, 2
; SI-NEXT: v_writelane_b32 v32, s37, 3
; SI-NEXT: v_writelane_b32 v32, s38, 4
; SI-NEXT: v_writelane_b32 v32, s39, 5
; SI-NEXT: v_writelane_b32 v32, s48, 6
; SI-NEXT: v_writelane_b32 v32, s49, 7
; SI-NEXT: v_writelane_b32 v32, s50, 8
; SI-NEXT: v_writelane_b32 v32, s51, 9
; SI-NEXT: v_writelane_b32 v32, s52, 10
; SI-NEXT: v_writelane_b32 v32, s53, 11
; SI-NEXT: v_writelane_b32 v32, s54, 12
; SI-NEXT: v_writelane_b32 v32, s55, 13
; SI-NEXT: v_writelane_b32 v32, s64, 14
; SI-NEXT: v_writelane_b32 v32, s65, 15
; SI-NEXT: v_writelane_b32 v32, s66, 16
; SI-NEXT: v_writelane_b32 v32, s67, 17
; SI-NEXT: v_writelane_b32 v32, s68, 18
; SI-NEXT: v_writelane_b32 v32, s69, 19
; SI-NEXT: v_writelane_b32 v32, s30, 20
; SI-NEXT: v_writelane_b32 v32, s31, 21
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s8, v8
; SI-NEXT: v_readfirstlane_b32 s10, v7
; SI-NEXT: v_readfirstlane_b32 s12, v6
; SI-NEXT: v_readfirstlane_b32 s14, v5
; SI-NEXT: v_readfirstlane_b32 s72, v4
; SI-NEXT: v_readfirstlane_b32 s74, v3
; SI-NEXT: v_readfirstlane_b32 s76, v2
; SI-NEXT: v_readfirstlane_b32 s79, v1
; SI-NEXT: v_readfirstlane_b32 s89, v0
; SI-NEXT: s_lshr_b32 s78, s29, 16
; SI-NEXT: s_lshr_b32 s90, s28, 16
; SI-NEXT: s_lshr_b32 s92, s27, 16
; SI-NEXT: s_lshr_b32 s93, s26, 16
; SI-NEXT: s_lshr_b32 s94, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s4, s21, 16
; SI-NEXT: s_lshr_b32 s30, s20, 16
; SI-NEXT: s_lshr_b32 s31, s19, 16
; SI-NEXT: s_lshr_b32 s34, s18, 16
; SI-NEXT: s_lshr_b32 s68, s17, 16
; SI-NEXT: s_lshr_b32 s69, s16, 16
; SI-NEXT: s_lshr_b32 s35, s6, 16
; SI-NEXT: s_lshr_b32 s9, s8, 16
; SI-NEXT: s_lshr_b32 s11, s10, 16
; SI-NEXT: s_lshr_b32 s13, s12, 16
; SI-NEXT: s_lshr_b32 s15, s14, 16
; SI-NEXT: s_lshr_b32 s73, s72, 16
; SI-NEXT: s_lshr_b32 s75, s74, 16
; SI-NEXT: s_lshr_b32 s77, s76, 16
; SI-NEXT: s_lshr_b32 s88, s79, 16
; SI-NEXT: s_lshr_b32 s91, s89, 16
; SI-NEXT: v_readfirstlane_b32 s5, v10
; SI-NEXT: s_cmp_lg_u32 s5, 0
; SI-NEXT: s_cbranch_scc0 .LBB19_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s5, s16, 0xffff
; SI-NEXT: s_lshl_b32 s7, s69, 16
; SI-NEXT: s_or_b32 s36, s5, s7
; SI-NEXT: s_and_b32 s5, s17, 0xffff
; SI-NEXT: s_lshl_b32 s7, s68, 16
; SI-NEXT: s_or_b32 s37, s5, s7
; SI-NEXT: s_and_b32 s5, s18, 0xffff
; SI-NEXT: s_lshl_b32 s7, s34, 16
; SI-NEXT: s_or_b32 s38, s5, s7
; SI-NEXT: s_and_b32 s5, s19, 0xffff
; SI-NEXT: s_lshl_b32 s7, s31, 16
; SI-NEXT: s_or_b32 s39, s5, s7
; SI-NEXT: s_and_b32 s5, s20, 0xffff
; SI-NEXT: s_lshl_b32 s7, s30, 16
; SI-NEXT: s_or_b32 s40, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xffff
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_or_b32 s41, s5, s4
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s94, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s89, 0xffff
; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s79, 0xffff
; SI-NEXT: s_lshl_b32 s5, s88, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
; SI-NEXT: s_lshl_b32 s5, s13, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
; SI-NEXT: s_lshl_b32 s5, s11, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB19_3
; SI-NEXT: .LBB19_2:
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: .LBB19_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB19_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s69
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
; SI-NEXT: v_cvt_f32_f16_e32 v2, s68
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, s34
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_cvt_f32_f16_e32 v4, s31
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, s30
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, s20
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, s7
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, vcc_hi
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, vcc_lo
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_cvt_f32_f16_e32 v8, s23
; SI-NEXT: v_cvt_f32_f16_e32 v9, s95
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; SI-NEXT: v_cvt_f32_f16_e32 v9, s94
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s93
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v11, v9
; SI-NEXT: v_cvt_f32_f16_e32 v11, s26
; SI-NEXT: v_cvt_f32_f16_e32 v12, s92
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s90
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s78
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, s29
; SI-NEXT: v_cvt_f32_f16_e32 v15, s91
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_cvt_f32_f16_e32 v16, s89
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: v_cvt_f32_f16_e32 v15, s88
; SI-NEXT: v_cvt_f32_f16_e32 v17, s79
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s77
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, s76
; SI-NEXT: v_cvt_f32_f16_e32 v18, s75
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v19, s74
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_cvt_f32_f16_e32 v18, s73
; SI-NEXT: v_cvt_f32_f16_e32 v20, s72
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s15
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, s14
; SI-NEXT: v_cvt_f32_f16_e32 v21, s13
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_cvt_f32_f16_e32 v22, s12
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: v_cvt_f32_f16_e32 v21, s11
; SI-NEXT: v_cvt_f32_f16_e32 v23, s10
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s9
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: v_cvt_f32_f16_e32 v23, s8
; SI-NEXT: v_cvt_f32_f16_e32 v24, s35
; SI-NEXT: v_cvt_f32_f16_e32 v25, s6
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: s_branch .LBB19_6
; SI-NEXT: .LBB19_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB19_6: ; %end
; SI-NEXT: v_readlane_b32 s30, v32, 20
; SI-NEXT: v_readlane_b32 s31, v32, 21
; SI-NEXT: v_readlane_b32 s69, v32, 19
; SI-NEXT: v_readlane_b32 s68, v32, 18
; SI-NEXT: v_readlane_b32 s67, v32, 17
; SI-NEXT: v_readlane_b32 s66, v32, 16
; SI-NEXT: v_readlane_b32 s65, v32, 15
; SI-NEXT: v_readlane_b32 s64, v32, 14
; SI-NEXT: v_readlane_b32 s55, v32, 13
; SI-NEXT: v_readlane_b32 s54, v32, 12
; SI-NEXT: v_readlane_b32 s53, v32, 11
; SI-NEXT: v_readlane_b32 s52, v32, 10
; SI-NEXT: v_readlane_b32 s51, v32, 9
; SI-NEXT: v_readlane_b32 s50, v32, 8
; SI-NEXT: v_readlane_b32 s49, v32, 7
; SI-NEXT: v_readlane_b32 s48, v32, 6
; SI-NEXT: v_readlane_b32 s39, v32, 5
; SI-NEXT: v_readlane_b32 s38, v32, 4
; SI-NEXT: v_readlane_b32 s37, v32, 3
; SI-NEXT: v_readlane_b32 s36, v32, 2
; SI-NEXT: v_readlane_b32 s35, v32, 1
; SI-NEXT: v_readlane_b32 s34, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v24i32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s34, 0
; VI-NEXT: v_writelane_b32 v32, s35, 1
; VI-NEXT: v_writelane_b32 v32, s36, 2
; VI-NEXT: v_writelane_b32 v32, s37, 3
; VI-NEXT: v_writelane_b32 v32, s38, 4
; VI-NEXT: v_writelane_b32 v32, s39, 5
; VI-NEXT: v_writelane_b32 v32, s48, 6
; VI-NEXT: v_writelane_b32 v32, s49, 7
; VI-NEXT: v_writelane_b32 v32, s50, 8
; VI-NEXT: v_writelane_b32 v32, s51, 9
; VI-NEXT: v_writelane_b32 v32, s52, 10
; VI-NEXT: v_writelane_b32 v32, s53, 11
; VI-NEXT: v_writelane_b32 v32, s54, 12
; VI-NEXT: v_writelane_b32 v32, s55, 13
; VI-NEXT: v_writelane_b32 v32, s64, 14
; VI-NEXT: v_writelane_b32 v32, s65, 15
; VI-NEXT: v_writelane_b32 v32, s66, 16
; VI-NEXT: v_writelane_b32 v32, s67, 17
; VI-NEXT: v_writelane_b32 v32, s68, 18
; VI-NEXT: v_writelane_b32 v32, s69, 19
; VI-NEXT: v_writelane_b32 v32, s70, 20
; VI-NEXT: v_writelane_b32 v32, s71, 21
; VI-NEXT: v_writelane_b32 v32, s80, 22
; VI-NEXT: v_writelane_b32 v32, s81, 23
; VI-NEXT: v_writelane_b32 v32, s30, 24
; VI-NEXT: v_writelane_b32 v32, s31, 25
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s8, v8
; VI-NEXT: v_readfirstlane_b32 s10, v7
; VI-NEXT: v_readfirstlane_b32 s12, v6
; VI-NEXT: v_readfirstlane_b32 s14, v5
; VI-NEXT: v_readfirstlane_b32 s73, v4
; VI-NEXT: v_readfirstlane_b32 s76, v3
; VI-NEXT: v_readfirstlane_b32 s79, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s4, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s74, s28, 16
; VI-NEXT: s_lshr_b32 s77, s27, 16
; VI-NEXT: s_lshr_b32 s88, s26, 16
; VI-NEXT: s_lshr_b32 s90, s25, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s24, 16
; VI-NEXT: s_lshr_b32 s31, s23, 16
; VI-NEXT: s_lshr_b32 s34, s22, 16
; VI-NEXT: s_lshr_b32 s35, s21, 16
; VI-NEXT: s_lshr_b32 s68, s20, 16
; VI-NEXT: s_lshr_b32 s69, s19, 16
; VI-NEXT: s_lshr_b32 s70, s18, 16
; VI-NEXT: s_lshr_b32 s71, s17, 16
; VI-NEXT: s_lshr_b32 s80, s16, 16
; VI-NEXT: s_lshr_b32 s81, s6, 16
; VI-NEXT: s_lshr_b32 s9, s8, 16
; VI-NEXT: s_lshr_b32 s11, s10, 16
; VI-NEXT: s_lshr_b32 s13, s12, 16
; VI-NEXT: s_lshr_b32 s15, s14, 16
; VI-NEXT: s_lshr_b32 s75, s73, 16
; VI-NEXT: s_lshr_b32 s78, s76, 16
; VI-NEXT: s_lshr_b32 s89, s79, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s91, 16
; VI-NEXT: s_lshr_b32 s30, s4, 16
; VI-NEXT: v_readfirstlane_b32 s5, v10
; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc0 .LBB19_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s5, 0xffff, s16
; VI-NEXT: s_lshl_b32 s7, s80, 16
; VI-NEXT: s_or_b32 s36, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s7, s71, 16
; VI-NEXT: s_or_b32 s37, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s18
; VI-NEXT: s_lshl_b32 s7, s70, 16
; VI-NEXT: s_or_b32 s38, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s19
; VI-NEXT: s_lshl_b32 s7, s69, 16
; VI-NEXT: s_or_b32 s39, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s20
; VI-NEXT: s_lshl_b32 s7, s68, 16
; VI-NEXT: s_or_b32 s40, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s21
; VI-NEXT: s_lshl_b32 s7, s35, 16
; VI-NEXT: s_or_b32 s41, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s22
; VI-NEXT: s_lshl_b32 s7, s34, 16
; VI-NEXT: s_or_b32 s42, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s23
; VI-NEXT: s_lshl_b32 s7, s31, 16
; VI-NEXT: s_or_b32 s43, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s24
; VI-NEXT: s_lshl_b32 s7, vcc_hi, 16
; VI-NEXT: s_or_b32 s44, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s25
; VI-NEXT: s_lshl_b32 s7, s90, 16
; VI-NEXT: s_or_b32 s45, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s26
; VI-NEXT: s_lshl_b32 s7, s88, 16
; VI-NEXT: s_or_b32 s46, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s27
; VI-NEXT: s_lshl_b32 s7, s77, 16
; VI-NEXT: s_or_b32 s47, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s28
; VI-NEXT: s_lshl_b32 s7, s74, 16
; VI-NEXT: s_or_b32 s48, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s29
; VI-NEXT: s_lshl_b32 s7, s72, 16
; VI-NEXT: s_or_b32 s49, s5, s7
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_and_b32 s4, 0xffff, s4
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s15, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB19_3
; VI-NEXT: .LBB19_2:
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: .LBB19_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB19_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_mov_b32_e32 v0, s80
; VI-NEXT: v_mov_b32_e32 v2, s71
; VI-NEXT: v_add_f16_sdwa v0, v0, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v23
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v23
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v23
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_mov_b32_e32 v3, s69
; VI-NEXT: v_add_f16_sdwa v3, v3, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v23
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_mov_b32_e32 v4, s68
; VI-NEXT: v_add_f16_sdwa v4, v4, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v23
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_mov_b32_e32 v5, s35
; VI-NEXT: v_add_f16_sdwa v5, v5, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v23
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_mov_b32_e32 v6, s34
; VI-NEXT: v_add_f16_sdwa v6, v6, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v23
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_mov_b32_e32 v7, s31
; VI-NEXT: v_add_f16_sdwa v7, v7, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v23
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_mov_b32_e32 v8, vcc_hi
; VI-NEXT: v_add_f16_sdwa v8, v8, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v23
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_mov_b32_e32 v9, s90
; VI-NEXT: v_add_f16_sdwa v9, v9, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v23
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_mov_b32_e32 v10, s88
; VI-NEXT: v_add_f16_sdwa v10, v10, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v23
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_mov_b32_e32 v11, s77
; VI-NEXT: v_add_f16_sdwa v11, v11, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v23
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_mov_b32_e32 v12, s74
; VI-NEXT: v_add_f16_sdwa v12, v12, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v23
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_mov_b32_e32 v13, s72
; VI-NEXT: v_add_f16_sdwa v13, v13, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v23
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_add_f16_sdwa v14, v14, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v23
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_mov_b32_e32 v15, vcc_lo
; VI-NEXT: v_add_f16_sdwa v15, v15, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s91, v23
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_mov_b32_e32 v16, s89
; VI-NEXT: v_add_f16_sdwa v16, v16, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s79, v23
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_mov_b32_e32 v17, s78
; VI-NEXT: v_add_f16_sdwa v17, v17, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s76, v23
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_mov_b32_e32 v18, s75
; VI-NEXT: v_add_f16_sdwa v18, v18, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s73, v23
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_mov_b32_e32 v19, s15
; VI-NEXT: v_add_f16_sdwa v19, v19, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s14, v23
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_mov_b32_e32 v20, s13
; VI-NEXT: v_add_f16_sdwa v20, v20, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s12, v23
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_mov_b32_e32 v21, s11
; VI-NEXT: v_add_f16_sdwa v21, v21, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s10, v23
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_mov_b32_e32 v22, s9
; VI-NEXT: v_add_f16_sdwa v22, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s8, v23
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_mov_b32_e32 v24, s81
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: s_branch .LBB19_6
; VI-NEXT: .LBB19_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB19_6: ; %end
; VI-NEXT: v_readlane_b32 s30, v32, 24
; VI-NEXT: v_readlane_b32 s31, v32, 25
; VI-NEXT: v_readlane_b32 s81, v32, 23
; VI-NEXT: v_readlane_b32 s80, v32, 22
; VI-NEXT: v_readlane_b32 s71, v32, 21
; VI-NEXT: v_readlane_b32 s70, v32, 20
; VI-NEXT: v_readlane_b32 s69, v32, 19
; VI-NEXT: v_readlane_b32 s68, v32, 18
; VI-NEXT: v_readlane_b32 s67, v32, 17
; VI-NEXT: v_readlane_b32 s66, v32, 16
; VI-NEXT: v_readlane_b32 s65, v32, 15
; VI-NEXT: v_readlane_b32 s64, v32, 14
; VI-NEXT: v_readlane_b32 s55, v32, 13
; VI-NEXT: v_readlane_b32 s54, v32, 12
; VI-NEXT: v_readlane_b32 s53, v32, 11
; VI-NEXT: v_readlane_b32 s52, v32, 10
; VI-NEXT: v_readlane_b32 s51, v32, 9
; VI-NEXT: v_readlane_b32 s50, v32, 8
; VI-NEXT: v_readlane_b32 s49, v32, 7
; VI-NEXT: v_readlane_b32 s48, v32, 6
; VI-NEXT: v_readlane_b32 s39, v32, 5
; VI-NEXT: v_readlane_b32 s38, v32, 4
; VI-NEXT: v_readlane_b32 s37, v32, 3
; VI-NEXT: v_readlane_b32 s36, v32, 2
; VI-NEXT: v_readlane_b32 s35, v32, 1
; VI-NEXT: v_readlane_b32 s34, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v24i32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB19_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB19_3
; GFX9-NEXT: .LBB19_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB19_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB19_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_mov_b32_e32 v23, 0x200
; GFX9-NEXT: v_pk_add_f16 v0, s36, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s37, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, s38, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, s39, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, s40, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, s41, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, s42, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, s43, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, s44, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, s45, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, s46, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, s47, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, s48, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, s49, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, s50, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, s51, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB19_6
; GFX9-NEXT: .LBB19_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB19_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48f16_to_v24i32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB19_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB19_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB19_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB19_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <24 x i32>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <24 x i32>
br label %end
end:
%phi = phi <24 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x i32> %phi
}
define <12 x i64> @bitcast_v24f32_to_v12i64(<24 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v12i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB20_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v23, 1.0, v23
; SI-NEXT: v_add_f32_e32 v22, 1.0, v22
; SI-NEXT: v_add_f32_e32 v21, 1.0, v21
; SI-NEXT: v_add_f32_e32 v20, 1.0, v20
; SI-NEXT: v_add_f32_e32 v19, 1.0, v19
; SI-NEXT: v_add_f32_e32 v18, 1.0, v18
; SI-NEXT: v_add_f32_e32 v17, 1.0, v17
; SI-NEXT: v_add_f32_e32 v16, 1.0, v16
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
; SI-NEXT: .LBB20_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v12i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB20_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v23, 1.0, v23
; VI-NEXT: v_add_f32_e32 v22, 1.0, v22
; VI-NEXT: v_add_f32_e32 v21, 1.0, v21
; VI-NEXT: v_add_f32_e32 v20, 1.0, v20
; VI-NEXT: v_add_f32_e32 v19, 1.0, v19
; VI-NEXT: v_add_f32_e32 v18, 1.0, v18
; VI-NEXT: v_add_f32_e32 v17, 1.0, v17
; VI-NEXT: v_add_f32_e32 v16, 1.0, v16
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: .LBB20_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v12i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB20_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v23, 1.0, v23
; GFX9-NEXT: v_add_f32_e32 v22, 1.0, v22
; GFX9-NEXT: v_add_f32_e32 v21, 1.0, v21
; GFX9-NEXT: v_add_f32_e32 v20, 1.0, v20
; GFX9-NEXT: v_add_f32_e32 v19, 1.0, v19
; GFX9-NEXT: v_add_f32_e32 v18, 1.0, v18
; GFX9-NEXT: v_add_f32_e32 v17, 1.0, v17
; GFX9-NEXT: v_add_f32_e32 v16, 1.0, v16
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: .LBB20_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24f32_to_v12i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB20_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: .LBB20_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define inreg <12 x i64> @bitcast_v24f32_to_v12i64_scalar(<24 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v12i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s36, 0
; SI-NEXT: v_writelane_b32 v32, s37, 1
; SI-NEXT: v_writelane_b32 v32, s38, 2
; SI-NEXT: v_writelane_b32 v32, s39, 3
; SI-NEXT: v_writelane_b32 v32, s48, 4
; SI-NEXT: v_writelane_b32 v32, s49, 5
; SI-NEXT: v_writelane_b32 v32, s50, 6
; SI-NEXT: v_writelane_b32 v32, s51, 7
; SI-NEXT: v_writelane_b32 v32, s52, 8
; SI-NEXT: v_writelane_b32 v32, s53, 9
; SI-NEXT: v_writelane_b32 v32, s54, 10
; SI-NEXT: v_writelane_b32 v32, s55, 11
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_mov_b32 s49, s29
; SI-NEXT: s_mov_b32 s48, s28
; SI-NEXT: s_mov_b32 s47, s27
; SI-NEXT: s_mov_b32 s46, s26
; SI-NEXT: s_mov_b32 s45, s25
; SI-NEXT: s_mov_b32 s44, s24
; SI-NEXT: s_mov_b32 s43, s23
; SI-NEXT: s_mov_b32 s42, s22
; SI-NEXT: s_mov_b32 s41, s21
; SI-NEXT: s_mov_b32 s40, s20
; SI-NEXT: s_mov_b32 s39, s19
; SI-NEXT: s_mov_b32 s38, s18
; SI-NEXT: s_mov_b32 s37, s17
; SI-NEXT: s_mov_b32 s36, s16
; SI-NEXT: v_readfirstlane_b32 s59, v9
; SI-NEXT: v_readfirstlane_b32 s58, v8
; SI-NEXT: v_readfirstlane_b32 s57, v7
; SI-NEXT: v_readfirstlane_b32 s56, v6
; SI-NEXT: v_readfirstlane_b32 s55, v5
; SI-NEXT: v_readfirstlane_b32 s54, v4
; SI-NEXT: v_readfirstlane_b32 s53, v3
; SI-NEXT: v_readfirstlane_b32 s52, v2
; SI-NEXT: v_readfirstlane_b32 s51, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s50, v0
; SI-NEXT: s_cbranch_scc0 .LBB21_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB21_3
; SI-NEXT: .LBB21_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB21_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB21_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f32_e64 v23, s59, 1.0
; SI-NEXT: v_add_f32_e64 v22, s58, 1.0
; SI-NEXT: v_add_f32_e64 v21, s57, 1.0
; SI-NEXT: v_add_f32_e64 v20, s56, 1.0
; SI-NEXT: v_add_f32_e64 v19, s55, 1.0
; SI-NEXT: v_add_f32_e64 v18, s54, 1.0
; SI-NEXT: v_add_f32_e64 v17, s53, 1.0
; SI-NEXT: v_add_f32_e64 v16, s52, 1.0
; SI-NEXT: v_add_f32_e64 v15, s51, 1.0
; SI-NEXT: v_add_f32_e64 v14, s50, 1.0
; SI-NEXT: v_add_f32_e64 v13, s49, 1.0
; SI-NEXT: v_add_f32_e64 v12, s48, 1.0
; SI-NEXT: v_add_f32_e64 v11, s47, 1.0
; SI-NEXT: v_add_f32_e64 v10, s46, 1.0
; SI-NEXT: v_add_f32_e64 v9, s45, 1.0
; SI-NEXT: v_add_f32_e64 v8, s44, 1.0
; SI-NEXT: v_add_f32_e64 v7, s43, 1.0
; SI-NEXT: v_add_f32_e64 v6, s42, 1.0
; SI-NEXT: v_add_f32_e64 v5, s41, 1.0
; SI-NEXT: v_add_f32_e64 v4, s40, 1.0
; SI-NEXT: v_add_f32_e64 v3, s39, 1.0
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
; SI-NEXT: s_branch .LBB21_6
; SI-NEXT: .LBB21_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB21_6: ; %end
; SI-NEXT: v_readlane_b32 s55, v32, 11
; SI-NEXT: v_readlane_b32 s54, v32, 10
; SI-NEXT: v_readlane_b32 s53, v32, 9
; SI-NEXT: v_readlane_b32 s52, v32, 8
; SI-NEXT: v_readlane_b32 s51, v32, 7
; SI-NEXT: v_readlane_b32 s50, v32, 6
; SI-NEXT: v_readlane_b32 s49, v32, 5
; SI-NEXT: v_readlane_b32 s48, v32, 4
; SI-NEXT: v_readlane_b32 s39, v32, 3
; SI-NEXT: v_readlane_b32 s38, v32, 2
; SI-NEXT: v_readlane_b32 s37, v32, 1
; SI-NEXT: v_readlane_b32 s36, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v12i64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s36, 0
; VI-NEXT: v_writelane_b32 v32, s37, 1
; VI-NEXT: v_writelane_b32 v32, s38, 2
; VI-NEXT: v_writelane_b32 v32, s39, 3
; VI-NEXT: v_writelane_b32 v32, s48, 4
; VI-NEXT: v_writelane_b32 v32, s49, 5
; VI-NEXT: v_writelane_b32 v32, s50, 6
; VI-NEXT: v_writelane_b32 v32, s51, 7
; VI-NEXT: v_writelane_b32 v32, s52, 8
; VI-NEXT: v_writelane_b32 v32, s53, 9
; VI-NEXT: v_writelane_b32 v32, s54, 10
; VI-NEXT: v_writelane_b32 v32, s55, 11
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_mov_b32 s49, s29
; VI-NEXT: s_mov_b32 s48, s28
; VI-NEXT: s_mov_b32 s47, s27
; VI-NEXT: s_mov_b32 s46, s26
; VI-NEXT: s_mov_b32 s45, s25
; VI-NEXT: s_mov_b32 s44, s24
; VI-NEXT: s_mov_b32 s43, s23
; VI-NEXT: s_mov_b32 s42, s22
; VI-NEXT: s_mov_b32 s41, s21
; VI-NEXT: s_mov_b32 s40, s20
; VI-NEXT: s_mov_b32 s39, s19
; VI-NEXT: s_mov_b32 s38, s18
; VI-NEXT: s_mov_b32 s37, s17
; VI-NEXT: s_mov_b32 s36, s16
; VI-NEXT: v_readfirstlane_b32 s59, v9
; VI-NEXT: v_readfirstlane_b32 s58, v8
; VI-NEXT: v_readfirstlane_b32 s57, v7
; VI-NEXT: v_readfirstlane_b32 s56, v6
; VI-NEXT: v_readfirstlane_b32 s55, v5
; VI-NEXT: v_readfirstlane_b32 s54, v4
; VI-NEXT: v_readfirstlane_b32 s53, v3
; VI-NEXT: v_readfirstlane_b32 s52, v2
; VI-NEXT: v_readfirstlane_b32 s51, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s50, v0
; VI-NEXT: s_cbranch_scc0 .LBB21_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB21_3
; VI-NEXT: .LBB21_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB21_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB21_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f32_e64 v23, s59, 1.0
; VI-NEXT: v_add_f32_e64 v22, s58, 1.0
; VI-NEXT: v_add_f32_e64 v21, s57, 1.0
; VI-NEXT: v_add_f32_e64 v20, s56, 1.0
; VI-NEXT: v_add_f32_e64 v19, s55, 1.0
; VI-NEXT: v_add_f32_e64 v18, s54, 1.0
; VI-NEXT: v_add_f32_e64 v17, s53, 1.0
; VI-NEXT: v_add_f32_e64 v16, s52, 1.0
; VI-NEXT: v_add_f32_e64 v15, s51, 1.0
; VI-NEXT: v_add_f32_e64 v14, s50, 1.0
; VI-NEXT: v_add_f32_e64 v13, s49, 1.0
; VI-NEXT: v_add_f32_e64 v12, s48, 1.0
; VI-NEXT: v_add_f32_e64 v11, s47, 1.0
; VI-NEXT: v_add_f32_e64 v10, s46, 1.0
; VI-NEXT: v_add_f32_e64 v9, s45, 1.0
; VI-NEXT: v_add_f32_e64 v8, s44, 1.0
; VI-NEXT: v_add_f32_e64 v7, s43, 1.0
; VI-NEXT: v_add_f32_e64 v6, s42, 1.0
; VI-NEXT: v_add_f32_e64 v5, s41, 1.0
; VI-NEXT: v_add_f32_e64 v4, s40, 1.0
; VI-NEXT: v_add_f32_e64 v3, s39, 1.0
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
; VI-NEXT: s_branch .LBB21_6
; VI-NEXT: .LBB21_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB21_6: ; %end
; VI-NEXT: v_readlane_b32 s55, v32, 11
; VI-NEXT: v_readlane_b32 s54, v32, 10
; VI-NEXT: v_readlane_b32 s53, v32, 9
; VI-NEXT: v_readlane_b32 s52, v32, 8
; VI-NEXT: v_readlane_b32 s51, v32, 7
; VI-NEXT: v_readlane_b32 s50, v32, 6
; VI-NEXT: v_readlane_b32 s49, v32, 5
; VI-NEXT: v_readlane_b32 s48, v32, 4
; VI-NEXT: v_readlane_b32 s39, v32, 3
; VI-NEXT: v_readlane_b32 s38, v32, 2
; VI-NEXT: v_readlane_b32 s37, v32, 1
; VI-NEXT: v_readlane_b32 s36, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v12i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_mov_b32 s49, s29
; GFX9-NEXT: s_mov_b32 s48, s28
; GFX9-NEXT: s_mov_b32 s47, s27
; GFX9-NEXT: s_mov_b32 s46, s26
; GFX9-NEXT: s_mov_b32 s45, s25
; GFX9-NEXT: s_mov_b32 s44, s24
; GFX9-NEXT: s_mov_b32 s43, s23
; GFX9-NEXT: s_mov_b32 s42, s22
; GFX9-NEXT: s_mov_b32 s41, s21
; GFX9-NEXT: s_mov_b32 s40, s20
; GFX9-NEXT: s_mov_b32 s39, s19
; GFX9-NEXT: s_mov_b32 s38, s18
; GFX9-NEXT: s_mov_b32 s37, s17
; GFX9-NEXT: s_mov_b32 s36, s16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s55, v5
; GFX9-NEXT: v_readfirstlane_b32 s54, v4
; GFX9-NEXT: v_readfirstlane_b32 s53, v3
; GFX9-NEXT: v_readfirstlane_b32 s52, v2
; GFX9-NEXT: v_readfirstlane_b32 s51, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s50, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB21_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB21_3
; GFX9-NEXT: .LBB21_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB21_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB21_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e64 v23, s59, 1.0
; GFX9-NEXT: v_add_f32_e64 v22, s58, 1.0
; GFX9-NEXT: v_add_f32_e64 v21, s57, 1.0
; GFX9-NEXT: v_add_f32_e64 v20, s56, 1.0
; GFX9-NEXT: v_add_f32_e64 v19, s55, 1.0
; GFX9-NEXT: v_add_f32_e64 v18, s54, 1.0
; GFX9-NEXT: v_add_f32_e64 v17, s53, 1.0
; GFX9-NEXT: v_add_f32_e64 v16, s52, 1.0
; GFX9-NEXT: v_add_f32_e64 v15, s51, 1.0
; GFX9-NEXT: v_add_f32_e64 v14, s50, 1.0
; GFX9-NEXT: v_add_f32_e64 v13, s49, 1.0
; GFX9-NEXT: v_add_f32_e64 v12, s48, 1.0
; GFX9-NEXT: v_add_f32_e64 v11, s47, 1.0
; GFX9-NEXT: v_add_f32_e64 v10, s46, 1.0
; GFX9-NEXT: v_add_f32_e64 v9, s45, 1.0
; GFX9-NEXT: v_add_f32_e64 v8, s44, 1.0
; GFX9-NEXT: v_add_f32_e64 v7, s43, 1.0
; GFX9-NEXT: v_add_f32_e64 v6, s42, 1.0
; GFX9-NEXT: v_add_f32_e64 v5, s41, 1.0
; GFX9-NEXT: v_add_f32_e64 v4, s40, 1.0
; GFX9-NEXT: v_add_f32_e64 v3, s39, 1.0
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
; GFX9-NEXT: s_branch .LBB21_6
; GFX9-NEXT: .LBB21_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB21_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24f32_to_v12i64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: v_writelane_b32 v32, s39, 3
; GFX11-NEXT: v_writelane_b32 v32, s48, 4
; GFX11-NEXT: v_writelane_b32 v32, s49, 5
; GFX11-NEXT: v_writelane_b32 v32, s50, 6
; GFX11-NEXT: v_writelane_b32 v32, s51, 7
; GFX11-NEXT: v_writelane_b32 v32, s52, 8
; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_writelane_b32 v32, s54, 10
; GFX11-NEXT: v_writelane_b32 v32, s55, 11
; GFX11-NEXT: s_mov_b32 s36, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
; GFX11-NEXT: v_readfirstlane_b32 s59, v5
; GFX11-NEXT: v_readfirstlane_b32 s58, v4
; GFX11-NEXT: v_readfirstlane_b32 s57, v3
; GFX11-NEXT: v_readfirstlane_b32 s56, v2
; GFX11-NEXT: v_readfirstlane_b32 s55, v1
; GFX11-NEXT: v_readfirstlane_b32 s54, v0
; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_mov_b32 s52, s28
; GFX11-NEXT: s_mov_b32 s51, s27
; GFX11-NEXT: s_mov_b32 s50, s26
; GFX11-NEXT: s_mov_b32 s49, s25
; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
; GFX11-NEXT: s_mov_b32 s40, s16
; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB21_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: .LBB21_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB21_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_f32_e64 v23, s59, 1.0
; GFX11-NEXT: v_add_f32_e64 v22, s58, 1.0
; GFX11-NEXT: v_add_f32_e64 v21, s57, 1.0
; GFX11-NEXT: v_add_f32_e64 v20, s56, 1.0
; GFX11-NEXT: v_add_f32_e64 v19, s55, 1.0
; GFX11-NEXT: v_add_f32_e64 v18, s54, 1.0
; GFX11-NEXT: v_add_f32_e64 v17, s53, 1.0
; GFX11-NEXT: v_add_f32_e64 v16, s52, 1.0
; GFX11-NEXT: v_add_f32_e64 v15, s51, 1.0
; GFX11-NEXT: v_add_f32_e64 v14, s50, 1.0
; GFX11-NEXT: v_add_f32_e64 v13, s49, 1.0
; GFX11-NEXT: v_add_f32_e64 v12, s48, 1.0
; GFX11-NEXT: v_add_f32_e64 v11, s47, 1.0
; GFX11-NEXT: v_add_f32_e64 v10, s46, 1.0
; GFX11-NEXT: v_add_f32_e64 v9, s45, 1.0
; GFX11-NEXT: v_add_f32_e64 v8, s44, 1.0
; GFX11-NEXT: v_add_f32_e64 v7, s43, 1.0
; GFX11-NEXT: v_add_f32_e64 v6, s42, 1.0
; GFX11-NEXT: v_add_f32_e64 v5, s41, 1.0
; GFX11-NEXT: v_add_f32_e64 v4, s40, 1.0
; GFX11-NEXT: v_add_f32_e64 v3, s39, 1.0
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
; GFX11-NEXT: s_branch .LBB21_5
; GFX11-NEXT: .LBB21_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v1, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v3, s39
; GFX11-NEXT: v_dual_mov_b32 v4, s40 :: v_dual_mov_b32 v5, s41
; GFX11-NEXT: v_dual_mov_b32 v6, s42 :: v_dual_mov_b32 v7, s43
; GFX11-NEXT: v_dual_mov_b32 v8, s44 :: v_dual_mov_b32 v9, s45
; GFX11-NEXT: v_dual_mov_b32 v10, s46 :: v_dual_mov_b32 v11, s47
; GFX11-NEXT: v_dual_mov_b32 v12, s48 :: v_dual_mov_b32 v13, s49
; GFX11-NEXT: v_dual_mov_b32 v14, s50 :: v_dual_mov_b32 v15, s51
; GFX11-NEXT: v_dual_mov_b32 v16, s52 :: v_dual_mov_b32 v17, s53
; GFX11-NEXT: v_dual_mov_b32 v18, s54 :: v_dual_mov_b32 v19, s55
; GFX11-NEXT: v_dual_mov_b32 v20, s56 :: v_dual_mov_b32 v21, s57
; GFX11-NEXT: v_dual_mov_b32 v22, s58 :: v_dual_mov_b32 v23, s59
; GFX11-NEXT: v_dual_mov_b32 v24, s60 :: v_dual_mov_b32 v25, s61
; GFX11-NEXT: v_dual_mov_b32 v26, s62 :: v_dual_mov_b32 v27, s63
; GFX11-NEXT: v_dual_mov_b32 v28, s64 :: v_dual_mov_b32 v29, s65
; GFX11-NEXT: v_dual_mov_b32 v30, s66 :: v_dual_mov_b32 v31, s67
; GFX11-NEXT: .LBB21_5: ; %end
; GFX11-NEXT: v_readlane_b32 s55, v32, 11
; GFX11-NEXT: v_readlane_b32 s54, v32, 10
; GFX11-NEXT: v_readlane_b32 s53, v32, 9
; GFX11-NEXT: v_readlane_b32 s52, v32, 8
; GFX11-NEXT: v_readlane_b32 s51, v32, 7
; GFX11-NEXT: v_readlane_b32 s50, v32, 6
; GFX11-NEXT: v_readlane_b32 s49, v32, 5
; GFX11-NEXT: v_readlane_b32 s48, v32, 4
; GFX11-NEXT: v_readlane_b32 s39, v32, 3
; GFX11-NEXT: v_readlane_b32 s38, v32, 2
; GFX11-NEXT: v_readlane_b32 s37, v32, 1
; GFX11-NEXT: v_readlane_b32 s36, v32, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v32, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define <24 x float> @bitcast_v12i64_to_v24f32(<12 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v24f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB22_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: .LBB22_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v24f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB22_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: .LBB22_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v24f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB22_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, 3, v22
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v23, vcc
; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, 3, v20
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, 3, v18
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, 3, v16
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: .LBB22_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v24f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB22_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
; GFX11-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: .LBB22_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define inreg <24 x float> @bitcast_v12i64_to_v24f32_scalar(<12 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v24f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s7, v8
; SI-NEXT: v_readfirstlane_b32 s8, v7
; SI-NEXT: v_readfirstlane_b32 s9, v6
; SI-NEXT: v_readfirstlane_b32 s10, v5
; SI-NEXT: v_readfirstlane_b32 s11, v4
; SI-NEXT: v_readfirstlane_b32 s12, v3
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s15, v0
; SI-NEXT: s_cbranch_scc0 .LBB23_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB23_3
; SI-NEXT: .LBB23_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB23_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB23_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
; SI-NEXT: s_add_u32 s9, s9, 3
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s11, s11, 3
; SI-NEXT: s_addc_u32 s10, s10, 0
; SI-NEXT: s_add_u32 s13, s13, 3
; SI-NEXT: s_addc_u32 s12, s12, 0
; SI-NEXT: s_add_u32 s15, s15, 3
; SI-NEXT: s_addc_u32 s14, s14, 0
; SI-NEXT: s_add_u32 s28, s28, 3
; SI-NEXT: s_addc_u32 s29, s29, 0
; SI-NEXT: s_add_u32 s26, s26, 3
; SI-NEXT: s_addc_u32 s27, s27, 0
; SI-NEXT: s_add_u32 s24, s24, 3
; SI-NEXT: s_addc_u32 s25, s25, 0
; SI-NEXT: s_add_u32 s22, s22, 3
; SI-NEXT: s_addc_u32 s23, s23, 0
; SI-NEXT: s_add_u32 s20, s20, 3
; SI-NEXT: s_addc_u32 s21, s21, 0
; SI-NEXT: s_add_u32 s18, s18, 3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
; SI-NEXT: .LBB23_5: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s15
; SI-NEXT: v_mov_b32_e32 v15, s14
; SI-NEXT: v_mov_b32_e32 v16, s13
; SI-NEXT: v_mov_b32_e32 v17, s12
; SI-NEXT: v_mov_b32_e32 v18, s11
; SI-NEXT: v_mov_b32_e32 v19, s10
; SI-NEXT: v_mov_b32_e32 v20, s9
; SI-NEXT: v_mov_b32_e32 v21, s8
; SI-NEXT: v_mov_b32_e32 v22, s7
; SI-NEXT: v_mov_b32_e32 v23, s6
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v24f32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB23_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB23_3
; VI-NEXT: .LBB23_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB23_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB23_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
; VI-NEXT: s_add_u32 s9, s9, 3
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s11, s11, 3
; VI-NEXT: s_addc_u32 s10, s10, 0
; VI-NEXT: s_add_u32 s13, s13, 3
; VI-NEXT: s_addc_u32 s12, s12, 0
; VI-NEXT: s_add_u32 s15, s15, 3
; VI-NEXT: s_addc_u32 s14, s14, 0
; VI-NEXT: s_add_u32 s28, s28, 3
; VI-NEXT: s_addc_u32 s29, s29, 0
; VI-NEXT: s_add_u32 s26, s26, 3
; VI-NEXT: s_addc_u32 s27, s27, 0
; VI-NEXT: s_add_u32 s24, s24, 3
; VI-NEXT: s_addc_u32 s25, s25, 0
; VI-NEXT: s_add_u32 s22, s22, 3
; VI-NEXT: s_addc_u32 s23, s23, 0
; VI-NEXT: s_add_u32 s20, s20, 3
; VI-NEXT: s_addc_u32 s21, s21, 0
; VI-NEXT: s_add_u32 s18, s18, 3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
; VI-NEXT: .LBB23_5: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v24f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB23_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB23_3
; GFX9-NEXT: .LBB23_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB23_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB23_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
; GFX9-NEXT: s_add_u32 s9, s9, 3
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s11, s11, 3
; GFX9-NEXT: s_addc_u32 s10, s10, 0
; GFX9-NEXT: s_add_u32 s13, s13, 3
; GFX9-NEXT: s_addc_u32 s12, s12, 0
; GFX9-NEXT: s_add_u32 s15, s15, 3
; GFX9-NEXT: s_addc_u32 s14, s14, 0
; GFX9-NEXT: s_add_u32 s28, s28, 3
; GFX9-NEXT: s_addc_u32 s29, s29, 0
; GFX9-NEXT: s_add_u32 s26, s26, 3
; GFX9-NEXT: s_addc_u32 s27, s27, 0
; GFX9-NEXT: s_add_u32 s24, s24, 3
; GFX9-NEXT: s_addc_u32 s25, s25, 0
; GFX9-NEXT: s_add_u32 s22, s22, 3
; GFX9-NEXT: s_addc_u32 s23, s23, 0
; GFX9-NEXT: s_add_u32 s20, s20, 3
; GFX9-NEXT: s_addc_u32 s21, s21, 0
; GFX9-NEXT: s_add_u32 s18, s18, 3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
; GFX9-NEXT: .LBB23_5: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v24f32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s10, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB23_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s10, -1
; GFX11-NEXT: .LBB23_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s10, s10, exec_lo
; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s10, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB23_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
; GFX11-NEXT: s_add_u32 s7, s7, 3
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s9, s9, 3
; GFX11-NEXT: s_addc_u32 s8, s8, 0
; GFX11-NEXT: s_add_u32 s28, s28, 3
; GFX11-NEXT: s_addc_u32 s29, s29, 0
; GFX11-NEXT: s_add_u32 s26, s26, 3
; GFX11-NEXT: s_addc_u32 s27, s27, 0
; GFX11-NEXT: s_add_u32 s24, s24, 3
; GFX11-NEXT: s_addc_u32 s25, s25, 0
; GFX11-NEXT: s_add_u32 s22, s22, 3
; GFX11-NEXT: s_addc_u32 s23, s23, 0
; GFX11-NEXT: s_add_u32 s20, s20, 3
; GFX11-NEXT: s_addc_u32 s21, s21, 0
; GFX11-NEXT: s_add_u32 s18, s18, 3
; GFX11-NEXT: s_addc_u32 s19, s19, 0
; GFX11-NEXT: s_add_u32 s16, s16, 3
; GFX11-NEXT: s_addc_u32 s17, s17, 0
; GFX11-NEXT: s_add_u32 s2, s2, 3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: .LBB23_4: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define <12 x double> @bitcast_v24f32_to_v12f64(<24 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v12f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB24_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v23, 1.0, v23
; SI-NEXT: v_add_f32_e32 v22, 1.0, v22
; SI-NEXT: v_add_f32_e32 v21, 1.0, v21
; SI-NEXT: v_add_f32_e32 v20, 1.0, v20
; SI-NEXT: v_add_f32_e32 v19, 1.0, v19
; SI-NEXT: v_add_f32_e32 v18, 1.0, v18
; SI-NEXT: v_add_f32_e32 v17, 1.0, v17
; SI-NEXT: v_add_f32_e32 v16, 1.0, v16
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
; SI-NEXT: .LBB24_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v12f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB24_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v23, 1.0, v23
; VI-NEXT: v_add_f32_e32 v22, 1.0, v22
; VI-NEXT: v_add_f32_e32 v21, 1.0, v21
; VI-NEXT: v_add_f32_e32 v20, 1.0, v20
; VI-NEXT: v_add_f32_e32 v19, 1.0, v19
; VI-NEXT: v_add_f32_e32 v18, 1.0, v18
; VI-NEXT: v_add_f32_e32 v17, 1.0, v17
; VI-NEXT: v_add_f32_e32 v16, 1.0, v16
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: .LBB24_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v12f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB24_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v23, 1.0, v23
; GFX9-NEXT: v_add_f32_e32 v22, 1.0, v22
; GFX9-NEXT: v_add_f32_e32 v21, 1.0, v21
; GFX9-NEXT: v_add_f32_e32 v20, 1.0, v20
; GFX9-NEXT: v_add_f32_e32 v19, 1.0, v19
; GFX9-NEXT: v_add_f32_e32 v18, 1.0, v18
; GFX9-NEXT: v_add_f32_e32 v17, 1.0, v17
; GFX9-NEXT: v_add_f32_e32 v16, 1.0, v16
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: .LBB24_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24f32_to_v12f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB24_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-NEXT: .LBB24_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define inreg <12 x double> @bitcast_v24f32_to_v12f64_scalar(<24 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v12f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s36, 0
; SI-NEXT: v_writelane_b32 v32, s37, 1
; SI-NEXT: v_writelane_b32 v32, s38, 2
; SI-NEXT: v_writelane_b32 v32, s39, 3
; SI-NEXT: v_writelane_b32 v32, s48, 4
; SI-NEXT: v_writelane_b32 v32, s49, 5
; SI-NEXT: v_writelane_b32 v32, s50, 6
; SI-NEXT: v_writelane_b32 v32, s51, 7
; SI-NEXT: v_writelane_b32 v32, s52, 8
; SI-NEXT: v_writelane_b32 v32, s53, 9
; SI-NEXT: v_writelane_b32 v32, s54, 10
; SI-NEXT: v_writelane_b32 v32, s55, 11
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_mov_b32 s49, s29
; SI-NEXT: s_mov_b32 s48, s28
; SI-NEXT: s_mov_b32 s47, s27
; SI-NEXT: s_mov_b32 s46, s26
; SI-NEXT: s_mov_b32 s45, s25
; SI-NEXT: s_mov_b32 s44, s24
; SI-NEXT: s_mov_b32 s43, s23
; SI-NEXT: s_mov_b32 s42, s22
; SI-NEXT: s_mov_b32 s41, s21
; SI-NEXT: s_mov_b32 s40, s20
; SI-NEXT: s_mov_b32 s39, s19
; SI-NEXT: s_mov_b32 s38, s18
; SI-NEXT: s_mov_b32 s37, s17
; SI-NEXT: s_mov_b32 s36, s16
; SI-NEXT: v_readfirstlane_b32 s59, v9
; SI-NEXT: v_readfirstlane_b32 s58, v8
; SI-NEXT: v_readfirstlane_b32 s57, v7
; SI-NEXT: v_readfirstlane_b32 s56, v6
; SI-NEXT: v_readfirstlane_b32 s55, v5
; SI-NEXT: v_readfirstlane_b32 s54, v4
; SI-NEXT: v_readfirstlane_b32 s53, v3
; SI-NEXT: v_readfirstlane_b32 s52, v2
; SI-NEXT: v_readfirstlane_b32 s51, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s50, v0
; SI-NEXT: s_cbranch_scc0 .LBB25_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB25_3
; SI-NEXT: .LBB25_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB25_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB25_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f32_e64 v23, s59, 1.0
; SI-NEXT: v_add_f32_e64 v22, s58, 1.0
; SI-NEXT: v_add_f32_e64 v21, s57, 1.0
; SI-NEXT: v_add_f32_e64 v20, s56, 1.0
; SI-NEXT: v_add_f32_e64 v19, s55, 1.0
; SI-NEXT: v_add_f32_e64 v18, s54, 1.0
; SI-NEXT: v_add_f32_e64 v17, s53, 1.0
; SI-NEXT: v_add_f32_e64 v16, s52, 1.0
; SI-NEXT: v_add_f32_e64 v15, s51, 1.0
; SI-NEXT: v_add_f32_e64 v14, s50, 1.0
; SI-NEXT: v_add_f32_e64 v13, s49, 1.0
; SI-NEXT: v_add_f32_e64 v12, s48, 1.0
; SI-NEXT: v_add_f32_e64 v11, s47, 1.0
; SI-NEXT: v_add_f32_e64 v10, s46, 1.0
; SI-NEXT: v_add_f32_e64 v9, s45, 1.0
; SI-NEXT: v_add_f32_e64 v8, s44, 1.0
; SI-NEXT: v_add_f32_e64 v7, s43, 1.0
; SI-NEXT: v_add_f32_e64 v6, s42, 1.0
; SI-NEXT: v_add_f32_e64 v5, s41, 1.0
; SI-NEXT: v_add_f32_e64 v4, s40, 1.0
; SI-NEXT: v_add_f32_e64 v3, s39, 1.0
; SI-NEXT: v_add_f32_e64 v2, s38, 1.0
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
; SI-NEXT: v_add_f32_e64 v0, s36, 1.0
; SI-NEXT: s_branch .LBB25_6
; SI-NEXT: .LBB25_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB25_6: ; %end
; SI-NEXT: v_readlane_b32 s55, v32, 11
; SI-NEXT: v_readlane_b32 s54, v32, 10
; SI-NEXT: v_readlane_b32 s53, v32, 9
; SI-NEXT: v_readlane_b32 s52, v32, 8
; SI-NEXT: v_readlane_b32 s51, v32, 7
; SI-NEXT: v_readlane_b32 s50, v32, 6
; SI-NEXT: v_readlane_b32 s49, v32, 5
; SI-NEXT: v_readlane_b32 s48, v32, 4
; SI-NEXT: v_readlane_b32 s39, v32, 3
; SI-NEXT: v_readlane_b32 s38, v32, 2
; SI-NEXT: v_readlane_b32 s37, v32, 1
; SI-NEXT: v_readlane_b32 s36, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v12f64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s36, 0
; VI-NEXT: v_writelane_b32 v32, s37, 1
; VI-NEXT: v_writelane_b32 v32, s38, 2
; VI-NEXT: v_writelane_b32 v32, s39, 3
; VI-NEXT: v_writelane_b32 v32, s48, 4
; VI-NEXT: v_writelane_b32 v32, s49, 5
; VI-NEXT: v_writelane_b32 v32, s50, 6
; VI-NEXT: v_writelane_b32 v32, s51, 7
; VI-NEXT: v_writelane_b32 v32, s52, 8
; VI-NEXT: v_writelane_b32 v32, s53, 9
; VI-NEXT: v_writelane_b32 v32, s54, 10
; VI-NEXT: v_writelane_b32 v32, s55, 11
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_mov_b32 s49, s29
; VI-NEXT: s_mov_b32 s48, s28
; VI-NEXT: s_mov_b32 s47, s27
; VI-NEXT: s_mov_b32 s46, s26
; VI-NEXT: s_mov_b32 s45, s25
; VI-NEXT: s_mov_b32 s44, s24
; VI-NEXT: s_mov_b32 s43, s23
; VI-NEXT: s_mov_b32 s42, s22
; VI-NEXT: s_mov_b32 s41, s21
; VI-NEXT: s_mov_b32 s40, s20
; VI-NEXT: s_mov_b32 s39, s19
; VI-NEXT: s_mov_b32 s38, s18
; VI-NEXT: s_mov_b32 s37, s17
; VI-NEXT: s_mov_b32 s36, s16
; VI-NEXT: v_readfirstlane_b32 s59, v9
; VI-NEXT: v_readfirstlane_b32 s58, v8
; VI-NEXT: v_readfirstlane_b32 s57, v7
; VI-NEXT: v_readfirstlane_b32 s56, v6
; VI-NEXT: v_readfirstlane_b32 s55, v5
; VI-NEXT: v_readfirstlane_b32 s54, v4
; VI-NEXT: v_readfirstlane_b32 s53, v3
; VI-NEXT: v_readfirstlane_b32 s52, v2
; VI-NEXT: v_readfirstlane_b32 s51, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s50, v0
; VI-NEXT: s_cbranch_scc0 .LBB25_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB25_3
; VI-NEXT: .LBB25_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB25_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB25_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f32_e64 v23, s59, 1.0
; VI-NEXT: v_add_f32_e64 v22, s58, 1.0
; VI-NEXT: v_add_f32_e64 v21, s57, 1.0
; VI-NEXT: v_add_f32_e64 v20, s56, 1.0
; VI-NEXT: v_add_f32_e64 v19, s55, 1.0
; VI-NEXT: v_add_f32_e64 v18, s54, 1.0
; VI-NEXT: v_add_f32_e64 v17, s53, 1.0
; VI-NEXT: v_add_f32_e64 v16, s52, 1.0
; VI-NEXT: v_add_f32_e64 v15, s51, 1.0
; VI-NEXT: v_add_f32_e64 v14, s50, 1.0
; VI-NEXT: v_add_f32_e64 v13, s49, 1.0
; VI-NEXT: v_add_f32_e64 v12, s48, 1.0
; VI-NEXT: v_add_f32_e64 v11, s47, 1.0
; VI-NEXT: v_add_f32_e64 v10, s46, 1.0
; VI-NEXT: v_add_f32_e64 v9, s45, 1.0
; VI-NEXT: v_add_f32_e64 v8, s44, 1.0
; VI-NEXT: v_add_f32_e64 v7, s43, 1.0
; VI-NEXT: v_add_f32_e64 v6, s42, 1.0
; VI-NEXT: v_add_f32_e64 v5, s41, 1.0
; VI-NEXT: v_add_f32_e64 v4, s40, 1.0
; VI-NEXT: v_add_f32_e64 v3, s39, 1.0
; VI-NEXT: v_add_f32_e64 v2, s38, 1.0
; VI-NEXT: v_add_f32_e64 v1, s37, 1.0
; VI-NEXT: v_add_f32_e64 v0, s36, 1.0
; VI-NEXT: s_branch .LBB25_6
; VI-NEXT: .LBB25_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB25_6: ; %end
; VI-NEXT: v_readlane_b32 s55, v32, 11
; VI-NEXT: v_readlane_b32 s54, v32, 10
; VI-NEXT: v_readlane_b32 s53, v32, 9
; VI-NEXT: v_readlane_b32 s52, v32, 8
; VI-NEXT: v_readlane_b32 s51, v32, 7
; VI-NEXT: v_readlane_b32 s50, v32, 6
; VI-NEXT: v_readlane_b32 s49, v32, 5
; VI-NEXT: v_readlane_b32 s48, v32, 4
; VI-NEXT: v_readlane_b32 s39, v32, 3
; VI-NEXT: v_readlane_b32 s38, v32, 2
; VI-NEXT: v_readlane_b32 s37, v32, 1
; VI-NEXT: v_readlane_b32 s36, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v12f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_mov_b32 s49, s29
; GFX9-NEXT: s_mov_b32 s48, s28
; GFX9-NEXT: s_mov_b32 s47, s27
; GFX9-NEXT: s_mov_b32 s46, s26
; GFX9-NEXT: s_mov_b32 s45, s25
; GFX9-NEXT: s_mov_b32 s44, s24
; GFX9-NEXT: s_mov_b32 s43, s23
; GFX9-NEXT: s_mov_b32 s42, s22
; GFX9-NEXT: s_mov_b32 s41, s21
; GFX9-NEXT: s_mov_b32 s40, s20
; GFX9-NEXT: s_mov_b32 s39, s19
; GFX9-NEXT: s_mov_b32 s38, s18
; GFX9-NEXT: s_mov_b32 s37, s17
; GFX9-NEXT: s_mov_b32 s36, s16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s55, v5
; GFX9-NEXT: v_readfirstlane_b32 s54, v4
; GFX9-NEXT: v_readfirstlane_b32 s53, v3
; GFX9-NEXT: v_readfirstlane_b32 s52, v2
; GFX9-NEXT: v_readfirstlane_b32 s51, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s50, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB25_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB25_3
; GFX9-NEXT: .LBB25_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB25_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB25_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e64 v23, s59, 1.0
; GFX9-NEXT: v_add_f32_e64 v22, s58, 1.0
; GFX9-NEXT: v_add_f32_e64 v21, s57, 1.0
; GFX9-NEXT: v_add_f32_e64 v20, s56, 1.0
; GFX9-NEXT: v_add_f32_e64 v19, s55, 1.0
; GFX9-NEXT: v_add_f32_e64 v18, s54, 1.0
; GFX9-NEXT: v_add_f32_e64 v17, s53, 1.0
; GFX9-NEXT: v_add_f32_e64 v16, s52, 1.0
; GFX9-NEXT: v_add_f32_e64 v15, s51, 1.0
; GFX9-NEXT: v_add_f32_e64 v14, s50, 1.0
; GFX9-NEXT: v_add_f32_e64 v13, s49, 1.0
; GFX9-NEXT: v_add_f32_e64 v12, s48, 1.0
; GFX9-NEXT: v_add_f32_e64 v11, s47, 1.0
; GFX9-NEXT: v_add_f32_e64 v10, s46, 1.0
; GFX9-NEXT: v_add_f32_e64 v9, s45, 1.0
; GFX9-NEXT: v_add_f32_e64 v8, s44, 1.0
; GFX9-NEXT: v_add_f32_e64 v7, s43, 1.0
; GFX9-NEXT: v_add_f32_e64 v6, s42, 1.0
; GFX9-NEXT: v_add_f32_e64 v5, s41, 1.0
; GFX9-NEXT: v_add_f32_e64 v4, s40, 1.0
; GFX9-NEXT: v_add_f32_e64 v3, s39, 1.0
; GFX9-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s36, 1.0
; GFX9-NEXT: s_branch .LBB25_6
; GFX9-NEXT: .LBB25_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB25_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v24f32_to_v12f64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: v_writelane_b32 v32, s39, 3
; GFX11-NEXT: v_writelane_b32 v32, s48, 4
; GFX11-NEXT: v_writelane_b32 v32, s49, 5
; GFX11-NEXT: v_writelane_b32 v32, s50, 6
; GFX11-NEXT: v_writelane_b32 v32, s51, 7
; GFX11-NEXT: v_writelane_b32 v32, s52, 8
; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_writelane_b32 v32, s54, 10
; GFX11-NEXT: v_writelane_b32 v32, s55, 11
; GFX11-NEXT: s_mov_b32 s36, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
; GFX11-NEXT: v_readfirstlane_b32 s59, v5
; GFX11-NEXT: v_readfirstlane_b32 s58, v4
; GFX11-NEXT: v_readfirstlane_b32 s57, v3
; GFX11-NEXT: v_readfirstlane_b32 s56, v2
; GFX11-NEXT: v_readfirstlane_b32 s55, v1
; GFX11-NEXT: v_readfirstlane_b32 s54, v0
; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_mov_b32 s52, s28
; GFX11-NEXT: s_mov_b32 s51, s27
; GFX11-NEXT: s_mov_b32 s50, s26
; GFX11-NEXT: s_mov_b32 s49, s25
; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
; GFX11-NEXT: s_mov_b32 s40, s16
; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB25_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: .LBB25_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB25_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_f32_e64 v23, s59, 1.0
; GFX11-NEXT: v_add_f32_e64 v22, s58, 1.0
; GFX11-NEXT: v_add_f32_e64 v21, s57, 1.0
; GFX11-NEXT: v_add_f32_e64 v20, s56, 1.0
; GFX11-NEXT: v_add_f32_e64 v19, s55, 1.0
; GFX11-NEXT: v_add_f32_e64 v18, s54, 1.0
; GFX11-NEXT: v_add_f32_e64 v17, s53, 1.0
; GFX11-NEXT: v_add_f32_e64 v16, s52, 1.0
; GFX11-NEXT: v_add_f32_e64 v15, s51, 1.0
; GFX11-NEXT: v_add_f32_e64 v14, s50, 1.0
; GFX11-NEXT: v_add_f32_e64 v13, s49, 1.0
; GFX11-NEXT: v_add_f32_e64 v12, s48, 1.0
; GFX11-NEXT: v_add_f32_e64 v11, s47, 1.0
; GFX11-NEXT: v_add_f32_e64 v10, s46, 1.0
; GFX11-NEXT: v_add_f32_e64 v9, s45, 1.0
; GFX11-NEXT: v_add_f32_e64 v8, s44, 1.0
; GFX11-NEXT: v_add_f32_e64 v7, s43, 1.0
; GFX11-NEXT: v_add_f32_e64 v6, s42, 1.0
; GFX11-NEXT: v_add_f32_e64 v5, s41, 1.0
; GFX11-NEXT: v_add_f32_e64 v4, s40, 1.0
; GFX11-NEXT: v_add_f32_e64 v3, s39, 1.0
; GFX11-NEXT: v_add_f32_e64 v2, s38, 1.0
; GFX11-NEXT: v_add_f32_e64 v1, s37, 1.0
; GFX11-NEXT: v_add_f32_e64 v0, s36, 1.0
; GFX11-NEXT: s_branch .LBB25_5
; GFX11-NEXT: .LBB25_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v1, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v3, s39
; GFX11-NEXT: v_dual_mov_b32 v4, s40 :: v_dual_mov_b32 v5, s41
; GFX11-NEXT: v_dual_mov_b32 v6, s42 :: v_dual_mov_b32 v7, s43
; GFX11-NEXT: v_dual_mov_b32 v8, s44 :: v_dual_mov_b32 v9, s45
; GFX11-NEXT: v_dual_mov_b32 v10, s46 :: v_dual_mov_b32 v11, s47
; GFX11-NEXT: v_dual_mov_b32 v12, s48 :: v_dual_mov_b32 v13, s49
; GFX11-NEXT: v_dual_mov_b32 v14, s50 :: v_dual_mov_b32 v15, s51
; GFX11-NEXT: v_dual_mov_b32 v16, s52 :: v_dual_mov_b32 v17, s53
; GFX11-NEXT: v_dual_mov_b32 v18, s54 :: v_dual_mov_b32 v19, s55
; GFX11-NEXT: v_dual_mov_b32 v20, s56 :: v_dual_mov_b32 v21, s57
; GFX11-NEXT: v_dual_mov_b32 v22, s58 :: v_dual_mov_b32 v23, s59
; GFX11-NEXT: v_dual_mov_b32 v24, s60 :: v_dual_mov_b32 v25, s61
; GFX11-NEXT: v_dual_mov_b32 v26, s62 :: v_dual_mov_b32 v27, s63
; GFX11-NEXT: v_dual_mov_b32 v28, s64 :: v_dual_mov_b32 v29, s65
; GFX11-NEXT: v_dual_mov_b32 v30, s66 :: v_dual_mov_b32 v31, s67
; GFX11-NEXT: .LBB25_5: ; %end
; GFX11-NEXT: v_readlane_b32 s55, v32, 11
; GFX11-NEXT: v_readlane_b32 s54, v32, 10
; GFX11-NEXT: v_readlane_b32 s53, v32, 9
; GFX11-NEXT: v_readlane_b32 s52, v32, 8
; GFX11-NEXT: v_readlane_b32 s51, v32, 7
; GFX11-NEXT: v_readlane_b32 s50, v32, 6
; GFX11-NEXT: v_readlane_b32 s49, v32, 5
; GFX11-NEXT: v_readlane_b32 s48, v32, 4
; GFX11-NEXT: v_readlane_b32 s39, v32, 3
; GFX11-NEXT: v_readlane_b32 s38, v32, 2
; GFX11-NEXT: v_readlane_b32 s37, v32, 1
; GFX11-NEXT: v_readlane_b32 s36, v32, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v32, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define <24 x float> @bitcast_v12f64_to_v24f32(<12 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v24f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB26_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT: .LBB26_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v24f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB26_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: .LBB26_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v24f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB26_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: .LBB26_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12f64_to_v24f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB26_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: .LBB26_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define inreg <24 x float> @bitcast_v12f64_to_v24f32_scalar(<12 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v24f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s36, 0
; SI-NEXT: v_writelane_b32 v32, s37, 1
; SI-NEXT: v_writelane_b32 v32, s38, 2
; SI-NEXT: v_writelane_b32 v32, s39, 3
; SI-NEXT: v_writelane_b32 v32, s48, 4
; SI-NEXT: v_writelane_b32 v32, s49, 5
; SI-NEXT: v_writelane_b32 v32, s50, 6
; SI-NEXT: v_writelane_b32 v32, s51, 7
; SI-NEXT: v_writelane_b32 v32, s52, 8
; SI-NEXT: v_writelane_b32 v32, s53, 9
; SI-NEXT: v_writelane_b32 v32, s54, 10
; SI-NEXT: v_writelane_b32 v32, s55, 11
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_mov_b32 s49, s29
; SI-NEXT: s_mov_b32 s48, s28
; SI-NEXT: s_mov_b32 s47, s27
; SI-NEXT: s_mov_b32 s46, s26
; SI-NEXT: s_mov_b32 s45, s25
; SI-NEXT: s_mov_b32 s44, s24
; SI-NEXT: s_mov_b32 s43, s23
; SI-NEXT: s_mov_b32 s42, s22
; SI-NEXT: s_mov_b32 s41, s21
; SI-NEXT: s_mov_b32 s40, s20
; SI-NEXT: s_mov_b32 s39, s19
; SI-NEXT: s_mov_b32 s38, s18
; SI-NEXT: s_mov_b32 s37, s17
; SI-NEXT: s_mov_b32 s36, s16
; SI-NEXT: v_readfirstlane_b32 s59, v9
; SI-NEXT: v_readfirstlane_b32 s58, v8
; SI-NEXT: v_readfirstlane_b32 s57, v7
; SI-NEXT: v_readfirstlane_b32 s56, v6
; SI-NEXT: v_readfirstlane_b32 s55, v5
; SI-NEXT: v_readfirstlane_b32 s54, v4
; SI-NEXT: v_readfirstlane_b32 s53, v3
; SI-NEXT: v_readfirstlane_b32 s52, v2
; SI-NEXT: v_readfirstlane_b32 s51, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s50, v0
; SI-NEXT: s_cbranch_scc0 .LBB27_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB27_3
; SI-NEXT: .LBB27_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB27_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB27_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; SI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; SI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; SI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; SI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; SI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; SI-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; SI-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; SI-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; SI-NEXT: s_branch .LBB27_6
; SI-NEXT: .LBB27_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB27_6: ; %end
; SI-NEXT: v_readlane_b32 s55, v32, 11
; SI-NEXT: v_readlane_b32 s54, v32, 10
; SI-NEXT: v_readlane_b32 s53, v32, 9
; SI-NEXT: v_readlane_b32 s52, v32, 8
; SI-NEXT: v_readlane_b32 s51, v32, 7
; SI-NEXT: v_readlane_b32 s50, v32, 6
; SI-NEXT: v_readlane_b32 s49, v32, 5
; SI-NEXT: v_readlane_b32 s48, v32, 4
; SI-NEXT: v_readlane_b32 s39, v32, 3
; SI-NEXT: v_readlane_b32 s38, v32, 2
; SI-NEXT: v_readlane_b32 s37, v32, 1
; SI-NEXT: v_readlane_b32 s36, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v24f32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s36, 0
; VI-NEXT: v_writelane_b32 v32, s37, 1
; VI-NEXT: v_writelane_b32 v32, s38, 2
; VI-NEXT: v_writelane_b32 v32, s39, 3
; VI-NEXT: v_writelane_b32 v32, s48, 4
; VI-NEXT: v_writelane_b32 v32, s49, 5
; VI-NEXT: v_writelane_b32 v32, s50, 6
; VI-NEXT: v_writelane_b32 v32, s51, 7
; VI-NEXT: v_writelane_b32 v32, s52, 8
; VI-NEXT: v_writelane_b32 v32, s53, 9
; VI-NEXT: v_writelane_b32 v32, s54, 10
; VI-NEXT: v_writelane_b32 v32, s55, 11
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_mov_b32 s49, s29
; VI-NEXT: s_mov_b32 s48, s28
; VI-NEXT: s_mov_b32 s47, s27
; VI-NEXT: s_mov_b32 s46, s26
; VI-NEXT: s_mov_b32 s45, s25
; VI-NEXT: s_mov_b32 s44, s24
; VI-NEXT: s_mov_b32 s43, s23
; VI-NEXT: s_mov_b32 s42, s22
; VI-NEXT: s_mov_b32 s41, s21
; VI-NEXT: s_mov_b32 s40, s20
; VI-NEXT: s_mov_b32 s39, s19
; VI-NEXT: s_mov_b32 s38, s18
; VI-NEXT: s_mov_b32 s37, s17
; VI-NEXT: s_mov_b32 s36, s16
; VI-NEXT: v_readfirstlane_b32 s59, v9
; VI-NEXT: v_readfirstlane_b32 s58, v8
; VI-NEXT: v_readfirstlane_b32 s57, v7
; VI-NEXT: v_readfirstlane_b32 s56, v6
; VI-NEXT: v_readfirstlane_b32 s55, v5
; VI-NEXT: v_readfirstlane_b32 s54, v4
; VI-NEXT: v_readfirstlane_b32 s53, v3
; VI-NEXT: v_readfirstlane_b32 s52, v2
; VI-NEXT: v_readfirstlane_b32 s51, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s50, v0
; VI-NEXT: s_cbranch_scc0 .LBB27_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB27_3
; VI-NEXT: .LBB27_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB27_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB27_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; VI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; VI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; VI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; VI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; VI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; VI-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; VI-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; VI-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; VI-NEXT: s_branch .LBB27_6
; VI-NEXT: .LBB27_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB27_6: ; %end
; VI-NEXT: v_readlane_b32 s55, v32, 11
; VI-NEXT: v_readlane_b32 s54, v32, 10
; VI-NEXT: v_readlane_b32 s53, v32, 9
; VI-NEXT: v_readlane_b32 s52, v32, 8
; VI-NEXT: v_readlane_b32 s51, v32, 7
; VI-NEXT: v_readlane_b32 s50, v32, 6
; VI-NEXT: v_readlane_b32 s49, v32, 5
; VI-NEXT: v_readlane_b32 s48, v32, 4
; VI-NEXT: v_readlane_b32 s39, v32, 3
; VI-NEXT: v_readlane_b32 s38, v32, 2
; VI-NEXT: v_readlane_b32 s37, v32, 1
; VI-NEXT: v_readlane_b32 s36, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v24f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_mov_b32 s49, s29
; GFX9-NEXT: s_mov_b32 s48, s28
; GFX9-NEXT: s_mov_b32 s47, s27
; GFX9-NEXT: s_mov_b32 s46, s26
; GFX9-NEXT: s_mov_b32 s45, s25
; GFX9-NEXT: s_mov_b32 s44, s24
; GFX9-NEXT: s_mov_b32 s43, s23
; GFX9-NEXT: s_mov_b32 s42, s22
; GFX9-NEXT: s_mov_b32 s41, s21
; GFX9-NEXT: s_mov_b32 s40, s20
; GFX9-NEXT: s_mov_b32 s39, s19
; GFX9-NEXT: s_mov_b32 s38, s18
; GFX9-NEXT: s_mov_b32 s37, s17
; GFX9-NEXT: s_mov_b32 s36, s16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s55, v5
; GFX9-NEXT: v_readfirstlane_b32 s54, v4
; GFX9-NEXT: v_readfirstlane_b32 s53, v3
; GFX9-NEXT: v_readfirstlane_b32 s52, v2
; GFX9-NEXT: v_readfirstlane_b32 s51, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s50, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB27_3
; GFX9-NEXT: .LBB27_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB27_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB27_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; GFX9-NEXT: s_branch .LBB27_6
; GFX9-NEXT: .LBB27_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB27_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12f64_to_v24f32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: v_writelane_b32 v32, s39, 3
; GFX11-NEXT: v_writelane_b32 v32, s48, 4
; GFX11-NEXT: v_writelane_b32 v32, s49, 5
; GFX11-NEXT: v_writelane_b32 v32, s50, 6
; GFX11-NEXT: v_writelane_b32 v32, s51, 7
; GFX11-NEXT: v_writelane_b32 v32, s52, 8
; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_writelane_b32 v32, s54, 10
; GFX11-NEXT: v_writelane_b32 v32, s55, 11
; GFX11-NEXT: s_mov_b32 s36, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
; GFX11-NEXT: v_readfirstlane_b32 s59, v5
; GFX11-NEXT: v_readfirstlane_b32 s58, v4
; GFX11-NEXT: v_readfirstlane_b32 s57, v3
; GFX11-NEXT: v_readfirstlane_b32 s56, v2
; GFX11-NEXT: v_readfirstlane_b32 s55, v1
; GFX11-NEXT: v_readfirstlane_b32 s54, v0
; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_mov_b32 s52, s28
; GFX11-NEXT: s_mov_b32 s51, s27
; GFX11-NEXT: s_mov_b32 s50, s26
; GFX11-NEXT: s_mov_b32 s49, s25
; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
; GFX11-NEXT: s_mov_b32 s40, s16
; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB27_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: .LBB27_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB27_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; GFX11-NEXT: s_branch .LBB27_5
; GFX11-NEXT: .LBB27_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v1, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v3, s39
; GFX11-NEXT: v_dual_mov_b32 v4, s40 :: v_dual_mov_b32 v5, s41
; GFX11-NEXT: v_dual_mov_b32 v6, s42 :: v_dual_mov_b32 v7, s43
; GFX11-NEXT: v_dual_mov_b32 v8, s44 :: v_dual_mov_b32 v9, s45
; GFX11-NEXT: v_dual_mov_b32 v10, s46 :: v_dual_mov_b32 v11, s47
; GFX11-NEXT: v_dual_mov_b32 v12, s48 :: v_dual_mov_b32 v13, s49
; GFX11-NEXT: v_dual_mov_b32 v14, s50 :: v_dual_mov_b32 v15, s51
; GFX11-NEXT: v_dual_mov_b32 v16, s52 :: v_dual_mov_b32 v17, s53
; GFX11-NEXT: v_dual_mov_b32 v18, s54 :: v_dual_mov_b32 v19, s55
; GFX11-NEXT: v_dual_mov_b32 v20, s56 :: v_dual_mov_b32 v21, s57
; GFX11-NEXT: v_dual_mov_b32 v22, s58 :: v_dual_mov_b32 v23, s59
; GFX11-NEXT: v_dual_mov_b32 v24, s60 :: v_dual_mov_b32 v25, s61
; GFX11-NEXT: v_dual_mov_b32 v26, s62 :: v_dual_mov_b32 v27, s63
; GFX11-NEXT: v_dual_mov_b32 v28, s64 :: v_dual_mov_b32 v29, s65
; GFX11-NEXT: v_dual_mov_b32 v30, s66 :: v_dual_mov_b32 v31, s67
; GFX11-NEXT: .LBB27_5: ; %end
; GFX11-NEXT: v_readlane_b32 s55, v32, 11
; GFX11-NEXT: v_readlane_b32 s54, v32, 10
; GFX11-NEXT: v_readlane_b32 s53, v32, 9
; GFX11-NEXT: v_readlane_b32 s52, v32, 8
; GFX11-NEXT: v_readlane_b32 s51, v32, 7
; GFX11-NEXT: v_readlane_b32 s50, v32, 6
; GFX11-NEXT: v_readlane_b32 s49, v32, 5
; GFX11-NEXT: v_readlane_b32 s48, v32, 4
; GFX11-NEXT: v_readlane_b32 s39, v32, 3
; GFX11-NEXT: v_readlane_b32 s38, v32, 2
; GFX11-NEXT: v_readlane_b32 s37, v32, 1
; GFX11-NEXT: v_readlane_b32 s36, v32, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v32, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define <48 x i16> @bitcast_v24f32_to_v48i16(<24 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB28_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB28_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB28_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
; SI-NEXT: v_add_f32_e32 v17, 1.0, v17
; SI-NEXT: v_add_f32_e32 v16, 1.0, v16
; SI-NEXT: v_add_f32_e32 v19, 1.0, v19
; SI-NEXT: v_add_f32_e32 v18, 1.0, v18
; SI-NEXT: v_add_f32_e32 v21, 1.0, v21
; SI-NEXT: v_add_f32_e32 v20, 1.0, v20
; SI-NEXT: v_add_f32_e32 v23, 1.0, v23
; SI-NEXT: v_add_f32_e32 v22, 1.0, v22
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB28_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v38
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v33
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: v_or_b32_e32 v1, v1, v49
; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v33
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v48i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB28_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB28_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB28_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v23, 1.0, v23
; VI-NEXT: v_add_f32_e32 v22, 1.0, v22
; VI-NEXT: v_add_f32_e32 v21, 1.0, v21
; VI-NEXT: v_add_f32_e32 v20, 1.0, v20
; VI-NEXT: v_add_f32_e32 v19, 1.0, v19
; VI-NEXT: v_add_f32_e32 v18, 1.0, v18
; VI-NEXT: v_add_f32_e32 v17, 1.0, v17
; VI-NEXT: v_add_f32_e32 v16, 1.0, v16
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB28_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v48i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB28_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB28_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB28_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v23, 1.0, v23
; GFX9-NEXT: v_add_f32_e32 v22, 1.0, v22
; GFX9-NEXT: v_add_f32_e32 v21, 1.0, v21
; GFX9-NEXT: v_add_f32_e32 v20, 1.0, v20
; GFX9-NEXT: v_add_f32_e32 v19, 1.0, v19
; GFX9-NEXT: v_add_f32_e32 v18, 1.0, v18
; GFX9-NEXT: v_add_f32_e32 v17, 1.0, v17
; GFX9-NEXT: v_add_f32_e32 v16, 1.0, v16
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB28_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v24f32_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB28_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-TRUE16-NEXT: .LBB28_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24f32_to_v48i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB28_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB28_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB28_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-FAKE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-FAKE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-FAKE16-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-FAKE16-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-FAKE16-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB28_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define inreg <48 x i16> @bitcast_v24f32_to_v48i16_scalar(<24 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v48i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v40, s30, 0
; SI-NEXT: v_writelane_b32 v40, s31, 1
; SI-NEXT: v_readfirstlane_b32 s12, v10
; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_readfirstlane_b32 s4, v8
; SI-NEXT: v_readfirstlane_b32 s7, v7
; SI-NEXT: v_readfirstlane_b32 s6, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s11, v3
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_readfirstlane_b32 s13, v1
; SI-NEXT: s_cmp_lg_u32 s12, 0
; SI-NEXT: v_readfirstlane_b32 s12, v0
; SI-NEXT: s_cbranch_scc0 .LBB29_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s7, 16
; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16
; SI-NEXT: s_lshr_b32 s30, s5, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s9, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s11, 16
; SI-NEXT: s_lshr_b32 s95, s13, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s93, s27, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s91, s23, 16
; SI-NEXT: s_lshr_b32 s90, s21, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: s_lshr_b32 s88, s17, 16
; SI-NEXT: s_mov_b32 s15, s40
; SI-NEXT: s_lshr_b64 s[40:41], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB29_3
; SI-NEXT: .LBB29_2:
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $vcc_hi
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: .LBB29_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: s_cbranch_scc1 .LBB29_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f32_e64 v23, s5, 1.0
; SI-NEXT: v_add_f32_e64 v22, s4, 1.0
; SI-NEXT: v_add_f32_e64 v21, s7, 1.0
; SI-NEXT: v_add_f32_e64 v20, s6, 1.0
; SI-NEXT: v_lshr_b64 v[24:25], v[22:23], 16
; SI-NEXT: v_add_f32_e64 v19, s9, 1.0
; SI-NEXT: v_add_f32_e64 v18, s8, 1.0
; SI-NEXT: v_lshr_b64 v[25:26], v[20:21], 16
; SI-NEXT: v_add_f32_e64 v17, s11, 1.0
; SI-NEXT: v_add_f32_e64 v16, s10, 1.0
; SI-NEXT: v_lshr_b64 v[26:27], v[18:19], 16
; SI-NEXT: v_add_f32_e64 v15, s13, 1.0
; SI-NEXT: v_add_f32_e64 v14, s12, 1.0
; SI-NEXT: v_lshr_b64 v[27:28], v[16:17], 16
; SI-NEXT: v_add_f32_e64 v13, s29, 1.0
; SI-NEXT: v_add_f32_e64 v12, s28, 1.0
; SI-NEXT: v_lshr_b64 v[28:29], v[14:15], 16
; SI-NEXT: v_add_f32_e64 v11, s27, 1.0
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
; SI-NEXT: v_lshr_b64 v[29:30], v[12:13], 16
; SI-NEXT: v_add_f32_e64 v9, s25, 1.0
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
; SI-NEXT: v_lshr_b64 v[30:31], v[10:11], 16
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
; SI-NEXT: v_lshr_b64 v[31:32], v[8:9], 16
; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_lshr_b64 v[32:33], v[6:7], 16
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_lshr_b64 v[33:34], v[4:5], 16
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
; SI-NEXT: v_lshr_b64 v[34:35], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[35:36], v[0:1], 16
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: s_branch .LBB29_6
; SI-NEXT: .LBB29_5:
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v15, s13
; SI-NEXT: v_mov_b32_e32 v16, s10
; SI-NEXT: v_mov_b32_e32 v17, s11
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v20, s6
; SI-NEXT: v_mov_b32_e32 v21, s7
; SI-NEXT: v_mov_b32_e32 v22, s4
; SI-NEXT: v_mov_b32_e32 v23, s5
; SI-NEXT: v_mov_b32_e32 v55, s88
; SI-NEXT: v_mov_b32_e32 v54, s89
; SI-NEXT: v_mov_b32_e32 v53, s90
; SI-NEXT: v_mov_b32_e32 v52, s91
; SI-NEXT: v_mov_b32_e32 v51, s92
; SI-NEXT: v_mov_b32_e32 v50, s93
; SI-NEXT: v_mov_b32_e32 v49, s94
; SI-NEXT: v_mov_b32_e32 v48, s95
; SI-NEXT: v_mov_b32_e32 v39, vcc_lo
; SI-NEXT: v_mov_b32_e32 v38, vcc_hi
; SI-NEXT: v_mov_b32_e32 v37, s15
; SI-NEXT: v_mov_b32_e32 v36, s30
; SI-NEXT: v_mov_b32_e32 v24, s14
; SI-NEXT: v_mov_b32_e32 v25, s40
; SI-NEXT: v_mov_b32_e32 v26, s42
; SI-NEXT: v_mov_b32_e32 v27, s44
; SI-NEXT: v_mov_b32_e32 v28, s46
; SI-NEXT: v_mov_b32_e32 v29, s56
; SI-NEXT: v_mov_b32_e32 v30, s58
; SI-NEXT: v_mov_b32_e32 v31, s60
; SI-NEXT: v_mov_b32_e32 v32, s62
; SI-NEXT: v_mov_b32_e32 v33, s72
; SI-NEXT: v_mov_b32_e32 v34, s74
; SI-NEXT: v_mov_b32_e32 v35, s76
; SI-NEXT: .LBB29_6: ; %end
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v49
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v48
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v39
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v38
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v37
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
; SI-NEXT: v_readlane_b32 s30, v40, 0
; SI-NEXT: v_or_b32_e32 v1, v1, v35
; SI-NEXT: v_or_b32_e32 v3, v3, v34
; SI-NEXT: v_or_b32_e32 v5, v5, v33
; SI-NEXT: v_or_b32_e32 v7, v7, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_readlane_b32 s31, v40, 1
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v48i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB29_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB29_3
; VI-NEXT: .LBB29_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB29_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB29_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f32_e64 v23, s6, 1.0
; VI-NEXT: v_add_f32_e64 v22, s7, 1.0
; VI-NEXT: v_add_f32_e64 v21, s8, 1.0
; VI-NEXT: v_add_f32_e64 v20, s9, 1.0
; VI-NEXT: v_add_f32_e64 v19, s10, 1.0
; VI-NEXT: v_add_f32_e64 v18, s11, 1.0
; VI-NEXT: v_add_f32_e64 v17, s12, 1.0
; VI-NEXT: v_add_f32_e64 v16, s13, 1.0
; VI-NEXT: v_add_f32_e64 v15, s14, 1.0
; VI-NEXT: v_add_f32_e64 v14, s15, 1.0
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: s_branch .LBB29_6
; VI-NEXT: .LBB29_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: v_mov_b32_e32 v55, s79
; VI-NEXT: v_mov_b32_e32 v54, s78
; VI-NEXT: v_mov_b32_e32 v53, s77
; VI-NEXT: v_mov_b32_e32 v52, s76
; VI-NEXT: v_mov_b32_e32 v51, s75
; VI-NEXT: v_mov_b32_e32 v50, s74
; VI-NEXT: v_mov_b32_e32 v49, s73
; VI-NEXT: v_mov_b32_e32 v48, s72
; VI-NEXT: v_mov_b32_e32 v39, s63
; VI-NEXT: v_mov_b32_e32 v38, s62
; VI-NEXT: v_mov_b32_e32 v37, s61
; VI-NEXT: v_mov_b32_e32 v36, s60
; VI-NEXT: v_mov_b32_e32 v35, s59
; VI-NEXT: v_mov_b32_e32 v34, s58
; VI-NEXT: v_mov_b32_e32 v33, s57
; VI-NEXT: v_mov_b32_e32 v32, s56
; VI-NEXT: v_mov_b32_e32 v31, s47
; VI-NEXT: v_mov_b32_e32 v30, s46
; VI-NEXT: v_mov_b32_e32 v29, s45
; VI-NEXT: v_mov_b32_e32 v28, s44
; VI-NEXT: v_mov_b32_e32 v27, s43
; VI-NEXT: v_mov_b32_e32 v26, s42
; VI-NEXT: v_mov_b32_e32 v25, s41
; VI-NEXT: v_mov_b32_e32 v24, s40
; VI-NEXT: .LBB29_6: ; %end
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v48i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB29_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB29_3
; GFX9-NEXT: .LBB29_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB29_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB29_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e64 v23, s6, 1.0
; GFX9-NEXT: v_add_f32_e64 v22, s7, 1.0
; GFX9-NEXT: v_add_f32_e64 v21, s8, 1.0
; GFX9-NEXT: v_add_f32_e64 v20, s9, 1.0
; GFX9-NEXT: v_add_f32_e64 v19, s10, 1.0
; GFX9-NEXT: v_add_f32_e64 v18, s11, 1.0
; GFX9-NEXT: v_add_f32_e64 v17, s12, 1.0
; GFX9-NEXT: v_add_f32_e64 v16, s13, 1.0
; GFX9-NEXT: v_add_f32_e64 v15, s14, 1.0
; GFX9-NEXT: v_add_f32_e64 v14, s15, 1.0
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: s_branch .LBB29_6
; GFX9-NEXT: .LBB29_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: v_mov_b32_e32 v55, s79
; GFX9-NEXT: v_mov_b32_e32 v54, s78
; GFX9-NEXT: v_mov_b32_e32 v53, s77
; GFX9-NEXT: v_mov_b32_e32 v52, s76
; GFX9-NEXT: v_mov_b32_e32 v51, s75
; GFX9-NEXT: v_mov_b32_e32 v50, s74
; GFX9-NEXT: v_mov_b32_e32 v49, s73
; GFX9-NEXT: v_mov_b32_e32 v48, s72
; GFX9-NEXT: v_mov_b32_e32 v39, s63
; GFX9-NEXT: v_mov_b32_e32 v38, s62
; GFX9-NEXT: v_mov_b32_e32 v37, s61
; GFX9-NEXT: v_mov_b32_e32 v36, s60
; GFX9-NEXT: v_mov_b32_e32 v35, s59
; GFX9-NEXT: v_mov_b32_e32 v34, s58
; GFX9-NEXT: v_mov_b32_e32 v33, s57
; GFX9-NEXT: v_mov_b32_e32 v32, s56
; GFX9-NEXT: v_mov_b32_e32 v31, s47
; GFX9-NEXT: v_mov_b32_e32 v30, s46
; GFX9-NEXT: v_mov_b32_e32 v29, s45
; GFX9-NEXT: v_mov_b32_e32 v28, s44
; GFX9-NEXT: v_mov_b32_e32 v27, s43
; GFX9-NEXT: v_mov_b32_e32 v26, s42
; GFX9-NEXT: v_mov_b32_e32 v25, s41
; GFX9-NEXT: v_mov_b32_e32 v24, s40
; GFX9-NEXT: .LBB29_6: ; %end
; GFX9-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; GFX9-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; GFX9-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX9-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX9-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v55, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v1, v54, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v2, v53, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v3, v52, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v6, v49, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v7, v48, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v8, v39, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v9, v38, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v10, v37, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v11, v36, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v12, v35, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v13, v34, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v14, v33, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v15, v32, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v16, v31, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v17, v30, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v18, v29, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v19, v28, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v20, v27, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v21, v26, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v22, v25, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v24f32_to_v48i16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s12, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB29_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s6, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s7, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s8, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s9, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s26, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s25, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s24, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s23, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s56, s22, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s21, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s20, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s19, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s60, s18, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s61, s17, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s62, s16, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s63, s3, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s72, s2, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s73, s1, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-TRUE16-NEXT: s_branch .LBB29_3
; GFX11-TRUE16-NEXT: .LBB29_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr73
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr72
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr63
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr62
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr61
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr60
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr59
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr58
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr57
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr56
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr47
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr46
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr45
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr44
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr43
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr42
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr41
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr40
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr15
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr14
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr13
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr11
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr10
; GFX11-TRUE16-NEXT: .LBB29_3: ; %Flow
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB29_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, s4, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, s5, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, s6, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, s7, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, s8, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, s9, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, s29, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, s28, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, s27, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, s26, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, s25, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, s24, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, s23, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, s22, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, s21, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, s20, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, s19, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, s18, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, s17, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, s16, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, s3, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, s0, 1.0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-TRUE16-NEXT: s_branch .LBB29_6
; GFX11-TRUE16-NEXT: .LBB29_5:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s74 :: v_dual_mov_b32 v54, s73
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, s72 :: v_dual_mov_b32 v52, s63
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, s62 :: v_dual_mov_b32 v50, s61
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, s60 :: v_dual_mov_b32 v48, s59
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, s58 :: v_dual_mov_b32 v38, s57
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, s56 :: v_dual_mov_b32 v36, s47
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s46 :: v_dual_mov_b32 v34, s45
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, s44 :: v_dual_mov_b32 v32, s43
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s42 :: v_dual_mov_b32 v30, s41
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, s40 :: v_dual_mov_b32 v28, s15
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, s14 :: v_dual_mov_b32 v26, s13
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s11 :: v_dual_mov_b32 v24, s10
; GFX11-TRUE16-NEXT: .LBB29_6: ; %end
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24f32_to_v48i16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s12, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB29_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s6, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s14, s7, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s15, s8, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s40, s9, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s44, s26, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s25, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s24, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s23, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s22, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s21, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s20, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s19, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s60, s18, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s61, s17, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s62, s16, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s63, s3, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s72, s2, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s73, s1, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-FAKE16-NEXT: s_branch .LBB29_3
; GFX11-FAKE16-NEXT: .LBB29_2:
; GFX11-FAKE16-NEXT: s_mov_b32 s12, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr72
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr62
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr61
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr58
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr57
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr46
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr45
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr40
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr15
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr14
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr13
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr11
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr10
; GFX11-FAKE16-NEXT: .LBB29_3: ; %Flow
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-FAKE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB29_5
; GFX11-FAKE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, s4, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, s5, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, s6, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, s7, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, s8, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, s9, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, s29, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, s28, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, s27, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, s26, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, s25, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, s24, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, s23, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, s22, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, s21, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, s20, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, s19, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, s18, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, s17, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, s16, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, s3, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, s2, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, s1, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, s0, 1.0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; GFX11-FAKE16-NEXT: s_branch .LBB29_6
; GFX11-FAKE16-NEXT: .LBB29_5:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v2, s1
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v0, s3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v7, s17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v5, s19
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v13, s21
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s22 :: v_dual_mov_b32 v11, s23
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s24 :: v_dual_mov_b32 v9, s25
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s26 :: v_dual_mov_b32 v17, s27
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v15, s29
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v23, s8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, s7 :: v_dual_mov_b32 v21, s6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, s5 :: v_dual_mov_b32 v19, s4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, s74 :: v_dual_mov_b32 v54, s73
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, s72 :: v_dual_mov_b32 v52, s63
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, s62 :: v_dual_mov_b32 v50, s61
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, s60 :: v_dual_mov_b32 v48, s59
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, s58 :: v_dual_mov_b32 v38, s57
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, s56 :: v_dual_mov_b32 v36, s47
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, s46 :: v_dual_mov_b32 v34, s45
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, s44 :: v_dual_mov_b32 v32, s43
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, s42 :: v_dual_mov_b32 v30, s41
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, s40 :: v_dual_mov_b32 v28, s15
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, s14 :: v_dual_mov_b32 v26, s13
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, s11 :: v_dual_mov_b32 v24, s10
; GFX11-FAKE16-NEXT: .LBB29_6: ; %end
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v53, 16, v64
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v52, 16, v65
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v51, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v48, 16, v52
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v39, 16, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v39, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v38, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v35, 16, v39
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v34, 16, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v30, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v29, 16, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v25, 16, v29
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v24, 16, v30
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define <24 x float> @bitcast_v48i16_to_v24f32(<48 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v24f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_or_b32_e32 v1, v1, v59
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v58
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v57
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_or_b32_e32 v7, v7, v56
; SI-NEXT: v_or_b32_e32 v8, v8, v63
; SI-NEXT: v_or_b32_e32 v9, v9, v62
; SI-NEXT: v_or_b32_e32 v10, v10, v61
; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB30_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB30_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v57, v5
; SI-NEXT: v_or_b32_e32 v6, v32, v6
; SI-NEXT: v_or_b32_e32 v7, v56, v7
; SI-NEXT: v_or_b32_e32 v8, v63, v8
; SI-NEXT: v_or_b32_e32 v9, v62, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: .LBB30_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v24f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB30_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB30_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB30_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 3
; VI-NEXT: v_add_u16_e32 v0, 3, v47
; VI-NEXT: v_add_u16_sdwa v1, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 3, v46
; VI-NEXT: v_add_u16_sdwa v2, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v45
; VI-NEXT: v_add_u16_sdwa v3, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v44
; VI-NEXT: v_add_u16_sdwa v4, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v43
; VI-NEXT: v_add_u16_sdwa v5, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v42
; VI-NEXT: v_add_u16_sdwa v6, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v41
; VI-NEXT: v_add_u16_sdwa v7, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: v_add_u16_e32 v7, 3, v40
; VI-NEXT: v_add_u16_sdwa v8, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v55
; VI-NEXT: v_add_u16_sdwa v9, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_add_u16_e32 v9, 3, v54
; VI-NEXT: v_add_u16_sdwa v10, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u16_e32 v10, 3, v53
; VI-NEXT: v_add_u16_sdwa v11, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_add_u16_e32 v11, 3, v52
; VI-NEXT: v_add_u16_sdwa v12, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u16_e32 v12, 3, v51
; VI-NEXT: v_add_u16_sdwa v13, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_add_u16_e32 v13, 3, v50
; VI-NEXT: v_add_u16_sdwa v14, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_add_u16_e32 v14, 3, v49
; VI-NEXT: v_add_u16_sdwa v15, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_add_u16_e32 v15, 3, v48
; VI-NEXT: v_add_u16_sdwa v16, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: v_add_u16_e32 v16, 3, v39
; VI-NEXT: v_add_u16_sdwa v17, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: v_add_u16_e32 v17, 3, v38
; VI-NEXT: v_add_u16_sdwa v18, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: v_add_u16_e32 v18, 3, v37
; VI-NEXT: v_add_u16_sdwa v19, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: v_add_u16_e32 v19, 3, v36
; VI-NEXT: v_add_u16_sdwa v20, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: v_add_u16_e32 v20, 3, v35
; VI-NEXT: v_add_u16_sdwa v21, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: v_add_u16_e32 v21, 3, v34
; VI-NEXT: v_add_u16_sdwa v22, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: v_add_u16_e32 v22, 3, v33
; VI-NEXT: v_add_u16_sdwa v24, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v22, v22, v24
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB30_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v24f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB30_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB30_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB30_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB30_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v24f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB30_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB30_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v24f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB30_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: .LBB30_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define inreg <24 x float> @bitcast_v48i16_to_v24f32_scalar(<48 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v24f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v24, s36, 0
; SI-NEXT: v_writelane_b32 v24, s37, 1
; SI-NEXT: v_writelane_b32 v24, s38, 2
; SI-NEXT: v_writelane_b32 v24, s39, 3
; SI-NEXT: v_writelane_b32 v24, s48, 4
; SI-NEXT: v_writelane_b32 v24, s49, 5
; SI-NEXT: v_writelane_b32 v24, s50, 6
; SI-NEXT: v_writelane_b32 v24, s51, 7
; SI-NEXT: v_writelane_b32 v24, s52, 8
; SI-NEXT: v_writelane_b32 v24, s53, 9
; SI-NEXT: v_writelane_b32 v24, s54, 10
; SI-NEXT: v_writelane_b32 v24, s55, 11
; SI-NEXT: v_writelane_b32 v24, s64, 12
; SI-NEXT: v_writelane_b32 v24, s65, 13
; SI-NEXT: v_writelane_b32 v24, s66, 14
; SI-NEXT: v_writelane_b32 v24, s67, 15
; SI-NEXT: v_writelane_b32 v24, s30, 16
; SI-NEXT: v_writelane_b32 v24, s31, 17
; SI-NEXT: v_readfirstlane_b32 s7, v9
; SI-NEXT: v_readfirstlane_b32 s9, v8
; SI-NEXT: v_readfirstlane_b32 s11, v7
; SI-NEXT: v_readfirstlane_b32 s13, v6
; SI-NEXT: v_readfirstlane_b32 s15, v5
; SI-NEXT: v_readfirstlane_b32 s74, v4
; SI-NEXT: v_readfirstlane_b32 s77, v3
; SI-NEXT: v_readfirstlane_b32 s88, v2
; SI-NEXT: v_readfirstlane_b32 s91, v1
; SI-NEXT: v_readfirstlane_b32 s94, v0
; SI-NEXT: s_lshr_b32 s72, s29, 16
; SI-NEXT: s_lshr_b32 s75, s28, 16
; SI-NEXT: s_lshr_b32 s78, s27, 16
; SI-NEXT: s_lshr_b32 s89, s26, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s60, s21, 16
; SI-NEXT: s_lshr_b32 s61, s20, 16
; SI-NEXT: s_lshr_b32 s62, s19, 16
; SI-NEXT: s_lshr_b32 s63, s18, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_lshr_b32 s31, s16, 16
; SI-NEXT: s_lshr_b32 s6, s7, 16
; SI-NEXT: s_lshr_b32 s8, s9, 16
; SI-NEXT: s_lshr_b32 s10, s11, 16
; SI-NEXT: s_lshr_b32 s12, s13, 16
; SI-NEXT: s_lshr_b32 s14, s15, 16
; SI-NEXT: s_lshr_b32 s73, s74, 16
; SI-NEXT: s_lshr_b32 s76, s77, 16
; SI-NEXT: s_lshr_b32 s79, s88, 16
; SI-NEXT: s_lshr_b32 s90, s91, 16
; SI-NEXT: s_lshr_b32 s93, s94, 16
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_cbranch_scc0 .LBB31_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s36, s4, s5
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s37, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s91, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s77, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s15, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s13, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s11, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s9, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB31_3
; SI-NEXT: .LBB31_2:
; SI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v25, s77, 0
; SI-NEXT: v_writelane_b32 v25, s74, 1
; SI-NEXT: v_writelane_b32 v25, s15, 2
; SI-NEXT: v_writelane_b32 v25, s13, 3
; SI-NEXT: s_mov_b32 s13, s11
; SI-NEXT: s_mov_b32 s11, s9
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_mov_b32 s7, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, s95
; SI-NEXT: s_mov_b32 s95, s93
; SI-NEXT: s_mov_b32 s93, s92
; SI-NEXT: s_mov_b32 s92, s90
; SI-NEXT: s_mov_b32 s90, s89
; SI-NEXT: s_mov_b32 s89, s79
; SI-NEXT: s_mov_b32 s79, s78
; SI-NEXT: s_mov_b32 s78, s76
; SI-NEXT: s_mov_b32 s76, s75
; SI-NEXT: s_mov_b32 s75, s73
; SI-NEXT: s_mov_b32 s73, s72
; SI-NEXT: s_mov_b32 s72, s14
; SI-NEXT: s_mov_b32 s14, s12
; SI-NEXT: s_mov_b32 s12, s10
; SI-NEXT: s_mov_b32 s10, s8
; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s6, s60
; SI-NEXT: s_mov_b32 s77, s88
; SI-NEXT: s_mov_b32 s88, s61
; SI-NEXT: s_mov_b32 s74, s91
; SI-NEXT: s_mov_b32 s91, s62
; SI-NEXT: s_mov_b32 s15, s63
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_mov_b32 s63, s15
; SI-NEXT: s_mov_b32 s62, s91
; SI-NEXT: s_mov_b32 s91, s74
; SI-NEXT: s_mov_b32 s61, s88
; SI-NEXT: s_mov_b32 s88, s77
; SI-NEXT: s_mov_b32 s60, s6
; SI-NEXT: s_mov_b32 s6, s8
; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s10, s12
; SI-NEXT: s_mov_b32 s12, s14
; SI-NEXT: s_mov_b32 s14, s72
; SI-NEXT: s_mov_b32 s72, s73
; SI-NEXT: s_mov_b32 s73, s75
; SI-NEXT: s_mov_b32 s75, s76
; SI-NEXT: s_mov_b32 s76, s78
; SI-NEXT: s_mov_b32 s78, s79
; SI-NEXT: s_mov_b32 s79, s89
; SI-NEXT: s_mov_b32 s89, s90
; SI-NEXT: s_mov_b32 s90, s92
; SI-NEXT: s_mov_b32 s92, s93
; SI-NEXT: s_mov_b32 s93, s95
; SI-NEXT: s_mov_b32 s95, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, s7
; SI-NEXT: s_mov_b32 s7, s9
; SI-NEXT: s_mov_b32 s9, s11
; SI-NEXT: s_mov_b32 s11, s13
; SI-NEXT: v_readlane_b32 s13, v25, 3
; SI-NEXT: v_readlane_b32 s15, v25, 2
; SI-NEXT: v_readlane_b32 s74, v25, 1
; SI-NEXT: v_readlane_b32 s77, v25, 0
; SI-NEXT: .LBB31_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB31_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s36, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s37, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s38, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s39, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s40, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s41, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s42, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s43, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s44, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s45, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s46, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s47, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s48, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s94, s94, 3
; SI-NEXT: s_add_i32 s49, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s50, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s91, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s51, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s88, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s52, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s77, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s74, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s54, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s15, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s13, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s56, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s11, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s9, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s58, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s7, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
; SI-NEXT: .LBB31_5: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 16
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_readlane_b32 s31, v24, 17
; SI-NEXT: v_readlane_b32 s67, v24, 15
; SI-NEXT: v_readlane_b32 s66, v24, 14
; SI-NEXT: v_readlane_b32 s65, v24, 13
; SI-NEXT: v_readlane_b32 s64, v24, 12
; SI-NEXT: v_readlane_b32 s55, v24, 11
; SI-NEXT: v_readlane_b32 s54, v24, 10
; SI-NEXT: v_readlane_b32 s53, v24, 9
; SI-NEXT: v_readlane_b32 s52, v24, 8
; SI-NEXT: v_readlane_b32 s51, v24, 7
; SI-NEXT: v_readlane_b32 s50, v24, 6
; SI-NEXT: v_readlane_b32 s49, v24, 5
; SI-NEXT: v_readlane_b32 s48, v24, 4
; SI-NEXT: v_readlane_b32 s39, v24, 3
; SI-NEXT: v_readlane_b32 s38, v24, 2
; SI-NEXT: v_readlane_b32 s37, v24, 1
; SI-NEXT: v_readlane_b32 s36, v24, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v24f32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v24, s34, 0
; VI-NEXT: v_writelane_b32 v24, s35, 1
; VI-NEXT: v_writelane_b32 v24, s36, 2
; VI-NEXT: v_writelane_b32 v24, s37, 3
; VI-NEXT: v_writelane_b32 v24, s38, 4
; VI-NEXT: v_writelane_b32 v24, s39, 5
; VI-NEXT: v_writelane_b32 v24, s48, 6
; VI-NEXT: v_writelane_b32 v24, s49, 7
; VI-NEXT: v_writelane_b32 v24, s50, 8
; VI-NEXT: v_writelane_b32 v24, s51, 9
; VI-NEXT: v_writelane_b32 v24, s52, 10
; VI-NEXT: v_writelane_b32 v24, s53, 11
; VI-NEXT: v_writelane_b32 v24, s54, 12
; VI-NEXT: v_writelane_b32 v24, s55, 13
; VI-NEXT: v_writelane_b32 v24, s64, 14
; VI-NEXT: v_writelane_b32 v24, s65, 15
; VI-NEXT: v_writelane_b32 v24, s66, 16
; VI-NEXT: v_writelane_b32 v24, s67, 17
; VI-NEXT: v_writelane_b32 v24, s30, 18
; VI-NEXT: v_writelane_b32 v24, s31, 19
; VI-NEXT: v_readfirstlane_b32 s7, v9
; VI-NEXT: v_readfirstlane_b32 s9, v8
; VI-NEXT: v_readfirstlane_b32 s11, v7
; VI-NEXT: v_readfirstlane_b32 s13, v6
; VI-NEXT: v_readfirstlane_b32 s15, v5
; VI-NEXT: v_readfirstlane_b32 s74, v4
; VI-NEXT: v_readfirstlane_b32 s77, v3
; VI-NEXT: v_readfirstlane_b32 s88, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s60, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s75, s28, 16
; VI-NEXT: s_lshr_b32 s78, s27, 16
; VI-NEXT: s_lshr_b32 s89, s26, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s25, 16
; VI-NEXT: s_lshr_b32 s61, s24, 16
; VI-NEXT: s_lshr_b32 s62, s23, 16
; VI-NEXT: s_lshr_b32 s63, s22, 16
; VI-NEXT: s_lshr_b32 s30, s21, 16
; VI-NEXT: s_lshr_b32 s31, s20, 16
; VI-NEXT: s_lshr_b32 s34, s19, 16
; VI-NEXT: s_lshr_b32 s35, s18, 16
; VI-NEXT: s_lshr_b32 s64, s17, 16
; VI-NEXT: s_lshr_b32 s65, s16, 16
; VI-NEXT: s_lshr_b32 s6, s7, 16
; VI-NEXT: s_lshr_b32 s8, s9, 16
; VI-NEXT: s_lshr_b32 s10, s11, 16
; VI-NEXT: s_lshr_b32 s12, s13, 16
; VI-NEXT: s_lshr_b32 s14, s15, 16
; VI-NEXT: s_lshr_b32 s73, s74, 16
; VI-NEXT: s_lshr_b32 s76, s77, 16
; VI-NEXT: s_lshr_b32 s79, s88, 16
; VI-NEXT: s_lshr_b32 s90, s91, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s60, 16
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: s_cbranch_scc0 .LBB31_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s17
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s60
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s88
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s15
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s13
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s9
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB31_3
; VI-NEXT: .LBB31_2:
; VI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: v_writelane_b32 v25, s77, 0
; VI-NEXT: v_writelane_b32 v25, s74, 1
; VI-NEXT: v_writelane_b32 v25, s15, 2
; VI-NEXT: v_writelane_b32 v25, s13, 3
; VI-NEXT: v_writelane_b32 v25, s11, 4
; VI-NEXT: v_writelane_b32 v25, s9, 5
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_mov_b32 s7, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, s90
; VI-NEXT: s_mov_b32 s90, s89
; VI-NEXT: s_mov_b32 s89, s79
; VI-NEXT: s_mov_b32 s79, s78
; VI-NEXT: s_mov_b32 s78, s76
; VI-NEXT: s_mov_b32 s76, s75
; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s12
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s8
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s6, s60
; VI-NEXT: s_mov_b32 s77, s61
; VI-NEXT: s_mov_b32 s74, s88
; VI-NEXT: s_mov_b32 s88, s62
; VI-NEXT: s_mov_b32 s11, s63
; VI-NEXT: s_mov_b32 s15, s91
; VI-NEXT: s_mov_b32 s91, s64
; VI-NEXT: s_mov_b32 s13, s65
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_mov_b32 s65, s13
; VI-NEXT: s_mov_b32 s64, s91
; VI-NEXT: s_mov_b32 s91, s15
; VI-NEXT: s_mov_b32 s63, s11
; VI-NEXT: s_mov_b32 s62, s88
; VI-NEXT: s_mov_b32 s88, s74
; VI-NEXT: s_mov_b32 s61, s77
; VI-NEXT: s_mov_b32 s60, s6
; VI-NEXT: s_mov_b32 s6, s8
; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s12, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s73
; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s76
; VI-NEXT: s_mov_b32 s76, s78
; VI-NEXT: s_mov_b32 s78, s79
; VI-NEXT: s_mov_b32 s79, s89
; VI-NEXT: s_mov_b32 s89, s90
; VI-NEXT: s_mov_b32 s90, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, s7
; VI-NEXT: s_mov_b32 s7, s9
; VI-NEXT: v_readlane_b32 s9, v25, 5
; VI-NEXT: v_readlane_b32 s11, v25, 4
; VI-NEXT: v_readlane_b32 s13, v25, 3
; VI-NEXT: v_readlane_b32 s15, v25, 2
; VI-NEXT: v_readlane_b32 s74, v25, 1
; VI-NEXT: v_readlane_b32 s77, v25, 0
; VI-NEXT: .LBB31_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB31_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s17, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s22, 0xffff
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s42, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s23, 0xffff
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s43, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s24, 0xffff
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s44, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s25, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s45, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s26, 0xffff
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s46, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s27, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s47, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s28, 0xffff
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s48, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s29, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s49, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s60, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s50, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s91, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s51, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s88, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s52, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s77, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s74, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s54, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s15, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s13, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s11, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s9, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s58, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s7, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: .LBB31_5: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_readlane_b32 s31, v24, 19
; VI-NEXT: v_readlane_b32 s67, v24, 17
; VI-NEXT: v_readlane_b32 s66, v24, 16
; VI-NEXT: v_readlane_b32 s65, v24, 15
; VI-NEXT: v_readlane_b32 s64, v24, 14
; VI-NEXT: v_readlane_b32 s55, v24, 13
; VI-NEXT: v_readlane_b32 s54, v24, 12
; VI-NEXT: v_readlane_b32 s53, v24, 11
; VI-NEXT: v_readlane_b32 s52, v24, 10
; VI-NEXT: v_readlane_b32 s51, v24, 9
; VI-NEXT: v_readlane_b32 s50, v24, 8
; VI-NEXT: v_readlane_b32 s49, v24, 7
; VI-NEXT: v_readlane_b32 s48, v24, 6
; VI-NEXT: v_readlane_b32 s39, v24, 5
; VI-NEXT: v_readlane_b32 s38, v24, 4
; VI-NEXT: v_readlane_b32 s37, v24, 3
; VI-NEXT: v_readlane_b32 s36, v24, 2
; VI-NEXT: v_readlane_b32 s35, v24, 1
; VI-NEXT: v_readlane_b32 s34, v24, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v24f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB31_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB31_3
; GFX9-NEXT: .LBB31_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB31_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB31_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v0, s36, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s37, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, s38, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, s39, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, s40, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, s41, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, s42, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, s43, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, s44, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, s45, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, s46, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, s47, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, s48, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, s49, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, s50, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB31_6
; GFX9-NEXT: .LBB31_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB31_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48i16_to_v24f32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB31_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB31_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB31_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB31_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define <48 x half> @bitcast_v24f32_to_v48f16(<24 x float> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v48f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB32_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB32_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB32_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
; SI-NEXT: v_add_f32_e32 v17, 1.0, v17
; SI-NEXT: v_add_f32_e32 v16, 1.0, v16
; SI-NEXT: v_add_f32_e32 v19, 1.0, v19
; SI-NEXT: v_add_f32_e32 v18, 1.0, v18
; SI-NEXT: v_add_f32_e32 v21, 1.0, v21
; SI-NEXT: v_add_f32_e32 v20, 1.0, v20
; SI-NEXT: v_add_f32_e32 v23, 1.0, v23
; SI-NEXT: v_add_f32_e32 v22, 1.0, v22
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB32_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v38
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v33
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: v_or_b32_e32 v1, v1, v49
; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v33
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v48f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB32_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB32_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB32_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_f32_e32 v23, 1.0, v23
; VI-NEXT: v_add_f32_e32 v22, 1.0, v22
; VI-NEXT: v_add_f32_e32 v21, 1.0, v21
; VI-NEXT: v_add_f32_e32 v20, 1.0, v20
; VI-NEXT: v_add_f32_e32 v19, 1.0, v19
; VI-NEXT: v_add_f32_e32 v18, 1.0, v18
; VI-NEXT: v_add_f32_e32 v17, 1.0, v17
; VI-NEXT: v_add_f32_e32 v16, 1.0, v16
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB32_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v48f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB32_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB32_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB32_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_f32_e32 v23, 1.0, v23
; GFX9-NEXT: v_add_f32_e32 v22, 1.0, v22
; GFX9-NEXT: v_add_f32_e32 v21, 1.0, v21
; GFX9-NEXT: v_add_f32_e32 v20, 1.0, v20
; GFX9-NEXT: v_add_f32_e32 v19, 1.0, v19
; GFX9-NEXT: v_add_f32_e32 v18, 1.0, v18
; GFX9-NEXT: v_add_f32_e32 v17, 1.0, v17
; GFX9-NEXT: v_add_f32_e32 v16, 1.0, v16
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB32_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v24f32_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB32_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-TRUE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-TRUE16-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-TRUE16-NEXT: .LBB32_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24f32_to_v48f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB32_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB32_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB32_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_dual_add_f32 v23, 1.0, v23 :: v_dual_add_f32 v22, 1.0, v22
; GFX11-FAKE16-NEXT: v_dual_add_f32 v21, 1.0, v21 :: v_dual_add_f32 v20, 1.0, v20
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 1.0, v19 :: v_dual_add_f32 v18, 1.0, v18
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 1.0, v17 :: v_dual_add_f32 v16, 1.0, v16
; GFX11-FAKE16-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
; GFX11-FAKE16-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
; GFX11-FAKE16-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
; GFX11-FAKE16-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
; GFX11-FAKE16-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
; GFX11-FAKE16-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB32_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define inreg <48 x half> @bitcast_v24f32_to_v48f16_scalar(<24 x float> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v24f32_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v40, s30, 0
; SI-NEXT: v_writelane_b32 v40, s31, 1
; SI-NEXT: v_readfirstlane_b32 s12, v10
; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_readfirstlane_b32 s4, v8
; SI-NEXT: v_readfirstlane_b32 s7, v7
; SI-NEXT: v_readfirstlane_b32 s6, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s11, v3
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_readfirstlane_b32 s13, v1
; SI-NEXT: s_cmp_lg_u32 s12, 0
; SI-NEXT: v_readfirstlane_b32 s12, v0
; SI-NEXT: s_cbranch_scc0 .LBB33_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s7, 16
; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16
; SI-NEXT: s_lshr_b32 s30, s5, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s9, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s11, 16
; SI-NEXT: s_lshr_b32 s95, s13, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s93, s27, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s91, s23, 16
; SI-NEXT: s_lshr_b32 s90, s21, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: s_lshr_b32 s88, s17, 16
; SI-NEXT: s_mov_b32 s15, s40
; SI-NEXT: s_lshr_b64 s[40:41], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB33_3
; SI-NEXT: .LBB33_2:
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $vcc_hi
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: .LBB33_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: s_cbranch_scc1 .LBB33_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f32_e64 v23, s5, 1.0
; SI-NEXT: v_add_f32_e64 v22, s4, 1.0
; SI-NEXT: v_add_f32_e64 v21, s7, 1.0
; SI-NEXT: v_add_f32_e64 v20, s6, 1.0
; SI-NEXT: v_lshr_b64 v[24:25], v[22:23], 16
; SI-NEXT: v_add_f32_e64 v19, s9, 1.0
; SI-NEXT: v_add_f32_e64 v18, s8, 1.0
; SI-NEXT: v_lshr_b64 v[25:26], v[20:21], 16
; SI-NEXT: v_add_f32_e64 v17, s11, 1.0
; SI-NEXT: v_add_f32_e64 v16, s10, 1.0
; SI-NEXT: v_lshr_b64 v[26:27], v[18:19], 16
; SI-NEXT: v_add_f32_e64 v15, s13, 1.0
; SI-NEXT: v_add_f32_e64 v14, s12, 1.0
; SI-NEXT: v_lshr_b64 v[27:28], v[16:17], 16
; SI-NEXT: v_add_f32_e64 v13, s29, 1.0
; SI-NEXT: v_add_f32_e64 v12, s28, 1.0
; SI-NEXT: v_lshr_b64 v[28:29], v[14:15], 16
; SI-NEXT: v_add_f32_e64 v11, s27, 1.0
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
; SI-NEXT: v_lshr_b64 v[29:30], v[12:13], 16
; SI-NEXT: v_add_f32_e64 v9, s25, 1.0
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
; SI-NEXT: v_lshr_b64 v[30:31], v[10:11], 16
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
; SI-NEXT: v_lshr_b64 v[31:32], v[8:9], 16
; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
; SI-NEXT: v_lshr_b64 v[32:33], v[6:7], 16
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
; SI-NEXT: v_lshr_b64 v[33:34], v[4:5], 16
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
; SI-NEXT: v_lshr_b64 v[34:35], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[35:36], v[0:1], 16
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: s_branch .LBB33_6
; SI-NEXT: .LBB33_5:
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v15, s13
; SI-NEXT: v_mov_b32_e32 v16, s10
; SI-NEXT: v_mov_b32_e32 v17, s11
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v20, s6
; SI-NEXT: v_mov_b32_e32 v21, s7
; SI-NEXT: v_mov_b32_e32 v22, s4
; SI-NEXT: v_mov_b32_e32 v23, s5
; SI-NEXT: v_mov_b32_e32 v55, s88
; SI-NEXT: v_mov_b32_e32 v54, s89
; SI-NEXT: v_mov_b32_e32 v53, s90
; SI-NEXT: v_mov_b32_e32 v52, s91
; SI-NEXT: v_mov_b32_e32 v51, s92
; SI-NEXT: v_mov_b32_e32 v50, s93
; SI-NEXT: v_mov_b32_e32 v49, s94
; SI-NEXT: v_mov_b32_e32 v48, s95
; SI-NEXT: v_mov_b32_e32 v39, vcc_lo
; SI-NEXT: v_mov_b32_e32 v38, vcc_hi
; SI-NEXT: v_mov_b32_e32 v37, s15
; SI-NEXT: v_mov_b32_e32 v36, s30
; SI-NEXT: v_mov_b32_e32 v24, s14
; SI-NEXT: v_mov_b32_e32 v25, s40
; SI-NEXT: v_mov_b32_e32 v26, s42
; SI-NEXT: v_mov_b32_e32 v27, s44
; SI-NEXT: v_mov_b32_e32 v28, s46
; SI-NEXT: v_mov_b32_e32 v29, s56
; SI-NEXT: v_mov_b32_e32 v30, s58
; SI-NEXT: v_mov_b32_e32 v31, s60
; SI-NEXT: v_mov_b32_e32 v32, s62
; SI-NEXT: v_mov_b32_e32 v33, s72
; SI-NEXT: v_mov_b32_e32 v34, s74
; SI-NEXT: v_mov_b32_e32 v35, s76
; SI-NEXT: .LBB33_6: ; %end
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v49
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v48
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v39
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v38
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v37
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
; SI-NEXT: v_readlane_b32 s30, v40, 0
; SI-NEXT: v_or_b32_e32 v1, v1, v35
; SI-NEXT: v_or_b32_e32 v3, v3, v34
; SI-NEXT: v_or_b32_e32 v5, v5, v33
; SI-NEXT: v_or_b32_e32 v7, v7, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_readlane_b32 s31, v40, 1
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v24f32_to_v48f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB33_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB33_3
; VI-NEXT: .LBB33_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB33_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB33_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f32_e64 v23, s6, 1.0
; VI-NEXT: v_add_f32_e64 v22, s7, 1.0
; VI-NEXT: v_add_f32_e64 v21, s8, 1.0
; VI-NEXT: v_add_f32_e64 v20, s9, 1.0
; VI-NEXT: v_add_f32_e64 v19, s10, 1.0
; VI-NEXT: v_add_f32_e64 v18, s11, 1.0
; VI-NEXT: v_add_f32_e64 v17, s12, 1.0
; VI-NEXT: v_add_f32_e64 v16, s13, 1.0
; VI-NEXT: v_add_f32_e64 v15, s14, 1.0
; VI-NEXT: v_add_f32_e64 v14, s15, 1.0
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: s_branch .LBB33_6
; VI-NEXT: .LBB33_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: v_mov_b32_e32 v55, s79
; VI-NEXT: v_mov_b32_e32 v54, s78
; VI-NEXT: v_mov_b32_e32 v53, s77
; VI-NEXT: v_mov_b32_e32 v52, s76
; VI-NEXT: v_mov_b32_e32 v51, s75
; VI-NEXT: v_mov_b32_e32 v50, s74
; VI-NEXT: v_mov_b32_e32 v49, s73
; VI-NEXT: v_mov_b32_e32 v48, s72
; VI-NEXT: v_mov_b32_e32 v39, s63
; VI-NEXT: v_mov_b32_e32 v38, s62
; VI-NEXT: v_mov_b32_e32 v37, s61
; VI-NEXT: v_mov_b32_e32 v36, s60
; VI-NEXT: v_mov_b32_e32 v35, s59
; VI-NEXT: v_mov_b32_e32 v34, s58
; VI-NEXT: v_mov_b32_e32 v33, s57
; VI-NEXT: v_mov_b32_e32 v32, s56
; VI-NEXT: v_mov_b32_e32 v31, s47
; VI-NEXT: v_mov_b32_e32 v30, s46
; VI-NEXT: v_mov_b32_e32 v29, s45
; VI-NEXT: v_mov_b32_e32 v28, s44
; VI-NEXT: v_mov_b32_e32 v27, s43
; VI-NEXT: v_mov_b32_e32 v26, s42
; VI-NEXT: v_mov_b32_e32 v25, s41
; VI-NEXT: v_mov_b32_e32 v24, s40
; VI-NEXT: .LBB33_6: ; %end
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v24f32_to_v48f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB33_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB33_3
; GFX9-NEXT: .LBB33_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB33_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB33_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f32_e64 v23, s6, 1.0
; GFX9-NEXT: v_add_f32_e64 v22, s7, 1.0
; GFX9-NEXT: v_add_f32_e64 v21, s8, 1.0
; GFX9-NEXT: v_add_f32_e64 v20, s9, 1.0
; GFX9-NEXT: v_add_f32_e64 v19, s10, 1.0
; GFX9-NEXT: v_add_f32_e64 v18, s11, 1.0
; GFX9-NEXT: v_add_f32_e64 v17, s12, 1.0
; GFX9-NEXT: v_add_f32_e64 v16, s13, 1.0
; GFX9-NEXT: v_add_f32_e64 v15, s14, 1.0
; GFX9-NEXT: v_add_f32_e64 v14, s15, 1.0
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: s_branch .LBB33_6
; GFX9-NEXT: .LBB33_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: v_mov_b32_e32 v55, s79
; GFX9-NEXT: v_mov_b32_e32 v54, s78
; GFX9-NEXT: v_mov_b32_e32 v53, s77
; GFX9-NEXT: v_mov_b32_e32 v52, s76
; GFX9-NEXT: v_mov_b32_e32 v51, s75
; GFX9-NEXT: v_mov_b32_e32 v50, s74
; GFX9-NEXT: v_mov_b32_e32 v49, s73
; GFX9-NEXT: v_mov_b32_e32 v48, s72
; GFX9-NEXT: v_mov_b32_e32 v39, s63
; GFX9-NEXT: v_mov_b32_e32 v38, s62
; GFX9-NEXT: v_mov_b32_e32 v37, s61
; GFX9-NEXT: v_mov_b32_e32 v36, s60
; GFX9-NEXT: v_mov_b32_e32 v35, s59
; GFX9-NEXT: v_mov_b32_e32 v34, s58
; GFX9-NEXT: v_mov_b32_e32 v33, s57
; GFX9-NEXT: v_mov_b32_e32 v32, s56
; GFX9-NEXT: v_mov_b32_e32 v31, s47
; GFX9-NEXT: v_mov_b32_e32 v30, s46
; GFX9-NEXT: v_mov_b32_e32 v29, s45
; GFX9-NEXT: v_mov_b32_e32 v28, s44
; GFX9-NEXT: v_mov_b32_e32 v27, s43
; GFX9-NEXT: v_mov_b32_e32 v26, s42
; GFX9-NEXT: v_mov_b32_e32 v25, s41
; GFX9-NEXT: v_mov_b32_e32 v24, s40
; GFX9-NEXT: .LBB33_6: ; %end
; GFX9-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; GFX9-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; GFX9-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX9-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX9-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v55, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v1, v54, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v2, v53, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v3, v52, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v6, v49, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v7, v48, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v8, v39, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v9, v38, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v10, v37, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v11, v36, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v12, v35, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v13, v34, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v14, v33, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v15, v32, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v16, v31, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v17, v30, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v18, v29, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v19, v28, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v20, v27, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v21, v26, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v22, v25, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v24f32_to_v48f16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s12, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB33_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s6, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s7, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s8, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s9, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s26, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s25, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s24, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s23, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s56, s22, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s21, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s20, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s19, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s60, s18, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s61, s17, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s62, s16, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s63, s3, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s72, s2, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s73, s1, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-TRUE16-NEXT: s_branch .LBB33_3
; GFX11-TRUE16-NEXT: .LBB33_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr73
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr72
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr63
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr62
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr61
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr60
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr59
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr58
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr57
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr56
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr47
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr46
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr45
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr44
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr43
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr42
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr41
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr40
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr15
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr14
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr13
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr11
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr10
; GFX11-TRUE16-NEXT: .LBB33_3: ; %Flow
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB33_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, s4, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, s5, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, s6, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, s7, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, s8, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, s9, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, s29, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, s28, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, s27, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, s26, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, s25, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, s24, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, s23, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, s22, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, s21, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, s20, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, s19, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, s18, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, s17, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, s16, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, s3, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, s2, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, s1, 1.0
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, s0, 1.0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-TRUE16-NEXT: s_branch .LBB33_6
; GFX11-TRUE16-NEXT: .LBB33_5:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s74 :: v_dual_mov_b32 v54, s73
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, s72 :: v_dual_mov_b32 v52, s63
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, s62 :: v_dual_mov_b32 v50, s61
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, s60 :: v_dual_mov_b32 v48, s59
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, s58 :: v_dual_mov_b32 v38, s57
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, s56 :: v_dual_mov_b32 v36, s47
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s46 :: v_dual_mov_b32 v34, s45
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, s44 :: v_dual_mov_b32 v32, s43
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s42 :: v_dual_mov_b32 v30, s41
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, s40 :: v_dual_mov_b32 v28, s15
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, s14 :: v_dual_mov_b32 v26, s13
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s11 :: v_dual_mov_b32 v24, s10
; GFX11-TRUE16-NEXT: .LBB33_6: ; %end
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v24f32_to_v48f16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s12, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB33_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s6, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s14, s7, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s15, s8, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s40, s9, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s44, s26, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s25, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s24, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s23, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s22, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s21, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s20, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s19, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s60, s18, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s61, s17, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s62, s16, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s63, s3, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s72, s2, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s73, s1, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-FAKE16-NEXT: s_branch .LBB33_3
; GFX11-FAKE16-NEXT: .LBB33_2:
; GFX11-FAKE16-NEXT: s_mov_b32 s12, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr72
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr62
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr61
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr58
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr57
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr46
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr45
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr40
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr15
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr14
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr13
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr11
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr10
; GFX11-FAKE16-NEXT: .LBB33_3: ; %Flow
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-FAKE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB33_5
; GFX11-FAKE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, s4, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, s5, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, s6, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, s7, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, s8, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, s9, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, s29, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, s28, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, s27, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, s26, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, s25, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, s24, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, s23, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, s22, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, s21, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, s20, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, s19, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, s18, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, s17, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, s16, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, s3, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, s2, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, s1, 1.0
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, s0, 1.0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; GFX11-FAKE16-NEXT: s_branch .LBB33_6
; GFX11-FAKE16-NEXT: .LBB33_5:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v2, s1
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v0, s3
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v7, s17
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v5, s19
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v13, s21
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s22 :: v_dual_mov_b32 v11, s23
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s24 :: v_dual_mov_b32 v9, s25
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s26 :: v_dual_mov_b32 v17, s27
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v15, s29
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v23, s8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, s7 :: v_dual_mov_b32 v21, s6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, s5 :: v_dual_mov_b32 v19, s4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, s74 :: v_dual_mov_b32 v54, s73
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, s72 :: v_dual_mov_b32 v52, s63
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, s62 :: v_dual_mov_b32 v50, s61
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, s60 :: v_dual_mov_b32 v48, s59
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, s58 :: v_dual_mov_b32 v38, s57
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, s56 :: v_dual_mov_b32 v36, s47
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, s46 :: v_dual_mov_b32 v34, s45
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, s44 :: v_dual_mov_b32 v32, s43
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, s42 :: v_dual_mov_b32 v30, s41
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, s40 :: v_dual_mov_b32 v28, s15
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, s14 :: v_dual_mov_b32 v26, s13
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, s11 :: v_dual_mov_b32 v24, s10
; GFX11-FAKE16-NEXT: .LBB33_6: ; %end
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v53, 16, v64
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v52, 16, v65
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v51, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v48, 16, v52
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v39, 16, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v39, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v38, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v35, 16, v39
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v34, 16, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v30, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v29, 16, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v25, 16, v29
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v24, 16, v30
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <24 x float> %a, splat (float 1.000000e+00)
%a2 = bitcast <24 x float> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <24 x float> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define <24 x float> @bitcast_v48f16_to_v24f32(<48 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v24f32:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB34_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v58
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v33
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v57
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB34_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB34_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v59
; SI-NEXT: v_cvt_f32_f16_e32 v2, v35
; SI-NEXT: v_cvt_f32_f16_e32 v1, v47
; SI-NEXT: v_cvt_f32_f16_e32 v3, v46
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_or_b32_e32 v1, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, v34
; SI-NEXT: v_cvt_f32_f16_e32 v3, v45
; SI-NEXT: v_cvt_f32_f16_e32 v4, v44
; SI-NEXT: v_cvt_f32_f16_e32 v5, v43
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v3, v58
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v42
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v7, v41
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, v33
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v40
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v9, v55
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_cvt_f32_f16_e32 v5, v57
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v54
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v11, v53
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v32
; SI-NEXT: v_cvt_f32_f16_e32 v12, v60
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f32_f16_e32 v13, v52
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_cvt_f32_f16_e32 v7, v56
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f32_f16_e32 v14, v51
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v16, v49
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v63
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v17, v48
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v19, v38
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_cvt_f32_f16_e32 v9, v62
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_cvt_f32_f16_e32 v20, v37
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v61
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_cvt_f32_f16_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, v50
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, v39
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, v36
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: .LBB34_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v24f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB34_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB34_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB34_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_add_f16_sdwa v0, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v47
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_add_f16_sdwa v1, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v46
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_f16_sdwa v2, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v45
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_add_f16_sdwa v3, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v44
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_add_f16_sdwa v4, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v43
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_add_f16_sdwa v5, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v42
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_add_f16_sdwa v6, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v41
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_add_f16_sdwa v7, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, 0x200, v40
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_f16_sdwa v8, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, 0x200, v55
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_add_f16_sdwa v9, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, 0x200, v54
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_add_f16_sdwa v10, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, 0x200, v53
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_add_f16_sdwa v11, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, 0x200, v52
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_add_f16_sdwa v12, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, 0x200, v51
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_add_f16_sdwa v13, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v50
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_add_f16_sdwa v14, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, 0x200, v49
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_add_f16_sdwa v15, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, 0x200, v48
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_add_f16_sdwa v16, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, 0x200, v39
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_add_f16_sdwa v17, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v38
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_add_f16_sdwa v18, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, 0x200, v37
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_add_f16_sdwa v19, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v36
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_add_f16_sdwa v20, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, 0x200, v35
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_add_f16_sdwa v21, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v34
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_add_f16_sdwa v22, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v33
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB34_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v24f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB34_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB34_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB34_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: s_movk_i32 s7, 0x200
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_f16 v0, v0, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, v14, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, v15, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, v16, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, v17, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, v18, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, v19, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, v20, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB34_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v24f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB34_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB34_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v24f32:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB34_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: .LBB34_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define inreg <24 x float> @bitcast_v48f16_to_v24f32_scalar(<48 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v24f32_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s34, 0
; SI-NEXT: v_writelane_b32 v32, s35, 1
; SI-NEXT: v_writelane_b32 v32, s36, 2
; SI-NEXT: v_writelane_b32 v32, s37, 3
; SI-NEXT: v_writelane_b32 v32, s38, 4
; SI-NEXT: v_writelane_b32 v32, s39, 5
; SI-NEXT: v_writelane_b32 v32, s48, 6
; SI-NEXT: v_writelane_b32 v32, s49, 7
; SI-NEXT: v_writelane_b32 v32, s50, 8
; SI-NEXT: v_writelane_b32 v32, s51, 9
; SI-NEXT: v_writelane_b32 v32, s52, 10
; SI-NEXT: v_writelane_b32 v32, s53, 11
; SI-NEXT: v_writelane_b32 v32, s54, 12
; SI-NEXT: v_writelane_b32 v32, s55, 13
; SI-NEXT: v_writelane_b32 v32, s64, 14
; SI-NEXT: v_writelane_b32 v32, s65, 15
; SI-NEXT: v_writelane_b32 v32, s66, 16
; SI-NEXT: v_writelane_b32 v32, s67, 17
; SI-NEXT: v_writelane_b32 v32, s68, 18
; SI-NEXT: v_writelane_b32 v32, s69, 19
; SI-NEXT: v_writelane_b32 v32, s30, 20
; SI-NEXT: v_writelane_b32 v32, s31, 21
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s8, v8
; SI-NEXT: v_readfirstlane_b32 s10, v7
; SI-NEXT: v_readfirstlane_b32 s12, v6
; SI-NEXT: v_readfirstlane_b32 s14, v5
; SI-NEXT: v_readfirstlane_b32 s72, v4
; SI-NEXT: v_readfirstlane_b32 s74, v3
; SI-NEXT: v_readfirstlane_b32 s76, v2
; SI-NEXT: v_readfirstlane_b32 s79, v1
; SI-NEXT: v_readfirstlane_b32 s89, v0
; SI-NEXT: s_lshr_b32 s78, s29, 16
; SI-NEXT: s_lshr_b32 s90, s28, 16
; SI-NEXT: s_lshr_b32 s92, s27, 16
; SI-NEXT: s_lshr_b32 s93, s26, 16
; SI-NEXT: s_lshr_b32 s94, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s4, s21, 16
; SI-NEXT: s_lshr_b32 s30, s20, 16
; SI-NEXT: s_lshr_b32 s31, s19, 16
; SI-NEXT: s_lshr_b32 s34, s18, 16
; SI-NEXT: s_lshr_b32 s68, s17, 16
; SI-NEXT: s_lshr_b32 s69, s16, 16
; SI-NEXT: s_lshr_b32 s35, s6, 16
; SI-NEXT: s_lshr_b32 s9, s8, 16
; SI-NEXT: s_lshr_b32 s11, s10, 16
; SI-NEXT: s_lshr_b32 s13, s12, 16
; SI-NEXT: s_lshr_b32 s15, s14, 16
; SI-NEXT: s_lshr_b32 s73, s72, 16
; SI-NEXT: s_lshr_b32 s75, s74, 16
; SI-NEXT: s_lshr_b32 s77, s76, 16
; SI-NEXT: s_lshr_b32 s88, s79, 16
; SI-NEXT: s_lshr_b32 s91, s89, 16
; SI-NEXT: v_readfirstlane_b32 s5, v10
; SI-NEXT: s_cmp_lg_u32 s5, 0
; SI-NEXT: s_cbranch_scc0 .LBB35_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s5, s16, 0xffff
; SI-NEXT: s_lshl_b32 s7, s69, 16
; SI-NEXT: s_or_b32 s36, s5, s7
; SI-NEXT: s_and_b32 s5, s17, 0xffff
; SI-NEXT: s_lshl_b32 s7, s68, 16
; SI-NEXT: s_or_b32 s37, s5, s7
; SI-NEXT: s_and_b32 s5, s18, 0xffff
; SI-NEXT: s_lshl_b32 s7, s34, 16
; SI-NEXT: s_or_b32 s38, s5, s7
; SI-NEXT: s_and_b32 s5, s19, 0xffff
; SI-NEXT: s_lshl_b32 s7, s31, 16
; SI-NEXT: s_or_b32 s39, s5, s7
; SI-NEXT: s_and_b32 s5, s20, 0xffff
; SI-NEXT: s_lshl_b32 s7, s30, 16
; SI-NEXT: s_or_b32 s40, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xffff
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_or_b32 s41, s5, s4
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s94, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s89, 0xffff
; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s79, 0xffff
; SI-NEXT: s_lshl_b32 s5, s88, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
; SI-NEXT: s_lshl_b32 s5, s13, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
; SI-NEXT: s_lshl_b32 s5, s11, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB35_3
; SI-NEXT: .LBB35_2:
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: .LBB35_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB35_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s69
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
; SI-NEXT: v_cvt_f32_f16_e32 v2, s68
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, s34
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_cvt_f32_f16_e32 v4, s31
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, s30
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, s20
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, s7
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, vcc_hi
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, vcc_lo
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_cvt_f32_f16_e32 v8, s23
; SI-NEXT: v_cvt_f32_f16_e32 v9, s95
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; SI-NEXT: v_cvt_f32_f16_e32 v9, s94
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s93
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v11, v9
; SI-NEXT: v_cvt_f32_f16_e32 v11, s26
; SI-NEXT: v_cvt_f32_f16_e32 v12, s92
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s90
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s78
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, s29
; SI-NEXT: v_cvt_f32_f16_e32 v15, s91
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_cvt_f32_f16_e32 v16, s89
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: v_cvt_f32_f16_e32 v15, s88
; SI-NEXT: v_cvt_f32_f16_e32 v17, s79
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s77
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, s76
; SI-NEXT: v_cvt_f32_f16_e32 v18, s75
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v19, s74
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_cvt_f32_f16_e32 v18, s73
; SI-NEXT: v_cvt_f32_f16_e32 v20, s72
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s15
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, s14
; SI-NEXT: v_cvt_f32_f16_e32 v21, s13
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_cvt_f32_f16_e32 v22, s12
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: v_cvt_f32_f16_e32 v21, s11
; SI-NEXT: v_cvt_f32_f16_e32 v23, s10
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s9
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: v_cvt_f32_f16_e32 v23, s8
; SI-NEXT: v_cvt_f32_f16_e32 v24, s35
; SI-NEXT: v_cvt_f32_f16_e32 v25, s6
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: s_branch .LBB35_6
; SI-NEXT: .LBB35_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB35_6: ; %end
; SI-NEXT: v_readlane_b32 s30, v32, 20
; SI-NEXT: v_readlane_b32 s31, v32, 21
; SI-NEXT: v_readlane_b32 s69, v32, 19
; SI-NEXT: v_readlane_b32 s68, v32, 18
; SI-NEXT: v_readlane_b32 s67, v32, 17
; SI-NEXT: v_readlane_b32 s66, v32, 16
; SI-NEXT: v_readlane_b32 s65, v32, 15
; SI-NEXT: v_readlane_b32 s64, v32, 14
; SI-NEXT: v_readlane_b32 s55, v32, 13
; SI-NEXT: v_readlane_b32 s54, v32, 12
; SI-NEXT: v_readlane_b32 s53, v32, 11
; SI-NEXT: v_readlane_b32 s52, v32, 10
; SI-NEXT: v_readlane_b32 s51, v32, 9
; SI-NEXT: v_readlane_b32 s50, v32, 8
; SI-NEXT: v_readlane_b32 s49, v32, 7
; SI-NEXT: v_readlane_b32 s48, v32, 6
; SI-NEXT: v_readlane_b32 s39, v32, 5
; SI-NEXT: v_readlane_b32 s38, v32, 4
; SI-NEXT: v_readlane_b32 s37, v32, 3
; SI-NEXT: v_readlane_b32 s36, v32, 2
; SI-NEXT: v_readlane_b32 s35, v32, 1
; SI-NEXT: v_readlane_b32 s34, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v24f32_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s34, 0
; VI-NEXT: v_writelane_b32 v32, s35, 1
; VI-NEXT: v_writelane_b32 v32, s36, 2
; VI-NEXT: v_writelane_b32 v32, s37, 3
; VI-NEXT: v_writelane_b32 v32, s38, 4
; VI-NEXT: v_writelane_b32 v32, s39, 5
; VI-NEXT: v_writelane_b32 v32, s48, 6
; VI-NEXT: v_writelane_b32 v32, s49, 7
; VI-NEXT: v_writelane_b32 v32, s50, 8
; VI-NEXT: v_writelane_b32 v32, s51, 9
; VI-NEXT: v_writelane_b32 v32, s52, 10
; VI-NEXT: v_writelane_b32 v32, s53, 11
; VI-NEXT: v_writelane_b32 v32, s54, 12
; VI-NEXT: v_writelane_b32 v32, s55, 13
; VI-NEXT: v_writelane_b32 v32, s64, 14
; VI-NEXT: v_writelane_b32 v32, s65, 15
; VI-NEXT: v_writelane_b32 v32, s66, 16
; VI-NEXT: v_writelane_b32 v32, s67, 17
; VI-NEXT: v_writelane_b32 v32, s68, 18
; VI-NEXT: v_writelane_b32 v32, s69, 19
; VI-NEXT: v_writelane_b32 v32, s70, 20
; VI-NEXT: v_writelane_b32 v32, s71, 21
; VI-NEXT: v_writelane_b32 v32, s80, 22
; VI-NEXT: v_writelane_b32 v32, s81, 23
; VI-NEXT: v_writelane_b32 v32, s30, 24
; VI-NEXT: v_writelane_b32 v32, s31, 25
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s8, v8
; VI-NEXT: v_readfirstlane_b32 s10, v7
; VI-NEXT: v_readfirstlane_b32 s12, v6
; VI-NEXT: v_readfirstlane_b32 s14, v5
; VI-NEXT: v_readfirstlane_b32 s73, v4
; VI-NEXT: v_readfirstlane_b32 s76, v3
; VI-NEXT: v_readfirstlane_b32 s79, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s4, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s74, s28, 16
; VI-NEXT: s_lshr_b32 s77, s27, 16
; VI-NEXT: s_lshr_b32 s88, s26, 16
; VI-NEXT: s_lshr_b32 s90, s25, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s24, 16
; VI-NEXT: s_lshr_b32 s31, s23, 16
; VI-NEXT: s_lshr_b32 s34, s22, 16
; VI-NEXT: s_lshr_b32 s35, s21, 16
; VI-NEXT: s_lshr_b32 s68, s20, 16
; VI-NEXT: s_lshr_b32 s69, s19, 16
; VI-NEXT: s_lshr_b32 s70, s18, 16
; VI-NEXT: s_lshr_b32 s71, s17, 16
; VI-NEXT: s_lshr_b32 s80, s16, 16
; VI-NEXT: s_lshr_b32 s81, s6, 16
; VI-NEXT: s_lshr_b32 s9, s8, 16
; VI-NEXT: s_lshr_b32 s11, s10, 16
; VI-NEXT: s_lshr_b32 s13, s12, 16
; VI-NEXT: s_lshr_b32 s15, s14, 16
; VI-NEXT: s_lshr_b32 s75, s73, 16
; VI-NEXT: s_lshr_b32 s78, s76, 16
; VI-NEXT: s_lshr_b32 s89, s79, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s91, 16
; VI-NEXT: s_lshr_b32 s30, s4, 16
; VI-NEXT: v_readfirstlane_b32 s5, v10
; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc0 .LBB35_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s5, 0xffff, s16
; VI-NEXT: s_lshl_b32 s7, s80, 16
; VI-NEXT: s_or_b32 s36, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s7, s71, 16
; VI-NEXT: s_or_b32 s37, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s18
; VI-NEXT: s_lshl_b32 s7, s70, 16
; VI-NEXT: s_or_b32 s38, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s19
; VI-NEXT: s_lshl_b32 s7, s69, 16
; VI-NEXT: s_or_b32 s39, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s20
; VI-NEXT: s_lshl_b32 s7, s68, 16
; VI-NEXT: s_or_b32 s40, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s21
; VI-NEXT: s_lshl_b32 s7, s35, 16
; VI-NEXT: s_or_b32 s41, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s22
; VI-NEXT: s_lshl_b32 s7, s34, 16
; VI-NEXT: s_or_b32 s42, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s23
; VI-NEXT: s_lshl_b32 s7, s31, 16
; VI-NEXT: s_or_b32 s43, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s24
; VI-NEXT: s_lshl_b32 s7, vcc_hi, 16
; VI-NEXT: s_or_b32 s44, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s25
; VI-NEXT: s_lshl_b32 s7, s90, 16
; VI-NEXT: s_or_b32 s45, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s26
; VI-NEXT: s_lshl_b32 s7, s88, 16
; VI-NEXT: s_or_b32 s46, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s27
; VI-NEXT: s_lshl_b32 s7, s77, 16
; VI-NEXT: s_or_b32 s47, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s28
; VI-NEXT: s_lshl_b32 s7, s74, 16
; VI-NEXT: s_or_b32 s48, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s29
; VI-NEXT: s_lshl_b32 s7, s72, 16
; VI-NEXT: s_or_b32 s49, s5, s7
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_and_b32 s4, 0xffff, s4
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s15, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB35_3
; VI-NEXT: .LBB35_2:
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: .LBB35_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB35_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_mov_b32_e32 v0, s80
; VI-NEXT: v_mov_b32_e32 v2, s71
; VI-NEXT: v_add_f16_sdwa v0, v0, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v23
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v23
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v23
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_mov_b32_e32 v3, s69
; VI-NEXT: v_add_f16_sdwa v3, v3, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v23
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_mov_b32_e32 v4, s68
; VI-NEXT: v_add_f16_sdwa v4, v4, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v23
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_mov_b32_e32 v5, s35
; VI-NEXT: v_add_f16_sdwa v5, v5, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v23
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_mov_b32_e32 v6, s34
; VI-NEXT: v_add_f16_sdwa v6, v6, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v23
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_mov_b32_e32 v7, s31
; VI-NEXT: v_add_f16_sdwa v7, v7, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v23
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_mov_b32_e32 v8, vcc_hi
; VI-NEXT: v_add_f16_sdwa v8, v8, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v23
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_mov_b32_e32 v9, s90
; VI-NEXT: v_add_f16_sdwa v9, v9, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v23
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_mov_b32_e32 v10, s88
; VI-NEXT: v_add_f16_sdwa v10, v10, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v23
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_mov_b32_e32 v11, s77
; VI-NEXT: v_add_f16_sdwa v11, v11, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v23
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_mov_b32_e32 v12, s74
; VI-NEXT: v_add_f16_sdwa v12, v12, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v23
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_mov_b32_e32 v13, s72
; VI-NEXT: v_add_f16_sdwa v13, v13, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v23
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_add_f16_sdwa v14, v14, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v23
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_mov_b32_e32 v15, vcc_lo
; VI-NEXT: v_add_f16_sdwa v15, v15, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s91, v23
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_mov_b32_e32 v16, s89
; VI-NEXT: v_add_f16_sdwa v16, v16, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s79, v23
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_mov_b32_e32 v17, s78
; VI-NEXT: v_add_f16_sdwa v17, v17, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s76, v23
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_mov_b32_e32 v18, s75
; VI-NEXT: v_add_f16_sdwa v18, v18, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s73, v23
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_mov_b32_e32 v19, s15
; VI-NEXT: v_add_f16_sdwa v19, v19, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s14, v23
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_mov_b32_e32 v20, s13
; VI-NEXT: v_add_f16_sdwa v20, v20, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s12, v23
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_mov_b32_e32 v21, s11
; VI-NEXT: v_add_f16_sdwa v21, v21, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s10, v23
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_mov_b32_e32 v22, s9
; VI-NEXT: v_add_f16_sdwa v22, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s8, v23
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_mov_b32_e32 v24, s81
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: s_branch .LBB35_6
; VI-NEXT: .LBB35_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB35_6: ; %end
; VI-NEXT: v_readlane_b32 s30, v32, 24
; VI-NEXT: v_readlane_b32 s31, v32, 25
; VI-NEXT: v_readlane_b32 s81, v32, 23
; VI-NEXT: v_readlane_b32 s80, v32, 22
; VI-NEXT: v_readlane_b32 s71, v32, 21
; VI-NEXT: v_readlane_b32 s70, v32, 20
; VI-NEXT: v_readlane_b32 s69, v32, 19
; VI-NEXT: v_readlane_b32 s68, v32, 18
; VI-NEXT: v_readlane_b32 s67, v32, 17
; VI-NEXT: v_readlane_b32 s66, v32, 16
; VI-NEXT: v_readlane_b32 s65, v32, 15
; VI-NEXT: v_readlane_b32 s64, v32, 14
; VI-NEXT: v_readlane_b32 s55, v32, 13
; VI-NEXT: v_readlane_b32 s54, v32, 12
; VI-NEXT: v_readlane_b32 s53, v32, 11
; VI-NEXT: v_readlane_b32 s52, v32, 10
; VI-NEXT: v_readlane_b32 s51, v32, 9
; VI-NEXT: v_readlane_b32 s50, v32, 8
; VI-NEXT: v_readlane_b32 s49, v32, 7
; VI-NEXT: v_readlane_b32 s48, v32, 6
; VI-NEXT: v_readlane_b32 s39, v32, 5
; VI-NEXT: v_readlane_b32 s38, v32, 4
; VI-NEXT: v_readlane_b32 s37, v32, 3
; VI-NEXT: v_readlane_b32 s36, v32, 2
; VI-NEXT: v_readlane_b32 s35, v32, 1
; VI-NEXT: v_readlane_b32 s34, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v24f32_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB35_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB35_3
; GFX9-NEXT: .LBB35_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB35_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB35_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_mov_b32_e32 v23, 0x200
; GFX9-NEXT: v_pk_add_f16 v0, s36, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s37, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, s38, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, s39, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, s40, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, s41, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, s42, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, s43, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, s44, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, s45, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, s46, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, s47, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, s48, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, s49, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, s50, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, s51, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB35_6
; GFX9-NEXT: .LBB35_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB35_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48f16_to_v24f32_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB35_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB35_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB35_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB35_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <24 x float>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <24 x float>
br label %end
end:
%phi = phi <24 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <24 x float> %phi
}
define <12 x double> @bitcast_v12i64_to_v12f64(<12 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v12f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB36_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; SI-NEXT: .LBB36_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v12f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB36_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; VI-NEXT: .LBB36_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v12f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB36_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, 3, v16
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, 3, v18
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, 3, v20
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, 3, v22
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v23, vcc
; GFX9-NEXT: .LBB36_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v12f64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB36_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
; GFX11-NEXT: .LBB36_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define inreg <12 x double> @bitcast_v12i64_to_v12f64_scalar(<12 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v12f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s7, v8
; SI-NEXT: v_readfirstlane_b32 s8, v7
; SI-NEXT: v_readfirstlane_b32 s9, v6
; SI-NEXT: v_readfirstlane_b32 s10, v5
; SI-NEXT: v_readfirstlane_b32 s11, v4
; SI-NEXT: v_readfirstlane_b32 s12, v3
; SI-NEXT: v_readfirstlane_b32 s13, v2
; SI-NEXT: v_readfirstlane_b32 s14, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s15, v0
; SI-NEXT: s_cbranch_scc0 .LBB37_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB37_3
; SI-NEXT: .LBB37_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB37_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB37_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
; SI-NEXT: s_add_u32 s18, s18, 3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s20, s20, 3
; SI-NEXT: s_addc_u32 s21, s21, 0
; SI-NEXT: s_add_u32 s22, s22, 3
; SI-NEXT: s_addc_u32 s23, s23, 0
; SI-NEXT: s_add_u32 s24, s24, 3
; SI-NEXT: s_addc_u32 s25, s25, 0
; SI-NEXT: s_add_u32 s26, s26, 3
; SI-NEXT: s_addc_u32 s27, s27, 0
; SI-NEXT: s_add_u32 s28, s28, 3
; SI-NEXT: s_addc_u32 s29, s29, 0
; SI-NEXT: s_add_u32 s15, s15, 3
; SI-NEXT: s_addc_u32 s14, s14, 0
; SI-NEXT: s_add_u32 s13, s13, 3
; SI-NEXT: s_addc_u32 s12, s12, 0
; SI-NEXT: s_add_u32 s11, s11, 3
; SI-NEXT: s_addc_u32 s10, s10, 0
; SI-NEXT: s_add_u32 s9, s9, 3
; SI-NEXT: s_addc_u32 s8, s8, 0
; SI-NEXT: s_add_u32 s7, s7, 3
; SI-NEXT: s_addc_u32 s6, s6, 0
; SI-NEXT: .LBB37_5: ; %end
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v14, s15
; SI-NEXT: v_mov_b32_e32 v15, s14
; SI-NEXT: v_mov_b32_e32 v16, s13
; SI-NEXT: v_mov_b32_e32 v17, s12
; SI-NEXT: v_mov_b32_e32 v18, s11
; SI-NEXT: v_mov_b32_e32 v19, s10
; SI-NEXT: v_mov_b32_e32 v20, s9
; SI-NEXT: v_mov_b32_e32 v21, s8
; SI-NEXT: v_mov_b32_e32 v22, s7
; SI-NEXT: v_mov_b32_e32 v23, s6
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v12f64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB37_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB37_3
; VI-NEXT: .LBB37_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB37_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB37_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
; VI-NEXT: s_add_u32 s18, s18, 3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s20, s20, 3
; VI-NEXT: s_addc_u32 s21, s21, 0
; VI-NEXT: s_add_u32 s22, s22, 3
; VI-NEXT: s_addc_u32 s23, s23, 0
; VI-NEXT: s_add_u32 s24, s24, 3
; VI-NEXT: s_addc_u32 s25, s25, 0
; VI-NEXT: s_add_u32 s26, s26, 3
; VI-NEXT: s_addc_u32 s27, s27, 0
; VI-NEXT: s_add_u32 s28, s28, 3
; VI-NEXT: s_addc_u32 s29, s29, 0
; VI-NEXT: s_add_u32 s15, s15, 3
; VI-NEXT: s_addc_u32 s14, s14, 0
; VI-NEXT: s_add_u32 s13, s13, 3
; VI-NEXT: s_addc_u32 s12, s12, 0
; VI-NEXT: s_add_u32 s11, s11, 3
; VI-NEXT: s_addc_u32 s10, s10, 0
; VI-NEXT: s_add_u32 s9, s9, 3
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
; VI-NEXT: .LBB37_5: ; %end
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v12f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB37_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB37_3
; GFX9-NEXT: .LBB37_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB37_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB37_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
; GFX9-NEXT: s_add_u32 s18, s18, 3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s20, s20, 3
; GFX9-NEXT: s_addc_u32 s21, s21, 0
; GFX9-NEXT: s_add_u32 s22, s22, 3
; GFX9-NEXT: s_addc_u32 s23, s23, 0
; GFX9-NEXT: s_add_u32 s24, s24, 3
; GFX9-NEXT: s_addc_u32 s25, s25, 0
; GFX9-NEXT: s_add_u32 s26, s26, 3
; GFX9-NEXT: s_addc_u32 s27, s27, 0
; GFX9-NEXT: s_add_u32 s28, s28, 3
; GFX9-NEXT: s_addc_u32 s29, s29, 0
; GFX9-NEXT: s_add_u32 s15, s15, 3
; GFX9-NEXT: s_addc_u32 s14, s14, 0
; GFX9-NEXT: s_add_u32 s13, s13, 3
; GFX9-NEXT: s_addc_u32 s12, s12, 0
; GFX9-NEXT: s_add_u32 s11, s11, 3
; GFX9-NEXT: s_addc_u32 s10, s10, 0
; GFX9-NEXT: s_add_u32 s9, s9, 3
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
; GFX9-NEXT: .LBB37_5: ; %end
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v12f64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s10, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB37_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s10, -1
; GFX11-NEXT: .LBB37_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s10, s10, exec_lo
; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s10, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB37_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_add_u32 s2, s2, 3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s16, s16, 3
; GFX11-NEXT: s_addc_u32 s17, s17, 0
; GFX11-NEXT: s_add_u32 s18, s18, 3
; GFX11-NEXT: s_addc_u32 s19, s19, 0
; GFX11-NEXT: s_add_u32 s20, s20, 3
; GFX11-NEXT: s_addc_u32 s21, s21, 0
; GFX11-NEXT: s_add_u32 s22, s22, 3
; GFX11-NEXT: s_addc_u32 s23, s23, 0
; GFX11-NEXT: s_add_u32 s24, s24, 3
; GFX11-NEXT: s_addc_u32 s25, s25, 0
; GFX11-NEXT: s_add_u32 s26, s26, 3
; GFX11-NEXT: s_addc_u32 s27, s27, 0
; GFX11-NEXT: s_add_u32 s28, s28, 3
; GFX11-NEXT: s_addc_u32 s29, s29, 0
; GFX11-NEXT: s_add_u32 s9, s9, 3
; GFX11-NEXT: s_addc_u32 s8, s8, 0
; GFX11-NEXT: s_add_u32 s7, s7, 3
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
; GFX11-NEXT: .LBB37_4: ; %end
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define <12 x i64> @bitcast_v12f64_to_v12i64(<12 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v12i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB38_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; SI-NEXT: .LBB38_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v12i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB38_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; VI-NEXT: .LBB38_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v12i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB38_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX9-NEXT: .LBB38_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12f64_to_v12i64:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, exec_lo
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-NEXT: s_cbranch_execz .LBB38_2
; GFX11-NEXT: ; %bb.1: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-NEXT: .LBB38_2: ; %end
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define inreg <12 x i64> @bitcast_v12f64_to_v12i64_scalar(<12 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v12i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s36, 0
; SI-NEXT: v_writelane_b32 v32, s37, 1
; SI-NEXT: v_writelane_b32 v32, s38, 2
; SI-NEXT: v_writelane_b32 v32, s39, 3
; SI-NEXT: v_writelane_b32 v32, s48, 4
; SI-NEXT: v_writelane_b32 v32, s49, 5
; SI-NEXT: v_writelane_b32 v32, s50, 6
; SI-NEXT: v_writelane_b32 v32, s51, 7
; SI-NEXT: v_writelane_b32 v32, s52, 8
; SI-NEXT: v_writelane_b32 v32, s53, 9
; SI-NEXT: v_writelane_b32 v32, s54, 10
; SI-NEXT: v_writelane_b32 v32, s55, 11
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_mov_b32 s49, s29
; SI-NEXT: s_mov_b32 s48, s28
; SI-NEXT: s_mov_b32 s47, s27
; SI-NEXT: s_mov_b32 s46, s26
; SI-NEXT: s_mov_b32 s45, s25
; SI-NEXT: s_mov_b32 s44, s24
; SI-NEXT: s_mov_b32 s43, s23
; SI-NEXT: s_mov_b32 s42, s22
; SI-NEXT: s_mov_b32 s41, s21
; SI-NEXT: s_mov_b32 s40, s20
; SI-NEXT: s_mov_b32 s39, s19
; SI-NEXT: s_mov_b32 s38, s18
; SI-NEXT: s_mov_b32 s37, s17
; SI-NEXT: s_mov_b32 s36, s16
; SI-NEXT: v_readfirstlane_b32 s59, v9
; SI-NEXT: v_readfirstlane_b32 s58, v8
; SI-NEXT: v_readfirstlane_b32 s57, v7
; SI-NEXT: v_readfirstlane_b32 s56, v6
; SI-NEXT: v_readfirstlane_b32 s55, v5
; SI-NEXT: v_readfirstlane_b32 s54, v4
; SI-NEXT: v_readfirstlane_b32 s53, v3
; SI-NEXT: v_readfirstlane_b32 s52, v2
; SI-NEXT: v_readfirstlane_b32 s51, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s50, v0
; SI-NEXT: s_cbranch_scc0 .LBB39_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB39_3
; SI-NEXT: .LBB39_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB39_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB39_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; SI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; SI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; SI-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; SI-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; SI-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; SI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; SI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; SI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; SI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; SI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; SI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; SI-NEXT: s_branch .LBB39_6
; SI-NEXT: .LBB39_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB39_6: ; %end
; SI-NEXT: v_readlane_b32 s55, v32, 11
; SI-NEXT: v_readlane_b32 s54, v32, 10
; SI-NEXT: v_readlane_b32 s53, v32, 9
; SI-NEXT: v_readlane_b32 s52, v32, 8
; SI-NEXT: v_readlane_b32 s51, v32, 7
; SI-NEXT: v_readlane_b32 s50, v32, 6
; SI-NEXT: v_readlane_b32 s49, v32, 5
; SI-NEXT: v_readlane_b32 s48, v32, 4
; SI-NEXT: v_readlane_b32 s39, v32, 3
; SI-NEXT: v_readlane_b32 s38, v32, 2
; SI-NEXT: v_readlane_b32 s37, v32, 1
; SI-NEXT: v_readlane_b32 s36, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v12i64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s36, 0
; VI-NEXT: v_writelane_b32 v32, s37, 1
; VI-NEXT: v_writelane_b32 v32, s38, 2
; VI-NEXT: v_writelane_b32 v32, s39, 3
; VI-NEXT: v_writelane_b32 v32, s48, 4
; VI-NEXT: v_writelane_b32 v32, s49, 5
; VI-NEXT: v_writelane_b32 v32, s50, 6
; VI-NEXT: v_writelane_b32 v32, s51, 7
; VI-NEXT: v_writelane_b32 v32, s52, 8
; VI-NEXT: v_writelane_b32 v32, s53, 9
; VI-NEXT: v_writelane_b32 v32, s54, 10
; VI-NEXT: v_writelane_b32 v32, s55, 11
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_mov_b32 s49, s29
; VI-NEXT: s_mov_b32 s48, s28
; VI-NEXT: s_mov_b32 s47, s27
; VI-NEXT: s_mov_b32 s46, s26
; VI-NEXT: s_mov_b32 s45, s25
; VI-NEXT: s_mov_b32 s44, s24
; VI-NEXT: s_mov_b32 s43, s23
; VI-NEXT: s_mov_b32 s42, s22
; VI-NEXT: s_mov_b32 s41, s21
; VI-NEXT: s_mov_b32 s40, s20
; VI-NEXT: s_mov_b32 s39, s19
; VI-NEXT: s_mov_b32 s38, s18
; VI-NEXT: s_mov_b32 s37, s17
; VI-NEXT: s_mov_b32 s36, s16
; VI-NEXT: v_readfirstlane_b32 s59, v9
; VI-NEXT: v_readfirstlane_b32 s58, v8
; VI-NEXT: v_readfirstlane_b32 s57, v7
; VI-NEXT: v_readfirstlane_b32 s56, v6
; VI-NEXT: v_readfirstlane_b32 s55, v5
; VI-NEXT: v_readfirstlane_b32 s54, v4
; VI-NEXT: v_readfirstlane_b32 s53, v3
; VI-NEXT: v_readfirstlane_b32 s52, v2
; VI-NEXT: v_readfirstlane_b32 s51, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s50, v0
; VI-NEXT: s_cbranch_scc0 .LBB39_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB39_3
; VI-NEXT: .LBB39_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB39_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB39_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; VI-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; VI-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; VI-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; VI-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; VI-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; VI-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; VI-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; VI-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; VI-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; VI-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; VI-NEXT: s_branch .LBB39_6
; VI-NEXT: .LBB39_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB39_6: ; %end
; VI-NEXT: v_readlane_b32 s55, v32, 11
; VI-NEXT: v_readlane_b32 s54, v32, 10
; VI-NEXT: v_readlane_b32 s53, v32, 9
; VI-NEXT: v_readlane_b32 s52, v32, 8
; VI-NEXT: v_readlane_b32 s51, v32, 7
; VI-NEXT: v_readlane_b32 s50, v32, 6
; VI-NEXT: v_readlane_b32 s49, v32, 5
; VI-NEXT: v_readlane_b32 s48, v32, 4
; VI-NEXT: v_readlane_b32 s39, v32, 3
; VI-NEXT: v_readlane_b32 s38, v32, 2
; VI-NEXT: v_readlane_b32 s37, v32, 1
; VI-NEXT: v_readlane_b32 s36, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v12i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_mov_b32 s49, s29
; GFX9-NEXT: s_mov_b32 s48, s28
; GFX9-NEXT: s_mov_b32 s47, s27
; GFX9-NEXT: s_mov_b32 s46, s26
; GFX9-NEXT: s_mov_b32 s45, s25
; GFX9-NEXT: s_mov_b32 s44, s24
; GFX9-NEXT: s_mov_b32 s43, s23
; GFX9-NEXT: s_mov_b32 s42, s22
; GFX9-NEXT: s_mov_b32 s41, s21
; GFX9-NEXT: s_mov_b32 s40, s20
; GFX9-NEXT: s_mov_b32 s39, s19
; GFX9-NEXT: s_mov_b32 s38, s18
; GFX9-NEXT: s_mov_b32 s37, s17
; GFX9-NEXT: s_mov_b32 s36, s16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s55, v5
; GFX9-NEXT: v_readfirstlane_b32 s54, v4
; GFX9-NEXT: v_readfirstlane_b32 s53, v3
; GFX9-NEXT: v_readfirstlane_b32 s52, v2
; GFX9-NEXT: v_readfirstlane_b32 s51, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s50, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB39_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB39_3
; GFX9-NEXT: .LBB39_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB39_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB39_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX9-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX9-NEXT: s_branch .LBB39_6
; GFX9-NEXT: .LBB39_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB39_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12f64_to_v12i64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
; GFX11-NEXT: scratch_store_b32 off, v32, s32 ; 4-byte Folded Spill
; GFX11-NEXT: s_mov_b32 exec_lo, s4
; GFX11-NEXT: v_writelane_b32 v32, s36, 0
; GFX11-NEXT: v_writelane_b32 v32, s37, 1
; GFX11-NEXT: v_writelane_b32 v32, s38, 2
; GFX11-NEXT: v_writelane_b32 v32, s39, 3
; GFX11-NEXT: v_writelane_b32 v32, s48, 4
; GFX11-NEXT: v_writelane_b32 v32, s49, 5
; GFX11-NEXT: v_writelane_b32 v32, s50, 6
; GFX11-NEXT: v_writelane_b32 v32, s51, 7
; GFX11-NEXT: v_writelane_b32 v32, s52, 8
; GFX11-NEXT: v_writelane_b32 v32, s53, 9
; GFX11-NEXT: v_writelane_b32 v32, s54, 10
; GFX11-NEXT: v_writelane_b32 v32, s55, 11
; GFX11-NEXT: s_mov_b32 s36, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v6
; GFX11-NEXT: v_readfirstlane_b32 s59, v5
; GFX11-NEXT: v_readfirstlane_b32 s58, v4
; GFX11-NEXT: v_readfirstlane_b32 s57, v3
; GFX11-NEXT: v_readfirstlane_b32 s56, v2
; GFX11-NEXT: v_readfirstlane_b32 s55, v1
; GFX11-NEXT: v_readfirstlane_b32 s54, v0
; GFX11-NEXT: s_mov_b32 s53, s29
; GFX11-NEXT: s_mov_b32 s52, s28
; GFX11-NEXT: s_mov_b32 s51, s27
; GFX11-NEXT: s_mov_b32 s50, s26
; GFX11-NEXT: s_mov_b32 s49, s25
; GFX11-NEXT: s_mov_b32 s48, s24
; GFX11-NEXT: s_mov_b32 s47, s23
; GFX11-NEXT: s_mov_b32 s46, s22
; GFX11-NEXT: s_mov_b32 s45, s21
; GFX11-NEXT: s_mov_b32 s44, s20
; GFX11-NEXT: s_mov_b32 s43, s19
; GFX11-NEXT: s_mov_b32 s42, s18
; GFX11-NEXT: s_mov_b32 s41, s17
; GFX11-NEXT: s_mov_b32 s40, s16
; GFX11-NEXT: s_mov_b32 s39, s3
; GFX11-NEXT: s_mov_b32 s38, s2
; GFX11-NEXT: s_mov_b32 s37, s1
; GFX11-NEXT: s_cmp_lg_u32 s0, 0
; GFX11-NEXT: s_mov_b32 s0, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB39_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s0, -1
; GFX11-NEXT: .LBB39_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s0, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB39_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_add_f64 v[0:1], s[36:37], 1.0
; GFX11-NEXT: v_add_f64 v[2:3], s[38:39], 1.0
; GFX11-NEXT: v_add_f64 v[4:5], s[40:41], 1.0
; GFX11-NEXT: v_add_f64 v[6:7], s[42:43], 1.0
; GFX11-NEXT: v_add_f64 v[8:9], s[44:45], 1.0
; GFX11-NEXT: v_add_f64 v[10:11], s[46:47], 1.0
; GFX11-NEXT: v_add_f64 v[12:13], s[48:49], 1.0
; GFX11-NEXT: v_add_f64 v[14:15], s[50:51], 1.0
; GFX11-NEXT: v_add_f64 v[16:17], s[52:53], 1.0
; GFX11-NEXT: v_add_f64 v[18:19], s[54:55], 1.0
; GFX11-NEXT: v_add_f64 v[20:21], s[56:57], 1.0
; GFX11-NEXT: v_add_f64 v[22:23], s[58:59], 1.0
; GFX11-NEXT: s_branch .LBB39_5
; GFX11-NEXT: .LBB39_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s36 :: v_dual_mov_b32 v1, s37
; GFX11-NEXT: v_dual_mov_b32 v2, s38 :: v_dual_mov_b32 v3, s39
; GFX11-NEXT: v_dual_mov_b32 v4, s40 :: v_dual_mov_b32 v5, s41
; GFX11-NEXT: v_dual_mov_b32 v6, s42 :: v_dual_mov_b32 v7, s43
; GFX11-NEXT: v_dual_mov_b32 v8, s44 :: v_dual_mov_b32 v9, s45
; GFX11-NEXT: v_dual_mov_b32 v10, s46 :: v_dual_mov_b32 v11, s47
; GFX11-NEXT: v_dual_mov_b32 v12, s48 :: v_dual_mov_b32 v13, s49
; GFX11-NEXT: v_dual_mov_b32 v14, s50 :: v_dual_mov_b32 v15, s51
; GFX11-NEXT: v_dual_mov_b32 v16, s52 :: v_dual_mov_b32 v17, s53
; GFX11-NEXT: v_dual_mov_b32 v18, s54 :: v_dual_mov_b32 v19, s55
; GFX11-NEXT: v_dual_mov_b32 v20, s56 :: v_dual_mov_b32 v21, s57
; GFX11-NEXT: v_dual_mov_b32 v22, s58 :: v_dual_mov_b32 v23, s59
; GFX11-NEXT: v_dual_mov_b32 v24, s60 :: v_dual_mov_b32 v25, s61
; GFX11-NEXT: v_dual_mov_b32 v26, s62 :: v_dual_mov_b32 v27, s63
; GFX11-NEXT: v_dual_mov_b32 v28, s64 :: v_dual_mov_b32 v29, s65
; GFX11-NEXT: v_dual_mov_b32 v30, s66 :: v_dual_mov_b32 v31, s67
; GFX11-NEXT: .LBB39_5: ; %end
; GFX11-NEXT: v_readlane_b32 s55, v32, 11
; GFX11-NEXT: v_readlane_b32 s54, v32, 10
; GFX11-NEXT: v_readlane_b32 s53, v32, 9
; GFX11-NEXT: v_readlane_b32 s52, v32, 8
; GFX11-NEXT: v_readlane_b32 s51, v32, 7
; GFX11-NEXT: v_readlane_b32 s50, v32, 6
; GFX11-NEXT: v_readlane_b32 s49, v32, 5
; GFX11-NEXT: v_readlane_b32 s48, v32, 4
; GFX11-NEXT: v_readlane_b32 s39, v32, 3
; GFX11-NEXT: v_readlane_b32 s38, v32, 2
; GFX11-NEXT: v_readlane_b32 s37, v32, 1
; GFX11-NEXT: v_readlane_b32 s36, v32, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v32, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define <48 x i16> @bitcast_v12i64_to_v48i16(<12 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB40_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v32, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v35, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB40_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB40_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v32, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v35, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB40_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v38
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v35
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v36
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v33
; SI-NEXT: v_or_b32_e32 v1, v1, v49
; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v35
; SI-NEXT: v_or_b32_e32 v7, v7, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v48i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB40_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB40_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB40_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB40_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v48i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB40_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB40_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB40_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, 3, v22
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v23, vcc
; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, 3, v20
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, 3, v18
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, 3, v16
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB40_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v12i64_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB40_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-TRUE16-NEXT: .LBB40_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12i64_to_v48i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB40_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB40_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB40_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB40_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define inreg <48 x i16> @bitcast_v12i64_to_v48i16_scalar(<12 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v48i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: v_readfirstlane_b32 s12, v10
; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_readfirstlane_b32 s4, v8
; SI-NEXT: v_readfirstlane_b32 s7, v7
; SI-NEXT: v_readfirstlane_b32 s6, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s11, v3
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_readfirstlane_b32 s13, v1
; SI-NEXT: s_cmp_lg_u32 s12, 0
; SI-NEXT: v_readfirstlane_b32 s12, v0
; SI-NEXT: ; implicit-def: $vgpr24 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB41_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s21, 16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v24, s40, 1
; SI-NEXT: s_lshr_b32 s40, s17, 16
; SI-NEXT: s_lshr_b32 s15, s5, 16
; SI-NEXT: s_lshr_b32 s90, s7, 16
; SI-NEXT: s_lshr_b32 s91, s9, 16
; SI-NEXT: s_lshr_b32 s92, s11, 16
; SI-NEXT: s_lshr_b32 s93, s13, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s95, s27, 16
; SI-NEXT: s_lshr_b32 s14, s25, 16
; SI-NEXT: s_lshr_b32 s88, s23, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: v_writelane_b32 v24, s40, 0
; SI-NEXT: s_lshr_b64 vcc, s[4:5], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[40:41], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB41_3
; SI-NEXT: .LBB41_2:
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; kill: killed $sgpr14
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; kill: killed $sgpr14
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: .LBB41_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: v_readlane_b32 s79, v24, 0
; SI-NEXT: v_readlane_b32 s78, v24, 1
; SI-NEXT: s_cbranch_scc1 .LBB41_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_u32 s4, s4, 3
; SI-NEXT: s_addc_u32 s5, s5, 0
; SI-NEXT: s_add_u32 s6, s6, 3
; SI-NEXT: s_addc_u32 s7, s7, 0
; SI-NEXT: s_add_u32 s8, s8, 3
; SI-NEXT: s_addc_u32 s9, s9, 0
; SI-NEXT: s_add_u32 s10, s10, 3
; SI-NEXT: s_addc_u32 s11, s11, 0
; SI-NEXT: s_add_u32 s12, s12, 3
; SI-NEXT: s_addc_u32 s13, s13, 0
; SI-NEXT: s_add_u32 s28, s28, 3
; SI-NEXT: s_addc_u32 s29, s29, 0
; SI-NEXT: s_add_u32 s26, s26, 3
; SI-NEXT: s_addc_u32 s27, s27, 0
; SI-NEXT: s_add_u32 s24, s24, 3
; SI-NEXT: s_addc_u32 s25, s25, 0
; SI-NEXT: s_add_u32 s22, s22, 3
; SI-NEXT: s_addc_u32 s23, s23, 0
; SI-NEXT: s_add_u32 s20, s20, 3
; SI-NEXT: s_addc_u32 s21, s21, 0
; SI-NEXT: s_add_u32 s18, s18, 3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
; SI-NEXT: s_lshr_b32 s15, s5, 16
; SI-NEXT: s_lshr_b32 s90, s7, 16
; SI-NEXT: s_lshr_b32 s91, s9, 16
; SI-NEXT: s_lshr_b32 s92, s11, 16
; SI-NEXT: s_lshr_b32 s93, s13, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s95, s27, 16
; SI-NEXT: s_lshr_b32 s14, s25, 16
; SI-NEXT: s_lshr_b32 s88, s23, 16
; SI-NEXT: s_lshr_b32 s78, s21, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: s_lshr_b32 s79, s17, 16
; SI-NEXT: s_lshr_b64 vcc, s[4:5], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[40:41], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: .LBB41_5: ; %end
; SI-NEXT: s_and_b32 s25, s25, 0xffff
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_or_b32 s14, s25, s14
; SI-NEXT: s_and_b32 s25, s26, 0xffff
; SI-NEXT: s_lshl_b32 s26, s60, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s27, 0xffff
; SI-NEXT: s_lshl_b32 s27, s95, 16
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s28, 0xffff
; SI-NEXT: s_lshl_b32 s28, s58, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s29, 0xffff
; SI-NEXT: s_lshl_b32 s29, s94, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_lshl_b32 s29, s56, 16
; SI-NEXT: s_lshl_b32 s41, s76, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s12, s12, s29
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s29, s93, 16
; SI-NEXT: s_or_b32 s16, s16, s41
; SI-NEXT: s_and_b32 s17, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s79, 16
; SI-NEXT: s_or_b32 s13, s13, s29
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s29, s46, 16
; SI-NEXT: s_or_b32 s17, s17, s41
; SI-NEXT: s_lshl_b32 s41, s74, 16
; SI-NEXT: s_and_b32 s18, s18, 0xffff
; SI-NEXT: s_or_b32 s10, s10, s29
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_lshl_b32 s29, s92, 16
; SI-NEXT: s_or_b32 s18, s18, s41
; SI-NEXT: s_and_b32 s19, s19, 0xffff
; SI-NEXT: s_lshl_b32 s41, s89, 16
; SI-NEXT: s_or_b32 s11, s11, s29
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_lshl_b32 s29, s44, 16
; SI-NEXT: s_or_b32 s19, s19, s41
; SI-NEXT: s_lshl_b32 s41, s72, 16
; SI-NEXT: s_and_b32 s20, s20, 0xffff
; SI-NEXT: s_or_b32 s8, s8, s29
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s29, s91, 16
; SI-NEXT: s_or_b32 s20, s20, s41
; SI-NEXT: s_and_b32 s21, s21, 0xffff
; SI-NEXT: s_lshl_b32 s41, s78, 16
; SI-NEXT: s_or_b32 s9, s9, s29
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s29, s42, 16
; SI-NEXT: s_or_b32 s21, s21, s41
; SI-NEXT: s_and_b32 s22, s22, 0xffff
; SI-NEXT: s_lshl_b32 s41, s62, 16
; SI-NEXT: s_or_b32 s6, s6, s29
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s29, s90, 16
; SI-NEXT: s_or_b32 s22, s22, s41
; SI-NEXT: s_and_b32 s23, s23, 0xffff
; SI-NEXT: s_lshl_b32 s41, s88, 16
; SI-NEXT: s_and_b32 s24, s24, 0xffff
; SI-NEXT: s_lshl_b32 s40, s40, 16
; SI-NEXT: s_or_b32 s7, s7, s29
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s29, vcc_lo, 16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_or_b32 s23, s23, s41
; SI-NEXT: s_or_b32 s24, s24, s40
; SI-NEXT: s_or_b32 s4, s4, s29
; SI-NEXT: s_or_b32 s5, s5, s15
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s14
; SI-NEXT: v_mov_b32_e32 v10, s25
; SI-NEXT: v_mov_b32_e32 v11, s26
; SI-NEXT: v_mov_b32_e32 v12, s27
; SI-NEXT: v_mov_b32_e32 v13, s28
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v15, s13
; SI-NEXT: v_mov_b32_e32 v16, s10
; SI-NEXT: v_mov_b32_e32 v17, s11
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v20, s6
; SI-NEXT: v_mov_b32_e32 v21, s7
; SI-NEXT: v_mov_b32_e32 v22, s4
; SI-NEXT: v_mov_b32_e32 v23, s5
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v48i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB41_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB41_3
; VI-NEXT: .LBB41_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB41_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB41_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
; VI-NEXT: s_add_u32 s9, s9, 3
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s11, s11, 3
; VI-NEXT: s_addc_u32 s10, s10, 0
; VI-NEXT: s_add_u32 s13, s13, 3
; VI-NEXT: s_addc_u32 s12, s12, 0
; VI-NEXT: s_add_u32 s15, s15, 3
; VI-NEXT: s_addc_u32 s14, s14, 0
; VI-NEXT: s_add_u32 s28, s28, 3
; VI-NEXT: s_addc_u32 s29, s29, 0
; VI-NEXT: s_add_u32 s26, s26, 3
; VI-NEXT: s_addc_u32 s27, s27, 0
; VI-NEXT: s_add_u32 s24, s24, 3
; VI-NEXT: s_addc_u32 s25, s25, 0
; VI-NEXT: s_add_u32 s22, s22, 3
; VI-NEXT: s_addc_u32 s23, s23, 0
; VI-NEXT: s_add_u32 s20, s20, 3
; VI-NEXT: s_addc_u32 s21, s21, 0
; VI-NEXT: s_add_u32 s18, s18, 3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: .LBB41_5: ; %end
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s16, s78, 16
; VI-NEXT: s_or_b32 s5, s5, s16
; VI-NEXT: s_and_b32 s16, 0xffff, s18
; VI-NEXT: s_lshl_b32 s17, s77, 16
; VI-NEXT: s_or_b32 s16, s16, s17
; VI-NEXT: s_and_b32 s17, 0xffff, s19
; VI-NEXT: s_lshl_b32 s18, s76, 16
; VI-NEXT: s_or_b32 s17, s17, s18
; VI-NEXT: s_and_b32 s18, 0xffff, s20
; VI-NEXT: s_lshl_b32 s19, s75, 16
; VI-NEXT: s_or_b32 s18, s18, s19
; VI-NEXT: s_and_b32 s19, 0xffff, s21
; VI-NEXT: s_lshl_b32 s20, s74, 16
; VI-NEXT: s_or_b32 s19, s19, s20
; VI-NEXT: s_and_b32 s20, 0xffff, s22
; VI-NEXT: s_lshl_b32 s21, s73, 16
; VI-NEXT: s_or_b32 s20, s20, s21
; VI-NEXT: s_and_b32 s21, 0xffff, s23
; VI-NEXT: s_lshl_b32 s22, s72, 16
; VI-NEXT: s_or_b32 s21, s21, s22
; VI-NEXT: s_and_b32 s22, 0xffff, s24
; VI-NEXT: s_lshl_b32 s23, s63, 16
; VI-NEXT: s_or_b32 s22, s22, s23
; VI-NEXT: s_and_b32 s23, 0xffff, s25
; VI-NEXT: s_lshl_b32 s24, s62, 16
; VI-NEXT: s_or_b32 s23, s23, s24
; VI-NEXT: s_and_b32 s24, 0xffff, s26
; VI-NEXT: s_lshl_b32 s25, s61, 16
; VI-NEXT: s_or_b32 s24, s24, s25
; VI-NEXT: s_and_b32 s25, 0xffff, s27
; VI-NEXT: s_lshl_b32 s26, s60, 16
; VI-NEXT: s_or_b32 s25, s25, s26
; VI-NEXT: s_and_b32 s26, 0xffff, s28
; VI-NEXT: s_lshl_b32 s27, s59, 16
; VI-NEXT: s_or_b32 s26, s26, s27
; VI-NEXT: s_and_b32 s27, 0xffff, s29
; VI-NEXT: s_lshl_b32 s28, s58, 16
; VI-NEXT: s_or_b32 s27, s27, s28
; VI-NEXT: s_and_b32 s15, 0xffff, s15
; VI-NEXT: s_lshl_b32 s28, s57, 16
; VI-NEXT: s_or_b32 s15, s15, s28
; VI-NEXT: s_and_b32 s14, 0xffff, s14
; VI-NEXT: s_lshl_b32 s28, s56, 16
; VI-NEXT: s_or_b32 s14, s14, s28
; VI-NEXT: s_and_b32 s13, 0xffff, s13
; VI-NEXT: s_lshl_b32 s28, s47, 16
; VI-NEXT: s_or_b32 s13, s13, s28
; VI-NEXT: s_and_b32 s12, 0xffff, s12
; VI-NEXT: s_lshl_b32 s28, s46, 16
; VI-NEXT: s_or_b32 s12, s12, s28
; VI-NEXT: s_and_b32 s11, 0xffff, s11
; VI-NEXT: s_lshl_b32 s28, s45, 16
; VI-NEXT: s_or_b32 s11, s11, s28
; VI-NEXT: s_and_b32 s10, 0xffff, s10
; VI-NEXT: s_lshl_b32 s28, s44, 16
; VI-NEXT: s_or_b32 s10, s10, s28
; VI-NEXT: s_and_b32 s9, 0xffff, s9
; VI-NEXT: s_lshl_b32 s28, s43, 16
; VI-NEXT: s_or_b32 s9, s9, s28
; VI-NEXT: s_and_b32 s8, 0xffff, s8
; VI-NEXT: s_lshl_b32 s28, s42, 16
; VI-NEXT: s_or_b32 s8, s8, s28
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s28, s41, 16
; VI-NEXT: s_or_b32 s7, s7, s28
; VI-NEXT: s_and_b32 s6, 0xffff, s6
; VI-NEXT: s_lshl_b32 s28, s40, 16
; VI-NEXT: s_or_b32 s6, s6, s28
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s17
; VI-NEXT: v_mov_b32_e32 v4, s18
; VI-NEXT: v_mov_b32_e32 v5, s19
; VI-NEXT: v_mov_b32_e32 v6, s20
; VI-NEXT: v_mov_b32_e32 v7, s21
; VI-NEXT: v_mov_b32_e32 v8, s22
; VI-NEXT: v_mov_b32_e32 v9, s23
; VI-NEXT: v_mov_b32_e32 v10, s24
; VI-NEXT: v_mov_b32_e32 v11, s25
; VI-NEXT: v_mov_b32_e32 v12, s26
; VI-NEXT: v_mov_b32_e32 v13, s27
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v48i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB41_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB41_3
; GFX9-NEXT: .LBB41_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB41_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB41_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
; GFX9-NEXT: s_add_u32 s9, s9, 3
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s11, s11, 3
; GFX9-NEXT: s_addc_u32 s10, s10, 0
; GFX9-NEXT: s_add_u32 s13, s13, 3
; GFX9-NEXT: s_addc_u32 s12, s12, 0
; GFX9-NEXT: s_add_u32 s15, s15, 3
; GFX9-NEXT: s_addc_u32 s14, s14, 0
; GFX9-NEXT: s_add_u32 s28, s28, 3
; GFX9-NEXT: s_addc_u32 s29, s29, 0
; GFX9-NEXT: s_add_u32 s26, s26, 3
; GFX9-NEXT: s_addc_u32 s27, s27, 0
; GFX9-NEXT: s_add_u32 s24, s24, 3
; GFX9-NEXT: s_addc_u32 s25, s25, 0
; GFX9-NEXT: s_add_u32 s22, s22, 3
; GFX9-NEXT: s_addc_u32 s23, s23, 0
; GFX9-NEXT: s_add_u32 s20, s20, 3
; GFX9-NEXT: s_addc_u32 s21, s21, 0
; GFX9-NEXT: s_add_u32 s18, s18, 3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: .LBB41_5: ; %end
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s78
; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s76
; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s74
; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s72
; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s60
; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s59
; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s58
; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s57
; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s46
; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s45
; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s44
; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s43
; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s42
; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s41
; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s40
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s17
; GFX9-NEXT: v_mov_b32_e32 v4, s18
; GFX9-NEXT: v_mov_b32_e32 v5, s19
; GFX9-NEXT: v_mov_b32_e32 v6, s20
; GFX9-NEXT: v_mov_b32_e32 v7, s21
; GFX9-NEXT: v_mov_b32_e32 v8, s22
; GFX9-NEXT: v_mov_b32_e32 v9, s23
; GFX9-NEXT: v_mov_b32_e32 v10, s24
; GFX9-NEXT: v_mov_b32_e32 v11, s25
; GFX9-NEXT: v_mov_b32_e32 v12, s26
; GFX9-NEXT: v_mov_b32_e32 v13, s27
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v48i16_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s74, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB41_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: s_branch .LBB41_3
; GFX11-NEXT: .LBB41_2:
; GFX11-NEXT: s_mov_b32 s74, -1
; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr72
; GFX11-NEXT: ; implicit-def: $sgpr63
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr61
; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr59
; GFX11-NEXT: ; implicit-def: $sgpr58
; GFX11-NEXT: ; implicit-def: $sgpr57
; GFX11-NEXT: ; implicit-def: $sgpr56
; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr46
; GFX11-NEXT: ; implicit-def: $sgpr45
; GFX11-NEXT: ; implicit-def: $sgpr44
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: ; implicit-def: $sgpr41
; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: ; implicit-def: $sgpr13
; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: ; implicit-def: $sgpr11
; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB41_3: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB41_5
; GFX11-NEXT: ; %bb.4: ; %cmp.true
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
; GFX11-NEXT: s_add_u32 s7, s7, 3
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s9, s9, 3
; GFX11-NEXT: s_addc_u32 s8, s8, 0
; GFX11-NEXT: s_add_u32 s28, s28, 3
; GFX11-NEXT: s_addc_u32 s29, s29, 0
; GFX11-NEXT: s_add_u32 s26, s26, 3
; GFX11-NEXT: s_addc_u32 s27, s27, 0
; GFX11-NEXT: s_add_u32 s24, s24, 3
; GFX11-NEXT: s_addc_u32 s25, s25, 0
; GFX11-NEXT: s_add_u32 s22, s22, 3
; GFX11-NEXT: s_addc_u32 s23, s23, 0
; GFX11-NEXT: s_add_u32 s20, s20, 3
; GFX11-NEXT: s_addc_u32 s21, s21, 0
; GFX11-NEXT: s_add_u32 s18, s18, 3
; GFX11-NEXT: s_addc_u32 s19, s19, 0
; GFX11-NEXT: s_add_u32 s16, s16, 3
; GFX11-NEXT: s_addc_u32 s17, s17, 0
; GFX11-NEXT: s_add_u32 s2, s2, 3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: .LBB41_5: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s72
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s62
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46
; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44
; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s40
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s10
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define <12 x i64> @bitcast_v48i16_to_v12i64(<48 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v12i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_or_b32_e32 v1, v1, v59
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v58
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v57
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_or_b32_e32 v7, v7, v56
; SI-NEXT: v_or_b32_e32 v8, v8, v63
; SI-NEXT: v_or_b32_e32 v9, v9, v62
; SI-NEXT: v_or_b32_e32 v10, v10, v61
; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB42_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB42_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v57, v5
; SI-NEXT: v_or_b32_e32 v6, v32, v6
; SI-NEXT: v_or_b32_e32 v7, v56, v7
; SI-NEXT: v_or_b32_e32 v8, v63, v8
; SI-NEXT: v_or_b32_e32 v9, v62, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: .LBB42_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v12i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB42_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB42_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB42_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 3
; VI-NEXT: v_add_u16_e32 v0, 3, v47
; VI-NEXT: v_add_u16_sdwa v1, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 3, v46
; VI-NEXT: v_add_u16_sdwa v2, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v45
; VI-NEXT: v_add_u16_sdwa v3, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v44
; VI-NEXT: v_add_u16_sdwa v4, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v43
; VI-NEXT: v_add_u16_sdwa v5, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v42
; VI-NEXT: v_add_u16_sdwa v6, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v41
; VI-NEXT: v_add_u16_sdwa v7, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: v_add_u16_e32 v7, 3, v40
; VI-NEXT: v_add_u16_sdwa v8, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v55
; VI-NEXT: v_add_u16_sdwa v9, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_add_u16_e32 v9, 3, v54
; VI-NEXT: v_add_u16_sdwa v10, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u16_e32 v10, 3, v53
; VI-NEXT: v_add_u16_sdwa v11, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_add_u16_e32 v11, 3, v52
; VI-NEXT: v_add_u16_sdwa v12, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u16_e32 v12, 3, v51
; VI-NEXT: v_add_u16_sdwa v13, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_add_u16_e32 v13, 3, v50
; VI-NEXT: v_add_u16_sdwa v14, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_add_u16_e32 v14, 3, v49
; VI-NEXT: v_add_u16_sdwa v15, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_add_u16_e32 v15, 3, v48
; VI-NEXT: v_add_u16_sdwa v16, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: v_add_u16_e32 v16, 3, v39
; VI-NEXT: v_add_u16_sdwa v17, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: v_add_u16_e32 v17, 3, v38
; VI-NEXT: v_add_u16_sdwa v18, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: v_add_u16_e32 v18, 3, v37
; VI-NEXT: v_add_u16_sdwa v19, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: v_add_u16_e32 v19, 3, v36
; VI-NEXT: v_add_u16_sdwa v20, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: v_add_u16_e32 v20, 3, v35
; VI-NEXT: v_add_u16_sdwa v21, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: v_add_u16_e32 v21, 3, v34
; VI-NEXT: v_add_u16_sdwa v22, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: v_add_u16_e32 v22, 3, v33
; VI-NEXT: v_add_u16_sdwa v24, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v22, v22, v24
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB42_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v12i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB42_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB42_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB42_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB42_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB42_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB42_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v12i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB42_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: .LBB42_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define inreg <12 x i64> @bitcast_v48i16_to_v12i64_scalar(<48 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v12i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v24, s36, 0
; SI-NEXT: v_writelane_b32 v24, s37, 1
; SI-NEXT: v_writelane_b32 v24, s38, 2
; SI-NEXT: v_writelane_b32 v24, s39, 3
; SI-NEXT: v_writelane_b32 v24, s48, 4
; SI-NEXT: v_writelane_b32 v24, s49, 5
; SI-NEXT: v_writelane_b32 v24, s50, 6
; SI-NEXT: v_writelane_b32 v24, s51, 7
; SI-NEXT: v_writelane_b32 v24, s52, 8
; SI-NEXT: v_writelane_b32 v24, s53, 9
; SI-NEXT: v_writelane_b32 v24, s54, 10
; SI-NEXT: v_writelane_b32 v24, s55, 11
; SI-NEXT: v_writelane_b32 v24, s64, 12
; SI-NEXT: v_writelane_b32 v24, s65, 13
; SI-NEXT: v_writelane_b32 v24, s66, 14
; SI-NEXT: v_writelane_b32 v24, s67, 15
; SI-NEXT: v_writelane_b32 v24, s30, 16
; SI-NEXT: v_writelane_b32 v24, s31, 17
; SI-NEXT: v_readfirstlane_b32 s7, v9
; SI-NEXT: v_readfirstlane_b32 s9, v8
; SI-NEXT: v_readfirstlane_b32 s11, v7
; SI-NEXT: v_readfirstlane_b32 s13, v6
; SI-NEXT: v_readfirstlane_b32 s15, v5
; SI-NEXT: v_readfirstlane_b32 s74, v4
; SI-NEXT: v_readfirstlane_b32 s77, v3
; SI-NEXT: v_readfirstlane_b32 s88, v2
; SI-NEXT: v_readfirstlane_b32 s91, v1
; SI-NEXT: v_readfirstlane_b32 s94, v0
; SI-NEXT: s_lshr_b32 s72, s29, 16
; SI-NEXT: s_lshr_b32 s75, s28, 16
; SI-NEXT: s_lshr_b32 s78, s27, 16
; SI-NEXT: s_lshr_b32 s89, s26, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s60, s21, 16
; SI-NEXT: s_lshr_b32 s61, s20, 16
; SI-NEXT: s_lshr_b32 s62, s19, 16
; SI-NEXT: s_lshr_b32 s63, s18, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_lshr_b32 s31, s16, 16
; SI-NEXT: s_lshr_b32 s6, s7, 16
; SI-NEXT: s_lshr_b32 s8, s9, 16
; SI-NEXT: s_lshr_b32 s10, s11, 16
; SI-NEXT: s_lshr_b32 s12, s13, 16
; SI-NEXT: s_lshr_b32 s14, s15, 16
; SI-NEXT: s_lshr_b32 s73, s74, 16
; SI-NEXT: s_lshr_b32 s76, s77, 16
; SI-NEXT: s_lshr_b32 s79, s88, 16
; SI-NEXT: s_lshr_b32 s90, s91, 16
; SI-NEXT: s_lshr_b32 s93, s94, 16
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_cbranch_scc0 .LBB43_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s36, s4, s5
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s37, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s91, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s77, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s15, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s13, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s11, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s9, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB43_3
; SI-NEXT: .LBB43_2:
; SI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v25, s77, 0
; SI-NEXT: v_writelane_b32 v25, s74, 1
; SI-NEXT: v_writelane_b32 v25, s15, 2
; SI-NEXT: v_writelane_b32 v25, s13, 3
; SI-NEXT: s_mov_b32 s13, s11
; SI-NEXT: s_mov_b32 s11, s9
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_mov_b32 s7, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, s95
; SI-NEXT: s_mov_b32 s95, s93
; SI-NEXT: s_mov_b32 s93, s92
; SI-NEXT: s_mov_b32 s92, s90
; SI-NEXT: s_mov_b32 s90, s89
; SI-NEXT: s_mov_b32 s89, s79
; SI-NEXT: s_mov_b32 s79, s78
; SI-NEXT: s_mov_b32 s78, s76
; SI-NEXT: s_mov_b32 s76, s75
; SI-NEXT: s_mov_b32 s75, s73
; SI-NEXT: s_mov_b32 s73, s72
; SI-NEXT: s_mov_b32 s72, s14
; SI-NEXT: s_mov_b32 s14, s12
; SI-NEXT: s_mov_b32 s12, s10
; SI-NEXT: s_mov_b32 s10, s8
; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s6, s60
; SI-NEXT: s_mov_b32 s77, s88
; SI-NEXT: s_mov_b32 s88, s61
; SI-NEXT: s_mov_b32 s74, s91
; SI-NEXT: s_mov_b32 s91, s62
; SI-NEXT: s_mov_b32 s15, s63
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_mov_b32 s63, s15
; SI-NEXT: s_mov_b32 s62, s91
; SI-NEXT: s_mov_b32 s91, s74
; SI-NEXT: s_mov_b32 s61, s88
; SI-NEXT: s_mov_b32 s88, s77
; SI-NEXT: s_mov_b32 s60, s6
; SI-NEXT: s_mov_b32 s6, s8
; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s10, s12
; SI-NEXT: s_mov_b32 s12, s14
; SI-NEXT: s_mov_b32 s14, s72
; SI-NEXT: s_mov_b32 s72, s73
; SI-NEXT: s_mov_b32 s73, s75
; SI-NEXT: s_mov_b32 s75, s76
; SI-NEXT: s_mov_b32 s76, s78
; SI-NEXT: s_mov_b32 s78, s79
; SI-NEXT: s_mov_b32 s79, s89
; SI-NEXT: s_mov_b32 s89, s90
; SI-NEXT: s_mov_b32 s90, s92
; SI-NEXT: s_mov_b32 s92, s93
; SI-NEXT: s_mov_b32 s93, s95
; SI-NEXT: s_mov_b32 s95, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, s7
; SI-NEXT: s_mov_b32 s7, s9
; SI-NEXT: s_mov_b32 s9, s11
; SI-NEXT: s_mov_b32 s11, s13
; SI-NEXT: v_readlane_b32 s13, v25, 3
; SI-NEXT: v_readlane_b32 s15, v25, 2
; SI-NEXT: v_readlane_b32 s74, v25, 1
; SI-NEXT: v_readlane_b32 s77, v25, 0
; SI-NEXT: .LBB43_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB43_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s36, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s37, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s38, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s39, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s40, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s41, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s42, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s43, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s44, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s45, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s46, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s47, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s48, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s94, s94, 3
; SI-NEXT: s_add_i32 s49, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s50, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s91, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s51, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s88, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s52, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s77, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s74, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s54, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s15, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s13, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s56, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s11, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s9, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s58, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s7, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
; SI-NEXT: .LBB43_5: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 16
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_readlane_b32 s31, v24, 17
; SI-NEXT: v_readlane_b32 s67, v24, 15
; SI-NEXT: v_readlane_b32 s66, v24, 14
; SI-NEXT: v_readlane_b32 s65, v24, 13
; SI-NEXT: v_readlane_b32 s64, v24, 12
; SI-NEXT: v_readlane_b32 s55, v24, 11
; SI-NEXT: v_readlane_b32 s54, v24, 10
; SI-NEXT: v_readlane_b32 s53, v24, 9
; SI-NEXT: v_readlane_b32 s52, v24, 8
; SI-NEXT: v_readlane_b32 s51, v24, 7
; SI-NEXT: v_readlane_b32 s50, v24, 6
; SI-NEXT: v_readlane_b32 s49, v24, 5
; SI-NEXT: v_readlane_b32 s48, v24, 4
; SI-NEXT: v_readlane_b32 s39, v24, 3
; SI-NEXT: v_readlane_b32 s38, v24, 2
; SI-NEXT: v_readlane_b32 s37, v24, 1
; SI-NEXT: v_readlane_b32 s36, v24, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v12i64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v24, s34, 0
; VI-NEXT: v_writelane_b32 v24, s35, 1
; VI-NEXT: v_writelane_b32 v24, s36, 2
; VI-NEXT: v_writelane_b32 v24, s37, 3
; VI-NEXT: v_writelane_b32 v24, s38, 4
; VI-NEXT: v_writelane_b32 v24, s39, 5
; VI-NEXT: v_writelane_b32 v24, s48, 6
; VI-NEXT: v_writelane_b32 v24, s49, 7
; VI-NEXT: v_writelane_b32 v24, s50, 8
; VI-NEXT: v_writelane_b32 v24, s51, 9
; VI-NEXT: v_writelane_b32 v24, s52, 10
; VI-NEXT: v_writelane_b32 v24, s53, 11
; VI-NEXT: v_writelane_b32 v24, s54, 12
; VI-NEXT: v_writelane_b32 v24, s55, 13
; VI-NEXT: v_writelane_b32 v24, s64, 14
; VI-NEXT: v_writelane_b32 v24, s65, 15
; VI-NEXT: v_writelane_b32 v24, s66, 16
; VI-NEXT: v_writelane_b32 v24, s67, 17
; VI-NEXT: v_writelane_b32 v24, s30, 18
; VI-NEXT: v_writelane_b32 v24, s31, 19
; VI-NEXT: v_readfirstlane_b32 s7, v9
; VI-NEXT: v_readfirstlane_b32 s9, v8
; VI-NEXT: v_readfirstlane_b32 s11, v7
; VI-NEXT: v_readfirstlane_b32 s13, v6
; VI-NEXT: v_readfirstlane_b32 s15, v5
; VI-NEXT: v_readfirstlane_b32 s74, v4
; VI-NEXT: v_readfirstlane_b32 s77, v3
; VI-NEXT: v_readfirstlane_b32 s88, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s60, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s75, s28, 16
; VI-NEXT: s_lshr_b32 s78, s27, 16
; VI-NEXT: s_lshr_b32 s89, s26, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s25, 16
; VI-NEXT: s_lshr_b32 s61, s24, 16
; VI-NEXT: s_lshr_b32 s62, s23, 16
; VI-NEXT: s_lshr_b32 s63, s22, 16
; VI-NEXT: s_lshr_b32 s30, s21, 16
; VI-NEXT: s_lshr_b32 s31, s20, 16
; VI-NEXT: s_lshr_b32 s34, s19, 16
; VI-NEXT: s_lshr_b32 s35, s18, 16
; VI-NEXT: s_lshr_b32 s64, s17, 16
; VI-NEXT: s_lshr_b32 s65, s16, 16
; VI-NEXT: s_lshr_b32 s6, s7, 16
; VI-NEXT: s_lshr_b32 s8, s9, 16
; VI-NEXT: s_lshr_b32 s10, s11, 16
; VI-NEXT: s_lshr_b32 s12, s13, 16
; VI-NEXT: s_lshr_b32 s14, s15, 16
; VI-NEXT: s_lshr_b32 s73, s74, 16
; VI-NEXT: s_lshr_b32 s76, s77, 16
; VI-NEXT: s_lshr_b32 s79, s88, 16
; VI-NEXT: s_lshr_b32 s90, s91, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s60, 16
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: s_cbranch_scc0 .LBB43_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s17
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s60
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s88
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s15
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s13
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s9
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB43_3
; VI-NEXT: .LBB43_2:
; VI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: v_writelane_b32 v25, s77, 0
; VI-NEXT: v_writelane_b32 v25, s74, 1
; VI-NEXT: v_writelane_b32 v25, s15, 2
; VI-NEXT: v_writelane_b32 v25, s13, 3
; VI-NEXT: v_writelane_b32 v25, s11, 4
; VI-NEXT: v_writelane_b32 v25, s9, 5
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_mov_b32 s7, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, s90
; VI-NEXT: s_mov_b32 s90, s89
; VI-NEXT: s_mov_b32 s89, s79
; VI-NEXT: s_mov_b32 s79, s78
; VI-NEXT: s_mov_b32 s78, s76
; VI-NEXT: s_mov_b32 s76, s75
; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s12
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s8
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s6, s60
; VI-NEXT: s_mov_b32 s77, s61
; VI-NEXT: s_mov_b32 s74, s88
; VI-NEXT: s_mov_b32 s88, s62
; VI-NEXT: s_mov_b32 s11, s63
; VI-NEXT: s_mov_b32 s15, s91
; VI-NEXT: s_mov_b32 s91, s64
; VI-NEXT: s_mov_b32 s13, s65
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_mov_b32 s65, s13
; VI-NEXT: s_mov_b32 s64, s91
; VI-NEXT: s_mov_b32 s91, s15
; VI-NEXT: s_mov_b32 s63, s11
; VI-NEXT: s_mov_b32 s62, s88
; VI-NEXT: s_mov_b32 s88, s74
; VI-NEXT: s_mov_b32 s61, s77
; VI-NEXT: s_mov_b32 s60, s6
; VI-NEXT: s_mov_b32 s6, s8
; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s12, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s73
; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s76
; VI-NEXT: s_mov_b32 s76, s78
; VI-NEXT: s_mov_b32 s78, s79
; VI-NEXT: s_mov_b32 s79, s89
; VI-NEXT: s_mov_b32 s89, s90
; VI-NEXT: s_mov_b32 s90, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, s7
; VI-NEXT: s_mov_b32 s7, s9
; VI-NEXT: v_readlane_b32 s9, v25, 5
; VI-NEXT: v_readlane_b32 s11, v25, 4
; VI-NEXT: v_readlane_b32 s13, v25, 3
; VI-NEXT: v_readlane_b32 s15, v25, 2
; VI-NEXT: v_readlane_b32 s74, v25, 1
; VI-NEXT: v_readlane_b32 s77, v25, 0
; VI-NEXT: .LBB43_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB43_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s17, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s22, 0xffff
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s42, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s23, 0xffff
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s43, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s24, 0xffff
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s44, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s25, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s45, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s26, 0xffff
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s46, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s27, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s47, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s28, 0xffff
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s48, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s29, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s49, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s60, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s50, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s91, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s51, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s88, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s52, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s77, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s74, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s54, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s15, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s13, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s11, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s9, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s58, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s7, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: .LBB43_5: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_readlane_b32 s31, v24, 19
; VI-NEXT: v_readlane_b32 s67, v24, 17
; VI-NEXT: v_readlane_b32 s66, v24, 16
; VI-NEXT: v_readlane_b32 s65, v24, 15
; VI-NEXT: v_readlane_b32 s64, v24, 14
; VI-NEXT: v_readlane_b32 s55, v24, 13
; VI-NEXT: v_readlane_b32 s54, v24, 12
; VI-NEXT: v_readlane_b32 s53, v24, 11
; VI-NEXT: v_readlane_b32 s52, v24, 10
; VI-NEXT: v_readlane_b32 s51, v24, 9
; VI-NEXT: v_readlane_b32 s50, v24, 8
; VI-NEXT: v_readlane_b32 s49, v24, 7
; VI-NEXT: v_readlane_b32 s48, v24, 6
; VI-NEXT: v_readlane_b32 s39, v24, 5
; VI-NEXT: v_readlane_b32 s38, v24, 4
; VI-NEXT: v_readlane_b32 s37, v24, 3
; VI-NEXT: v_readlane_b32 s36, v24, 2
; VI-NEXT: v_readlane_b32 s35, v24, 1
; VI-NEXT: v_readlane_b32 s34, v24, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v12i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB43_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB43_3
; GFX9-NEXT: .LBB43_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB43_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB43_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v0, s36, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s37, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, s38, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, s39, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, s40, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, s41, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, s42, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, s43, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, s44, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, s45, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, s46, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, s47, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, s48, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, s49, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, s50, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB43_6
; GFX9-NEXT: .LBB43_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB43_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48i16_to_v12i64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB43_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB43_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB43_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define <48 x half> @bitcast_v12i64_to_v48f16(<12 x i64> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v48f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB44_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v32, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v35, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB44_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB44_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v32, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v35, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v38, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v49, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB44_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v49
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v38
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v35
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v39
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v36
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v33
; SI-NEXT: v_or_b32_e32 v1, v1, v49
; SI-NEXT: v_or_b32_e32 v3, v3, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v35
; SI-NEXT: v_or_b32_e32 v7, v7, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v48f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB44_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB44_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB44_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v22, vcc, 3, v22
; VI-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc
; VI-NEXT: v_add_u32_e32 v20, vcc, 3, v20
; VI-NEXT: v_addc_u32_e32 v21, vcc, 0, v21, vcc
; VI-NEXT: v_add_u32_e32 v18, vcc, 3, v18
; VI-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
; VI-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB44_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v48f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB44_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB44_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB44_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_co_u32_e32 v22, vcc, 3, v22
; GFX9-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v23, vcc
; GFX9-NEXT: v_add_co_u32_e32 v20, vcc, 3, v20
; GFX9-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
; GFX9-NEXT: v_add_co_u32_e32 v18, vcc, 3, v18
; GFX9-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc
; GFX9-NEXT: v_add_co_u32_e32 v16, vcc, 3, v16
; GFX9-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB44_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v12i64_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB44_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-TRUE16-NEXT: .LBB44_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12i64_to_v48f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB44_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB44_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB44_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_co_u32 v22, vcc_lo, v22, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v23, null, 0, v23, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v20, vcc_lo, v20, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v21, null, 0, v21, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v18, vcc_lo, v18, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v19, null, 0, v19, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v16, vcc_lo, v16, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v17, null, 0, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
; GFX11-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB44_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define inreg <48 x half> @bitcast_v12i64_to_v48f16_scalar(<12 x i64> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12i64_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: v_readfirstlane_b32 s12, v10
; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_readfirstlane_b32 s4, v8
; SI-NEXT: v_readfirstlane_b32 s7, v7
; SI-NEXT: v_readfirstlane_b32 s6, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s11, v3
; SI-NEXT: v_readfirstlane_b32 s10, v2
; SI-NEXT: v_readfirstlane_b32 s13, v1
; SI-NEXT: s_cmp_lg_u32 s12, 0
; SI-NEXT: v_readfirstlane_b32 s12, v0
; SI-NEXT: ; implicit-def: $vgpr24 : SGPR spill to VGPR lane
; SI-NEXT: s_cbranch_scc0 .LBB45_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s21, 16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v24, s40, 1
; SI-NEXT: s_lshr_b32 s40, s17, 16
; SI-NEXT: s_lshr_b32 s15, s5, 16
; SI-NEXT: s_lshr_b32 s90, s7, 16
; SI-NEXT: s_lshr_b32 s91, s9, 16
; SI-NEXT: s_lshr_b32 s92, s11, 16
; SI-NEXT: s_lshr_b32 s93, s13, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s95, s27, 16
; SI-NEXT: s_lshr_b32 s14, s25, 16
; SI-NEXT: s_lshr_b32 s88, s23, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: v_writelane_b32 v24, s40, 0
; SI-NEXT: s_lshr_b64 vcc, s[4:5], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[40:41], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB45_3
; SI-NEXT: .LBB45_2:
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; kill: killed $sgpr14
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; kill: killed $sgpr14
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: .LBB45_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: v_readlane_b32 s79, v24, 0
; SI-NEXT: v_readlane_b32 s78, v24, 1
; SI-NEXT: s_cbranch_scc1 .LBB45_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_u32 s4, s4, 3
; SI-NEXT: s_addc_u32 s5, s5, 0
; SI-NEXT: s_add_u32 s6, s6, 3
; SI-NEXT: s_addc_u32 s7, s7, 0
; SI-NEXT: s_add_u32 s8, s8, 3
; SI-NEXT: s_addc_u32 s9, s9, 0
; SI-NEXT: s_add_u32 s10, s10, 3
; SI-NEXT: s_addc_u32 s11, s11, 0
; SI-NEXT: s_add_u32 s12, s12, 3
; SI-NEXT: s_addc_u32 s13, s13, 0
; SI-NEXT: s_add_u32 s28, s28, 3
; SI-NEXT: s_addc_u32 s29, s29, 0
; SI-NEXT: s_add_u32 s26, s26, 3
; SI-NEXT: s_addc_u32 s27, s27, 0
; SI-NEXT: s_add_u32 s24, s24, 3
; SI-NEXT: s_addc_u32 s25, s25, 0
; SI-NEXT: s_add_u32 s22, s22, 3
; SI-NEXT: s_addc_u32 s23, s23, 0
; SI-NEXT: s_add_u32 s20, s20, 3
; SI-NEXT: s_addc_u32 s21, s21, 0
; SI-NEXT: s_add_u32 s18, s18, 3
; SI-NEXT: s_addc_u32 s19, s19, 0
; SI-NEXT: s_add_u32 s16, s16, 3
; SI-NEXT: s_addc_u32 s17, s17, 0
; SI-NEXT: s_lshr_b32 s15, s5, 16
; SI-NEXT: s_lshr_b32 s90, s7, 16
; SI-NEXT: s_lshr_b32 s91, s9, 16
; SI-NEXT: s_lshr_b32 s92, s11, 16
; SI-NEXT: s_lshr_b32 s93, s13, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s95, s27, 16
; SI-NEXT: s_lshr_b32 s14, s25, 16
; SI-NEXT: s_lshr_b32 s88, s23, 16
; SI-NEXT: s_lshr_b32 s78, s21, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: s_lshr_b32 s79, s17, 16
; SI-NEXT: s_lshr_b64 vcc, s[4:5], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[40:41], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: .LBB45_5: ; %end
; SI-NEXT: s_and_b32 s25, s25, 0xffff
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_or_b32 s14, s25, s14
; SI-NEXT: s_and_b32 s25, s26, 0xffff
; SI-NEXT: s_lshl_b32 s26, s60, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s27, 0xffff
; SI-NEXT: s_lshl_b32 s27, s95, 16
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s28, 0xffff
; SI-NEXT: s_lshl_b32 s28, s58, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: s_and_b32 s28, s29, 0xffff
; SI-NEXT: s_lshl_b32 s29, s94, 16
; SI-NEXT: s_or_b32 s28, s28, s29
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_lshl_b32 s29, s56, 16
; SI-NEXT: s_lshl_b32 s41, s76, 16
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_or_b32 s12, s12, s29
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s29, s93, 16
; SI-NEXT: s_or_b32 s16, s16, s41
; SI-NEXT: s_and_b32 s17, s17, 0xffff
; SI-NEXT: s_lshl_b32 s41, s79, 16
; SI-NEXT: s_or_b32 s13, s13, s29
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s29, s46, 16
; SI-NEXT: s_or_b32 s17, s17, s41
; SI-NEXT: s_lshl_b32 s41, s74, 16
; SI-NEXT: s_and_b32 s18, s18, 0xffff
; SI-NEXT: s_or_b32 s10, s10, s29
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_lshl_b32 s29, s92, 16
; SI-NEXT: s_or_b32 s18, s18, s41
; SI-NEXT: s_and_b32 s19, s19, 0xffff
; SI-NEXT: s_lshl_b32 s41, s89, 16
; SI-NEXT: s_or_b32 s11, s11, s29
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_lshl_b32 s29, s44, 16
; SI-NEXT: s_or_b32 s19, s19, s41
; SI-NEXT: s_lshl_b32 s41, s72, 16
; SI-NEXT: s_and_b32 s20, s20, 0xffff
; SI-NEXT: s_or_b32 s8, s8, s29
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s29, s91, 16
; SI-NEXT: s_or_b32 s20, s20, s41
; SI-NEXT: s_and_b32 s21, s21, 0xffff
; SI-NEXT: s_lshl_b32 s41, s78, 16
; SI-NEXT: s_or_b32 s9, s9, s29
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s29, s42, 16
; SI-NEXT: s_or_b32 s21, s21, s41
; SI-NEXT: s_and_b32 s22, s22, 0xffff
; SI-NEXT: s_lshl_b32 s41, s62, 16
; SI-NEXT: s_or_b32 s6, s6, s29
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s29, s90, 16
; SI-NEXT: s_or_b32 s22, s22, s41
; SI-NEXT: s_and_b32 s23, s23, 0xffff
; SI-NEXT: s_lshl_b32 s41, s88, 16
; SI-NEXT: s_and_b32 s24, s24, 0xffff
; SI-NEXT: s_lshl_b32 s40, s40, 16
; SI-NEXT: s_or_b32 s7, s7, s29
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s29, vcc_lo, 16
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s15, s15, 16
; SI-NEXT: s_or_b32 s23, s23, s41
; SI-NEXT: s_or_b32 s24, s24, s40
; SI-NEXT: s_or_b32 s4, s4, s29
; SI-NEXT: s_or_b32 s5, s5, s15
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s14
; SI-NEXT: v_mov_b32_e32 v10, s25
; SI-NEXT: v_mov_b32_e32 v11, s26
; SI-NEXT: v_mov_b32_e32 v12, s27
; SI-NEXT: v_mov_b32_e32 v13, s28
; SI-NEXT: v_mov_b32_e32 v14, s12
; SI-NEXT: v_mov_b32_e32 v15, s13
; SI-NEXT: v_mov_b32_e32 v16, s10
; SI-NEXT: v_mov_b32_e32 v17, s11
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v20, s6
; SI-NEXT: v_mov_b32_e32 v21, s7
; SI-NEXT: v_mov_b32_e32 v22, s4
; SI-NEXT: v_mov_b32_e32 v23, s5
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12i64_to_v48f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s7, v8
; VI-NEXT: v_readfirstlane_b32 s8, v7
; VI-NEXT: v_readfirstlane_b32 s9, v6
; VI-NEXT: v_readfirstlane_b32 s10, v5
; VI-NEXT: v_readfirstlane_b32 s11, v4
; VI-NEXT: v_readfirstlane_b32 s12, v3
; VI-NEXT: v_readfirstlane_b32 s13, v2
; VI-NEXT: v_readfirstlane_b32 s14, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s15, v0
; VI-NEXT: s_cbranch_scc0 .LBB45_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB45_3
; VI-NEXT: .LBB45_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB45_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB45_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_u32 s7, s7, 3
; VI-NEXT: s_addc_u32 s6, s6, 0
; VI-NEXT: s_add_u32 s9, s9, 3
; VI-NEXT: s_addc_u32 s8, s8, 0
; VI-NEXT: s_add_u32 s11, s11, 3
; VI-NEXT: s_addc_u32 s10, s10, 0
; VI-NEXT: s_add_u32 s13, s13, 3
; VI-NEXT: s_addc_u32 s12, s12, 0
; VI-NEXT: s_add_u32 s15, s15, 3
; VI-NEXT: s_addc_u32 s14, s14, 0
; VI-NEXT: s_add_u32 s28, s28, 3
; VI-NEXT: s_addc_u32 s29, s29, 0
; VI-NEXT: s_add_u32 s26, s26, 3
; VI-NEXT: s_addc_u32 s27, s27, 0
; VI-NEXT: s_add_u32 s24, s24, 3
; VI-NEXT: s_addc_u32 s25, s25, 0
; VI-NEXT: s_add_u32 s22, s22, 3
; VI-NEXT: s_addc_u32 s23, s23, 0
; VI-NEXT: s_add_u32 s20, s20, 3
; VI-NEXT: s_addc_u32 s21, s21, 0
; VI-NEXT: s_add_u32 s18, s18, 3
; VI-NEXT: s_addc_u32 s19, s19, 0
; VI-NEXT: s_add_u32 s16, s16, 3
; VI-NEXT: s_addc_u32 s17, s17, 0
; VI-NEXT: s_lshr_b32 s40, s6, 16
; VI-NEXT: s_lshr_b32 s41, s7, 16
; VI-NEXT: s_lshr_b32 s42, s8, 16
; VI-NEXT: s_lshr_b32 s43, s9, 16
; VI-NEXT: s_lshr_b32 s44, s10, 16
; VI-NEXT: s_lshr_b32 s45, s11, 16
; VI-NEXT: s_lshr_b32 s46, s12, 16
; VI-NEXT: s_lshr_b32 s47, s13, 16
; VI-NEXT: s_lshr_b32 s56, s14, 16
; VI-NEXT: s_lshr_b32 s57, s15, 16
; VI-NEXT: s_lshr_b32 s58, s29, 16
; VI-NEXT: s_lshr_b32 s59, s28, 16
; VI-NEXT: s_lshr_b32 s60, s27, 16
; VI-NEXT: s_lshr_b32 s61, s26, 16
; VI-NEXT: s_lshr_b32 s62, s25, 16
; VI-NEXT: s_lshr_b32 s63, s24, 16
; VI-NEXT: s_lshr_b32 s72, s23, 16
; VI-NEXT: s_lshr_b32 s73, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: .LBB45_5: ; %end
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s16, s78, 16
; VI-NEXT: s_or_b32 s5, s5, s16
; VI-NEXT: s_and_b32 s16, 0xffff, s18
; VI-NEXT: s_lshl_b32 s17, s77, 16
; VI-NEXT: s_or_b32 s16, s16, s17
; VI-NEXT: s_and_b32 s17, 0xffff, s19
; VI-NEXT: s_lshl_b32 s18, s76, 16
; VI-NEXT: s_or_b32 s17, s17, s18
; VI-NEXT: s_and_b32 s18, 0xffff, s20
; VI-NEXT: s_lshl_b32 s19, s75, 16
; VI-NEXT: s_or_b32 s18, s18, s19
; VI-NEXT: s_and_b32 s19, 0xffff, s21
; VI-NEXT: s_lshl_b32 s20, s74, 16
; VI-NEXT: s_or_b32 s19, s19, s20
; VI-NEXT: s_and_b32 s20, 0xffff, s22
; VI-NEXT: s_lshl_b32 s21, s73, 16
; VI-NEXT: s_or_b32 s20, s20, s21
; VI-NEXT: s_and_b32 s21, 0xffff, s23
; VI-NEXT: s_lshl_b32 s22, s72, 16
; VI-NEXT: s_or_b32 s21, s21, s22
; VI-NEXT: s_and_b32 s22, 0xffff, s24
; VI-NEXT: s_lshl_b32 s23, s63, 16
; VI-NEXT: s_or_b32 s22, s22, s23
; VI-NEXT: s_and_b32 s23, 0xffff, s25
; VI-NEXT: s_lshl_b32 s24, s62, 16
; VI-NEXT: s_or_b32 s23, s23, s24
; VI-NEXT: s_and_b32 s24, 0xffff, s26
; VI-NEXT: s_lshl_b32 s25, s61, 16
; VI-NEXT: s_or_b32 s24, s24, s25
; VI-NEXT: s_and_b32 s25, 0xffff, s27
; VI-NEXT: s_lshl_b32 s26, s60, 16
; VI-NEXT: s_or_b32 s25, s25, s26
; VI-NEXT: s_and_b32 s26, 0xffff, s28
; VI-NEXT: s_lshl_b32 s27, s59, 16
; VI-NEXT: s_or_b32 s26, s26, s27
; VI-NEXT: s_and_b32 s27, 0xffff, s29
; VI-NEXT: s_lshl_b32 s28, s58, 16
; VI-NEXT: s_or_b32 s27, s27, s28
; VI-NEXT: s_and_b32 s15, 0xffff, s15
; VI-NEXT: s_lshl_b32 s28, s57, 16
; VI-NEXT: s_or_b32 s15, s15, s28
; VI-NEXT: s_and_b32 s14, 0xffff, s14
; VI-NEXT: s_lshl_b32 s28, s56, 16
; VI-NEXT: s_or_b32 s14, s14, s28
; VI-NEXT: s_and_b32 s13, 0xffff, s13
; VI-NEXT: s_lshl_b32 s28, s47, 16
; VI-NEXT: s_or_b32 s13, s13, s28
; VI-NEXT: s_and_b32 s12, 0xffff, s12
; VI-NEXT: s_lshl_b32 s28, s46, 16
; VI-NEXT: s_or_b32 s12, s12, s28
; VI-NEXT: s_and_b32 s11, 0xffff, s11
; VI-NEXT: s_lshl_b32 s28, s45, 16
; VI-NEXT: s_or_b32 s11, s11, s28
; VI-NEXT: s_and_b32 s10, 0xffff, s10
; VI-NEXT: s_lshl_b32 s28, s44, 16
; VI-NEXT: s_or_b32 s10, s10, s28
; VI-NEXT: s_and_b32 s9, 0xffff, s9
; VI-NEXT: s_lshl_b32 s28, s43, 16
; VI-NEXT: s_or_b32 s9, s9, s28
; VI-NEXT: s_and_b32 s8, 0xffff, s8
; VI-NEXT: s_lshl_b32 s28, s42, 16
; VI-NEXT: s_or_b32 s8, s8, s28
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s28, s41, 16
; VI-NEXT: s_or_b32 s7, s7, s28
; VI-NEXT: s_and_b32 s6, 0xffff, s6
; VI-NEXT: s_lshl_b32 s28, s40, 16
; VI-NEXT: s_or_b32 s6, s6, s28
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s17
; VI-NEXT: v_mov_b32_e32 v4, s18
; VI-NEXT: v_mov_b32_e32 v5, s19
; VI-NEXT: v_mov_b32_e32 v6, s20
; VI-NEXT: v_mov_b32_e32 v7, s21
; VI-NEXT: v_mov_b32_e32 v8, s22
; VI-NEXT: v_mov_b32_e32 v9, s23
; VI-NEXT: v_mov_b32_e32 v10, s24
; VI-NEXT: v_mov_b32_e32 v11, s25
; VI-NEXT: v_mov_b32_e32 v12, s26
; VI-NEXT: v_mov_b32_e32 v13, s27
; VI-NEXT: v_mov_b32_e32 v14, s15
; VI-NEXT: v_mov_b32_e32 v15, s14
; VI-NEXT: v_mov_b32_e32 v16, s13
; VI-NEXT: v_mov_b32_e32 v17, s12
; VI-NEXT: v_mov_b32_e32 v18, s11
; VI-NEXT: v_mov_b32_e32 v19, s10
; VI-NEXT: v_mov_b32_e32 v20, s9
; VI-NEXT: v_mov_b32_e32 v21, s8
; VI-NEXT: v_mov_b32_e32 v22, s7
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12i64_to_v48f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s6, v9
; GFX9-NEXT: v_readfirstlane_b32 s7, v8
; GFX9-NEXT: v_readfirstlane_b32 s8, v7
; GFX9-NEXT: v_readfirstlane_b32 s9, v6
; GFX9-NEXT: v_readfirstlane_b32 s10, v5
; GFX9-NEXT: v_readfirstlane_b32 s11, v4
; GFX9-NEXT: v_readfirstlane_b32 s12, v3
; GFX9-NEXT: v_readfirstlane_b32 s13, v2
; GFX9-NEXT: v_readfirstlane_b32 s14, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s15, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB45_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB45_3
; GFX9-NEXT: .LBB45_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB45_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB45_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_u32 s7, s7, 3
; GFX9-NEXT: s_addc_u32 s6, s6, 0
; GFX9-NEXT: s_add_u32 s9, s9, 3
; GFX9-NEXT: s_addc_u32 s8, s8, 0
; GFX9-NEXT: s_add_u32 s11, s11, 3
; GFX9-NEXT: s_addc_u32 s10, s10, 0
; GFX9-NEXT: s_add_u32 s13, s13, 3
; GFX9-NEXT: s_addc_u32 s12, s12, 0
; GFX9-NEXT: s_add_u32 s15, s15, 3
; GFX9-NEXT: s_addc_u32 s14, s14, 0
; GFX9-NEXT: s_add_u32 s28, s28, 3
; GFX9-NEXT: s_addc_u32 s29, s29, 0
; GFX9-NEXT: s_add_u32 s26, s26, 3
; GFX9-NEXT: s_addc_u32 s27, s27, 0
; GFX9-NEXT: s_add_u32 s24, s24, 3
; GFX9-NEXT: s_addc_u32 s25, s25, 0
; GFX9-NEXT: s_add_u32 s22, s22, 3
; GFX9-NEXT: s_addc_u32 s23, s23, 0
; GFX9-NEXT: s_add_u32 s20, s20, 3
; GFX9-NEXT: s_addc_u32 s21, s21, 0
; GFX9-NEXT: s_add_u32 s18, s18, 3
; GFX9-NEXT: s_addc_u32 s19, s19, 0
; GFX9-NEXT: s_add_u32 s16, s16, 3
; GFX9-NEXT: s_addc_u32 s17, s17, 0
; GFX9-NEXT: s_lshr_b32 s40, s6, 16
; GFX9-NEXT: s_lshr_b32 s41, s7, 16
; GFX9-NEXT: s_lshr_b32 s42, s8, 16
; GFX9-NEXT: s_lshr_b32 s43, s9, 16
; GFX9-NEXT: s_lshr_b32 s44, s10, 16
; GFX9-NEXT: s_lshr_b32 s45, s11, 16
; GFX9-NEXT: s_lshr_b32 s46, s12, 16
; GFX9-NEXT: s_lshr_b32 s47, s13, 16
; GFX9-NEXT: s_lshr_b32 s56, s14, 16
; GFX9-NEXT: s_lshr_b32 s57, s15, 16
; GFX9-NEXT: s_lshr_b32 s58, s29, 16
; GFX9-NEXT: s_lshr_b32 s59, s28, 16
; GFX9-NEXT: s_lshr_b32 s60, s27, 16
; GFX9-NEXT: s_lshr_b32 s61, s26, 16
; GFX9-NEXT: s_lshr_b32 s62, s25, 16
; GFX9-NEXT: s_lshr_b32 s63, s24, 16
; GFX9-NEXT: s_lshr_b32 s72, s23, 16
; GFX9-NEXT: s_lshr_b32 s73, s22, 16
; GFX9-NEXT: s_lshr_b32 s74, s21, 16
; GFX9-NEXT: s_lshr_b32 s75, s20, 16
; GFX9-NEXT: s_lshr_b32 s76, s19, 16
; GFX9-NEXT: s_lshr_b32 s77, s18, 16
; GFX9-NEXT: s_lshr_b32 s78, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: .LBB45_5: ; %end
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s78
; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s76
; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s74
; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s72
; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s60
; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s59
; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s58
; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s57
; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s56
; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s47
; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s46
; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s45
; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s44
; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s43
; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s42
; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s41
; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s40
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s17
; GFX9-NEXT: v_mov_b32_e32 v4, s18
; GFX9-NEXT: v_mov_b32_e32 v5, s19
; GFX9-NEXT: v_mov_b32_e32 v6, s20
; GFX9-NEXT: v_mov_b32_e32 v7, s21
; GFX9-NEXT: v_mov_b32_e32 v8, s22
; GFX9-NEXT: v_mov_b32_e32 v9, s23
; GFX9-NEXT: v_mov_b32_e32 v10, s24
; GFX9-NEXT: v_mov_b32_e32 v11, s25
; GFX9-NEXT: v_mov_b32_e32 v12, s26
; GFX9-NEXT: v_mov_b32_e32 v13, s27
; GFX9-NEXT: v_mov_b32_e32 v14, s15
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s13
; GFX9-NEXT: v_mov_b32_e32 v17, s12
; GFX9-NEXT: v_mov_b32_e32 v18, s11
; GFX9-NEXT: v_mov_b32_e32 v19, s10
; GFX9-NEXT: v_mov_b32_e32 v20, s9
; GFX9-NEXT: v_mov_b32_e32 v21, s8
; GFX9-NEXT: v_mov_b32_e32 v22, s7
; GFX9-NEXT: v_mov_b32_e32 v23, s6
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v12i64_to_v48f16_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-NEXT: v_readfirstlane_b32 s4, v5
; GFX11-NEXT: v_readfirstlane_b32 s5, v4
; GFX11-NEXT: v_readfirstlane_b32 s6, v3
; GFX11-NEXT: v_readfirstlane_b32 s7, v2
; GFX11-NEXT: v_readfirstlane_b32 s8, v1
; GFX11-NEXT: v_readfirstlane_b32 s9, v0
; GFX11-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-NEXT: s_mov_b32 s74, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB45_2
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: s_branch .LBB45_3
; GFX11-NEXT: .LBB45_2:
; GFX11-NEXT: s_mov_b32 s74, -1
; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr72
; GFX11-NEXT: ; implicit-def: $sgpr63
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr61
; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr59
; GFX11-NEXT: ; implicit-def: $sgpr58
; GFX11-NEXT: ; implicit-def: $sgpr57
; GFX11-NEXT: ; implicit-def: $sgpr56
; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr46
; GFX11-NEXT: ; implicit-def: $sgpr45
; GFX11-NEXT: ; implicit-def: $sgpr44
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: ; implicit-def: $sgpr41
; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: ; implicit-def: $sgpr13
; GFX11-NEXT: ; implicit-def: $sgpr12
; GFX11-NEXT: ; implicit-def: $sgpr11
; GFX11-NEXT: ; implicit-def: $sgpr10
; GFX11-NEXT: .LBB45_3: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB45_5
; GFX11-NEXT: ; %bb.4: ; %cmp.true
; GFX11-NEXT: s_add_u32 s5, s5, 3
; GFX11-NEXT: s_addc_u32 s4, s4, 0
; GFX11-NEXT: s_add_u32 s7, s7, 3
; GFX11-NEXT: s_addc_u32 s6, s6, 0
; GFX11-NEXT: s_add_u32 s9, s9, 3
; GFX11-NEXT: s_addc_u32 s8, s8, 0
; GFX11-NEXT: s_add_u32 s28, s28, 3
; GFX11-NEXT: s_addc_u32 s29, s29, 0
; GFX11-NEXT: s_add_u32 s26, s26, 3
; GFX11-NEXT: s_addc_u32 s27, s27, 0
; GFX11-NEXT: s_add_u32 s24, s24, 3
; GFX11-NEXT: s_addc_u32 s25, s25, 0
; GFX11-NEXT: s_add_u32 s22, s22, 3
; GFX11-NEXT: s_addc_u32 s23, s23, 0
; GFX11-NEXT: s_add_u32 s20, s20, 3
; GFX11-NEXT: s_addc_u32 s21, s21, 0
; GFX11-NEXT: s_add_u32 s18, s18, 3
; GFX11-NEXT: s_addc_u32 s19, s19, 0
; GFX11-NEXT: s_add_u32 s16, s16, 3
; GFX11-NEXT: s_addc_u32 s17, s17, 0
; GFX11-NEXT: s_add_u32 s2, s2, 3
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_add_u32 s0, s0, 3
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_lshr_b32 s10, s4, 16
; GFX11-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-NEXT: s_lshr_b32 s12, s6, 16
; GFX11-NEXT: s_lshr_b32 s13, s7, 16
; GFX11-NEXT: s_lshr_b32 s14, s8, 16
; GFX11-NEXT: s_lshr_b32 s15, s9, 16
; GFX11-NEXT: s_lshr_b32 s40, s29, 16
; GFX11-NEXT: s_lshr_b32 s41, s28, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b32 s43, s26, 16
; GFX11-NEXT: s_lshr_b32 s44, s25, 16
; GFX11-NEXT: s_lshr_b32 s45, s24, 16
; GFX11-NEXT: s_lshr_b32 s46, s23, 16
; GFX11-NEXT: s_lshr_b32 s47, s22, 16
; GFX11-NEXT: s_lshr_b32 s56, s21, 16
; GFX11-NEXT: s_lshr_b32 s57, s20, 16
; GFX11-NEXT: s_lshr_b32 s58, s19, 16
; GFX11-NEXT: s_lshr_b32 s59, s18, 16
; GFX11-NEXT: s_lshr_b32 s60, s17, 16
; GFX11-NEXT: s_lshr_b32 s61, s16, 16
; GFX11-NEXT: s_lshr_b32 s62, s3, 16
; GFX11-NEXT: s_lshr_b32 s63, s2, 16
; GFX11-NEXT: s_lshr_b32 s72, s1, 16
; GFX11-NEXT: s_lshr_b32 s73, s0, 16
; GFX11-NEXT: .LBB45_5: ; %end
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s72
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s62
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46
; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44
; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s40
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s10
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-NEXT: v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v19, s8
; GFX11-NEXT: v_dual_mov_b32 v20, s7 :: v_dual_mov_b32 v21, s6
; GFX11-NEXT: v_dual_mov_b32 v22, s5 :: v_dual_mov_b32 v23, s4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <12 x i64> %a, splat (i64 3)
%a2 = bitcast <12 x i64> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <12 x i64> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define <12 x i64> @bitcast_v48f16_to_v12i64(<48 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v12i64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB46_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v58
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v33
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v57
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB46_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB46_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v59
; SI-NEXT: v_cvt_f32_f16_e32 v2, v35
; SI-NEXT: v_cvt_f32_f16_e32 v1, v47
; SI-NEXT: v_cvt_f32_f16_e32 v3, v46
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_or_b32_e32 v1, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, v34
; SI-NEXT: v_cvt_f32_f16_e32 v3, v45
; SI-NEXT: v_cvt_f32_f16_e32 v4, v44
; SI-NEXT: v_cvt_f32_f16_e32 v5, v43
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v3, v58
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v42
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v7, v41
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, v33
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v40
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v9, v55
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_cvt_f32_f16_e32 v5, v57
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v54
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v11, v53
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v32
; SI-NEXT: v_cvt_f32_f16_e32 v12, v60
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f32_f16_e32 v13, v52
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_cvt_f32_f16_e32 v7, v56
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f32_f16_e32 v14, v51
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v16, v49
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v63
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v17, v48
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v19, v38
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_cvt_f32_f16_e32 v9, v62
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_cvt_f32_f16_e32 v20, v37
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v61
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_cvt_f32_f16_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, v50
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, v39
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, v36
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: .LBB46_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v12i64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB46_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB46_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB46_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_add_f16_sdwa v0, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v47
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_add_f16_sdwa v1, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v46
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_f16_sdwa v2, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v45
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_add_f16_sdwa v3, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v44
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_add_f16_sdwa v4, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v43
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_add_f16_sdwa v5, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v42
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_add_f16_sdwa v6, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v41
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_add_f16_sdwa v7, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, 0x200, v40
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_f16_sdwa v8, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, 0x200, v55
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_add_f16_sdwa v9, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, 0x200, v54
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_add_f16_sdwa v10, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, 0x200, v53
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_add_f16_sdwa v11, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, 0x200, v52
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_add_f16_sdwa v12, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, 0x200, v51
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_add_f16_sdwa v13, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v50
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_add_f16_sdwa v14, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, 0x200, v49
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_add_f16_sdwa v15, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, 0x200, v48
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_add_f16_sdwa v16, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, 0x200, v39
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_add_f16_sdwa v17, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v38
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_add_f16_sdwa v18, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, 0x200, v37
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_add_f16_sdwa v19, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v36
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_add_f16_sdwa v20, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, 0x200, v35
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_add_f16_sdwa v21, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v34
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_add_f16_sdwa v22, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v33
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB46_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v12i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB46_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB46_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB46_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: s_movk_i32 s7, 0x200
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_f16 v0, v0, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, v14, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, v15, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, v16, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, v17, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, v18, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, v19, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, v20, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB46_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12i64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB46_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v12i64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define inreg <12 x i64> @bitcast_v48f16_to_v12i64_scalar(<48 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v12i64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s34, 0
; SI-NEXT: v_writelane_b32 v32, s35, 1
; SI-NEXT: v_writelane_b32 v32, s36, 2
; SI-NEXT: v_writelane_b32 v32, s37, 3
; SI-NEXT: v_writelane_b32 v32, s38, 4
; SI-NEXT: v_writelane_b32 v32, s39, 5
; SI-NEXT: v_writelane_b32 v32, s48, 6
; SI-NEXT: v_writelane_b32 v32, s49, 7
; SI-NEXT: v_writelane_b32 v32, s50, 8
; SI-NEXT: v_writelane_b32 v32, s51, 9
; SI-NEXT: v_writelane_b32 v32, s52, 10
; SI-NEXT: v_writelane_b32 v32, s53, 11
; SI-NEXT: v_writelane_b32 v32, s54, 12
; SI-NEXT: v_writelane_b32 v32, s55, 13
; SI-NEXT: v_writelane_b32 v32, s64, 14
; SI-NEXT: v_writelane_b32 v32, s65, 15
; SI-NEXT: v_writelane_b32 v32, s66, 16
; SI-NEXT: v_writelane_b32 v32, s67, 17
; SI-NEXT: v_writelane_b32 v32, s68, 18
; SI-NEXT: v_writelane_b32 v32, s69, 19
; SI-NEXT: v_writelane_b32 v32, s30, 20
; SI-NEXT: v_writelane_b32 v32, s31, 21
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s8, v8
; SI-NEXT: v_readfirstlane_b32 s10, v7
; SI-NEXT: v_readfirstlane_b32 s12, v6
; SI-NEXT: v_readfirstlane_b32 s14, v5
; SI-NEXT: v_readfirstlane_b32 s72, v4
; SI-NEXT: v_readfirstlane_b32 s74, v3
; SI-NEXT: v_readfirstlane_b32 s76, v2
; SI-NEXT: v_readfirstlane_b32 s79, v1
; SI-NEXT: v_readfirstlane_b32 s89, v0
; SI-NEXT: s_lshr_b32 s78, s29, 16
; SI-NEXT: s_lshr_b32 s90, s28, 16
; SI-NEXT: s_lshr_b32 s92, s27, 16
; SI-NEXT: s_lshr_b32 s93, s26, 16
; SI-NEXT: s_lshr_b32 s94, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s4, s21, 16
; SI-NEXT: s_lshr_b32 s30, s20, 16
; SI-NEXT: s_lshr_b32 s31, s19, 16
; SI-NEXT: s_lshr_b32 s34, s18, 16
; SI-NEXT: s_lshr_b32 s68, s17, 16
; SI-NEXT: s_lshr_b32 s69, s16, 16
; SI-NEXT: s_lshr_b32 s35, s6, 16
; SI-NEXT: s_lshr_b32 s9, s8, 16
; SI-NEXT: s_lshr_b32 s11, s10, 16
; SI-NEXT: s_lshr_b32 s13, s12, 16
; SI-NEXT: s_lshr_b32 s15, s14, 16
; SI-NEXT: s_lshr_b32 s73, s72, 16
; SI-NEXT: s_lshr_b32 s75, s74, 16
; SI-NEXT: s_lshr_b32 s77, s76, 16
; SI-NEXT: s_lshr_b32 s88, s79, 16
; SI-NEXT: s_lshr_b32 s91, s89, 16
; SI-NEXT: v_readfirstlane_b32 s5, v10
; SI-NEXT: s_cmp_lg_u32 s5, 0
; SI-NEXT: s_cbranch_scc0 .LBB47_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s5, s16, 0xffff
; SI-NEXT: s_lshl_b32 s7, s69, 16
; SI-NEXT: s_or_b32 s36, s5, s7
; SI-NEXT: s_and_b32 s5, s17, 0xffff
; SI-NEXT: s_lshl_b32 s7, s68, 16
; SI-NEXT: s_or_b32 s37, s5, s7
; SI-NEXT: s_and_b32 s5, s18, 0xffff
; SI-NEXT: s_lshl_b32 s7, s34, 16
; SI-NEXT: s_or_b32 s38, s5, s7
; SI-NEXT: s_and_b32 s5, s19, 0xffff
; SI-NEXT: s_lshl_b32 s7, s31, 16
; SI-NEXT: s_or_b32 s39, s5, s7
; SI-NEXT: s_and_b32 s5, s20, 0xffff
; SI-NEXT: s_lshl_b32 s7, s30, 16
; SI-NEXT: s_or_b32 s40, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xffff
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_or_b32 s41, s5, s4
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s94, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s89, 0xffff
; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s79, 0xffff
; SI-NEXT: s_lshl_b32 s5, s88, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
; SI-NEXT: s_lshl_b32 s5, s13, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
; SI-NEXT: s_lshl_b32 s5, s11, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB47_3
; SI-NEXT: .LBB47_2:
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: .LBB47_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB47_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s69
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
; SI-NEXT: v_cvt_f32_f16_e32 v2, s68
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, s34
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_cvt_f32_f16_e32 v4, s31
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, s30
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, s20
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, s7
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, vcc_hi
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, vcc_lo
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_cvt_f32_f16_e32 v8, s23
; SI-NEXT: v_cvt_f32_f16_e32 v9, s95
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; SI-NEXT: v_cvt_f32_f16_e32 v9, s94
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s93
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v11, v9
; SI-NEXT: v_cvt_f32_f16_e32 v11, s26
; SI-NEXT: v_cvt_f32_f16_e32 v12, s92
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s90
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s78
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, s29
; SI-NEXT: v_cvt_f32_f16_e32 v15, s91
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_cvt_f32_f16_e32 v16, s89
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: v_cvt_f32_f16_e32 v15, s88
; SI-NEXT: v_cvt_f32_f16_e32 v17, s79
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s77
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, s76
; SI-NEXT: v_cvt_f32_f16_e32 v18, s75
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v19, s74
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_cvt_f32_f16_e32 v18, s73
; SI-NEXT: v_cvt_f32_f16_e32 v20, s72
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s15
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, s14
; SI-NEXT: v_cvt_f32_f16_e32 v21, s13
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_cvt_f32_f16_e32 v22, s12
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: v_cvt_f32_f16_e32 v21, s11
; SI-NEXT: v_cvt_f32_f16_e32 v23, s10
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s9
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: v_cvt_f32_f16_e32 v23, s8
; SI-NEXT: v_cvt_f32_f16_e32 v24, s35
; SI-NEXT: v_cvt_f32_f16_e32 v25, s6
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: s_branch .LBB47_6
; SI-NEXT: .LBB47_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB47_6: ; %end
; SI-NEXT: v_readlane_b32 s30, v32, 20
; SI-NEXT: v_readlane_b32 s31, v32, 21
; SI-NEXT: v_readlane_b32 s69, v32, 19
; SI-NEXT: v_readlane_b32 s68, v32, 18
; SI-NEXT: v_readlane_b32 s67, v32, 17
; SI-NEXT: v_readlane_b32 s66, v32, 16
; SI-NEXT: v_readlane_b32 s65, v32, 15
; SI-NEXT: v_readlane_b32 s64, v32, 14
; SI-NEXT: v_readlane_b32 s55, v32, 13
; SI-NEXT: v_readlane_b32 s54, v32, 12
; SI-NEXT: v_readlane_b32 s53, v32, 11
; SI-NEXT: v_readlane_b32 s52, v32, 10
; SI-NEXT: v_readlane_b32 s51, v32, 9
; SI-NEXT: v_readlane_b32 s50, v32, 8
; SI-NEXT: v_readlane_b32 s49, v32, 7
; SI-NEXT: v_readlane_b32 s48, v32, 6
; SI-NEXT: v_readlane_b32 s39, v32, 5
; SI-NEXT: v_readlane_b32 s38, v32, 4
; SI-NEXT: v_readlane_b32 s37, v32, 3
; SI-NEXT: v_readlane_b32 s36, v32, 2
; SI-NEXT: v_readlane_b32 s35, v32, 1
; SI-NEXT: v_readlane_b32 s34, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v12i64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s34, 0
; VI-NEXT: v_writelane_b32 v32, s35, 1
; VI-NEXT: v_writelane_b32 v32, s36, 2
; VI-NEXT: v_writelane_b32 v32, s37, 3
; VI-NEXT: v_writelane_b32 v32, s38, 4
; VI-NEXT: v_writelane_b32 v32, s39, 5
; VI-NEXT: v_writelane_b32 v32, s48, 6
; VI-NEXT: v_writelane_b32 v32, s49, 7
; VI-NEXT: v_writelane_b32 v32, s50, 8
; VI-NEXT: v_writelane_b32 v32, s51, 9
; VI-NEXT: v_writelane_b32 v32, s52, 10
; VI-NEXT: v_writelane_b32 v32, s53, 11
; VI-NEXT: v_writelane_b32 v32, s54, 12
; VI-NEXT: v_writelane_b32 v32, s55, 13
; VI-NEXT: v_writelane_b32 v32, s64, 14
; VI-NEXT: v_writelane_b32 v32, s65, 15
; VI-NEXT: v_writelane_b32 v32, s66, 16
; VI-NEXT: v_writelane_b32 v32, s67, 17
; VI-NEXT: v_writelane_b32 v32, s68, 18
; VI-NEXT: v_writelane_b32 v32, s69, 19
; VI-NEXT: v_writelane_b32 v32, s70, 20
; VI-NEXT: v_writelane_b32 v32, s71, 21
; VI-NEXT: v_writelane_b32 v32, s80, 22
; VI-NEXT: v_writelane_b32 v32, s81, 23
; VI-NEXT: v_writelane_b32 v32, s30, 24
; VI-NEXT: v_writelane_b32 v32, s31, 25
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s8, v8
; VI-NEXT: v_readfirstlane_b32 s10, v7
; VI-NEXT: v_readfirstlane_b32 s12, v6
; VI-NEXT: v_readfirstlane_b32 s14, v5
; VI-NEXT: v_readfirstlane_b32 s73, v4
; VI-NEXT: v_readfirstlane_b32 s76, v3
; VI-NEXT: v_readfirstlane_b32 s79, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s4, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s74, s28, 16
; VI-NEXT: s_lshr_b32 s77, s27, 16
; VI-NEXT: s_lshr_b32 s88, s26, 16
; VI-NEXT: s_lshr_b32 s90, s25, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s24, 16
; VI-NEXT: s_lshr_b32 s31, s23, 16
; VI-NEXT: s_lshr_b32 s34, s22, 16
; VI-NEXT: s_lshr_b32 s35, s21, 16
; VI-NEXT: s_lshr_b32 s68, s20, 16
; VI-NEXT: s_lshr_b32 s69, s19, 16
; VI-NEXT: s_lshr_b32 s70, s18, 16
; VI-NEXT: s_lshr_b32 s71, s17, 16
; VI-NEXT: s_lshr_b32 s80, s16, 16
; VI-NEXT: s_lshr_b32 s81, s6, 16
; VI-NEXT: s_lshr_b32 s9, s8, 16
; VI-NEXT: s_lshr_b32 s11, s10, 16
; VI-NEXT: s_lshr_b32 s13, s12, 16
; VI-NEXT: s_lshr_b32 s15, s14, 16
; VI-NEXT: s_lshr_b32 s75, s73, 16
; VI-NEXT: s_lshr_b32 s78, s76, 16
; VI-NEXT: s_lshr_b32 s89, s79, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s91, 16
; VI-NEXT: s_lshr_b32 s30, s4, 16
; VI-NEXT: v_readfirstlane_b32 s5, v10
; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc0 .LBB47_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s5, 0xffff, s16
; VI-NEXT: s_lshl_b32 s7, s80, 16
; VI-NEXT: s_or_b32 s36, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s7, s71, 16
; VI-NEXT: s_or_b32 s37, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s18
; VI-NEXT: s_lshl_b32 s7, s70, 16
; VI-NEXT: s_or_b32 s38, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s19
; VI-NEXT: s_lshl_b32 s7, s69, 16
; VI-NEXT: s_or_b32 s39, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s20
; VI-NEXT: s_lshl_b32 s7, s68, 16
; VI-NEXT: s_or_b32 s40, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s21
; VI-NEXT: s_lshl_b32 s7, s35, 16
; VI-NEXT: s_or_b32 s41, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s22
; VI-NEXT: s_lshl_b32 s7, s34, 16
; VI-NEXT: s_or_b32 s42, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s23
; VI-NEXT: s_lshl_b32 s7, s31, 16
; VI-NEXT: s_or_b32 s43, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s24
; VI-NEXT: s_lshl_b32 s7, vcc_hi, 16
; VI-NEXT: s_or_b32 s44, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s25
; VI-NEXT: s_lshl_b32 s7, s90, 16
; VI-NEXT: s_or_b32 s45, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s26
; VI-NEXT: s_lshl_b32 s7, s88, 16
; VI-NEXT: s_or_b32 s46, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s27
; VI-NEXT: s_lshl_b32 s7, s77, 16
; VI-NEXT: s_or_b32 s47, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s28
; VI-NEXT: s_lshl_b32 s7, s74, 16
; VI-NEXT: s_or_b32 s48, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s29
; VI-NEXT: s_lshl_b32 s7, s72, 16
; VI-NEXT: s_or_b32 s49, s5, s7
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_and_b32 s4, 0xffff, s4
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s15, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB47_3
; VI-NEXT: .LBB47_2:
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: .LBB47_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB47_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_mov_b32_e32 v0, s80
; VI-NEXT: v_mov_b32_e32 v2, s71
; VI-NEXT: v_add_f16_sdwa v0, v0, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v23
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v23
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v23
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_mov_b32_e32 v3, s69
; VI-NEXT: v_add_f16_sdwa v3, v3, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v23
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_mov_b32_e32 v4, s68
; VI-NEXT: v_add_f16_sdwa v4, v4, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v23
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_mov_b32_e32 v5, s35
; VI-NEXT: v_add_f16_sdwa v5, v5, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v23
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_mov_b32_e32 v6, s34
; VI-NEXT: v_add_f16_sdwa v6, v6, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v23
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_mov_b32_e32 v7, s31
; VI-NEXT: v_add_f16_sdwa v7, v7, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v23
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_mov_b32_e32 v8, vcc_hi
; VI-NEXT: v_add_f16_sdwa v8, v8, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v23
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_mov_b32_e32 v9, s90
; VI-NEXT: v_add_f16_sdwa v9, v9, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v23
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_mov_b32_e32 v10, s88
; VI-NEXT: v_add_f16_sdwa v10, v10, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v23
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_mov_b32_e32 v11, s77
; VI-NEXT: v_add_f16_sdwa v11, v11, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v23
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_mov_b32_e32 v12, s74
; VI-NEXT: v_add_f16_sdwa v12, v12, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v23
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_mov_b32_e32 v13, s72
; VI-NEXT: v_add_f16_sdwa v13, v13, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v23
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_add_f16_sdwa v14, v14, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v23
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_mov_b32_e32 v15, vcc_lo
; VI-NEXT: v_add_f16_sdwa v15, v15, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s91, v23
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_mov_b32_e32 v16, s89
; VI-NEXT: v_add_f16_sdwa v16, v16, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s79, v23
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_mov_b32_e32 v17, s78
; VI-NEXT: v_add_f16_sdwa v17, v17, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s76, v23
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_mov_b32_e32 v18, s75
; VI-NEXT: v_add_f16_sdwa v18, v18, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s73, v23
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_mov_b32_e32 v19, s15
; VI-NEXT: v_add_f16_sdwa v19, v19, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s14, v23
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_mov_b32_e32 v20, s13
; VI-NEXT: v_add_f16_sdwa v20, v20, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s12, v23
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_mov_b32_e32 v21, s11
; VI-NEXT: v_add_f16_sdwa v21, v21, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s10, v23
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_mov_b32_e32 v22, s9
; VI-NEXT: v_add_f16_sdwa v22, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s8, v23
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_mov_b32_e32 v24, s81
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: s_branch .LBB47_6
; VI-NEXT: .LBB47_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB47_6: ; %end
; VI-NEXT: v_readlane_b32 s30, v32, 24
; VI-NEXT: v_readlane_b32 s31, v32, 25
; VI-NEXT: v_readlane_b32 s81, v32, 23
; VI-NEXT: v_readlane_b32 s80, v32, 22
; VI-NEXT: v_readlane_b32 s71, v32, 21
; VI-NEXT: v_readlane_b32 s70, v32, 20
; VI-NEXT: v_readlane_b32 s69, v32, 19
; VI-NEXT: v_readlane_b32 s68, v32, 18
; VI-NEXT: v_readlane_b32 s67, v32, 17
; VI-NEXT: v_readlane_b32 s66, v32, 16
; VI-NEXT: v_readlane_b32 s65, v32, 15
; VI-NEXT: v_readlane_b32 s64, v32, 14
; VI-NEXT: v_readlane_b32 s55, v32, 13
; VI-NEXT: v_readlane_b32 s54, v32, 12
; VI-NEXT: v_readlane_b32 s53, v32, 11
; VI-NEXT: v_readlane_b32 s52, v32, 10
; VI-NEXT: v_readlane_b32 s51, v32, 9
; VI-NEXT: v_readlane_b32 s50, v32, 8
; VI-NEXT: v_readlane_b32 s49, v32, 7
; VI-NEXT: v_readlane_b32 s48, v32, 6
; VI-NEXT: v_readlane_b32 s39, v32, 5
; VI-NEXT: v_readlane_b32 s38, v32, 4
; VI-NEXT: v_readlane_b32 s37, v32, 3
; VI-NEXT: v_readlane_b32 s36, v32, 2
; VI-NEXT: v_readlane_b32 s35, v32, 1
; VI-NEXT: v_readlane_b32 s34, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v12i64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB47_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB47_3
; GFX9-NEXT: .LBB47_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB47_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB47_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_mov_b32_e32 v23, 0x200
; GFX9-NEXT: v_pk_add_f16 v0, s36, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s37, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, s38, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, s39, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, s40, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, s41, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, s42, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, s43, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, s44, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, s45, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, s46, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, s47, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, s48, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, s49, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, s50, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, s51, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB47_6
; GFX9-NEXT: .LBB47_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB47_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48f16_to_v12i64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB47_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB47_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB47_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB47_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <12 x i64>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <12 x i64>
br label %end
end:
%phi = phi <12 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x i64> %phi
}
define <48 x i16> @bitcast_v12f64_to_v48i16(<12 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB48_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v39, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v50, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB48_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB48_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v39, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v50, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB48_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v50
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v39
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v33
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v49
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v38
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: v_or_b32_e32 v1, v1, v50
; SI-NEXT: v_or_b32_e32 v3, v3, v39
; SI-NEXT: v_or_b32_e32 v5, v5, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v33
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v48i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB48_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB48_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB48_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB48_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v48i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB48_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB48_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB48_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB48_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v12f64_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-TRUE16-NEXT: .LBB48_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12f64_to_v48i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB48_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB48_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB48_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB48_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define inreg <48 x i16> @bitcast_v12f64_to_v48i16_scalar(<12 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v48i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v40, s30, 0
; SI-NEXT: v_writelane_b32 v40, s31, 1
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s13, v9
; SI-NEXT: v_readfirstlane_b32 s12, v8
; SI-NEXT: v_readfirstlane_b32 s11, v7
; SI-NEXT: v_readfirstlane_b32 s10, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s7, v3
; SI-NEXT: v_readfirstlane_b32 s6, v2
; SI-NEXT: v_readfirstlane_b32 s5, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s4, v0
; SI-NEXT: s_cbranch_scc0 .LBB49_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s11, 16
; SI-NEXT: s_lshr_b64 s[14:15], s[12:13], 16
; SI-NEXT: s_lshr_b32 s30, s13, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s9, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s7, 16
; SI-NEXT: s_lshr_b32 s95, s5, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s93, s27, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s91, s23, 16
; SI-NEXT: s_lshr_b32 s90, s21, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: s_lshr_b32 s88, s17, 16
; SI-NEXT: s_mov_b32 s15, s40
; SI-NEXT: s_lshr_b64 s[40:41], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB49_3
; SI-NEXT: .LBB49_2:
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $vcc_hi
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: .LBB49_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: s_cbranch_scc1 .LBB49_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f64 v[22:23], s[12:13], 1.0
; SI-NEXT: v_add_f64 v[20:21], s[10:11], 1.0
; SI-NEXT: v_add_f64 v[18:19], s[8:9], 1.0
; SI-NEXT: v_lshr_b64 v[24:25], v[22:23], 16
; SI-NEXT: v_add_f64 v[16:17], s[6:7], 1.0
; SI-NEXT: v_lshr_b64 v[25:26], v[20:21], 16
; SI-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
; SI-NEXT: v_lshr_b64 v[26:27], v[18:19], 16
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
; SI-NEXT: v_lshr_b64 v[27:28], v[16:17], 16
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; SI-NEXT: v_lshr_b64 v[28:29], v[14:15], 16
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT: v_lshr_b64 v[29:30], v[12:13], 16
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT: v_lshr_b64 v[30:31], v[10:11], 16
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT: v_lshr_b64 v[31:32], v[8:9], 16
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT: v_lshr_b64 v[32:33], v[6:7], 16
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
; SI-NEXT: v_lshr_b64 v[33:34], v[4:5], 16
; SI-NEXT: v_lshr_b64 v[34:35], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[35:36], v[0:1], 16
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v1
; SI-NEXT: s_branch .LBB49_6
; SI-NEXT: .LBB49_5:
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v23, s13
; SI-NEXT: v_mov_b32_e32 v21, s11
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v17, s7
; SI-NEXT: v_mov_b32_e32 v15, s5
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v14, s4
; SI-NEXT: v_mov_b32_e32 v16, s6
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v20, s10
; SI-NEXT: v_mov_b32_e32 v22, s12
; SI-NEXT: v_mov_b32_e32 v37, s30
; SI-NEXT: v_mov_b32_e32 v38, s15
; SI-NEXT: v_mov_b32_e32 v39, vcc_hi
; SI-NEXT: v_mov_b32_e32 v48, vcc_lo
; SI-NEXT: v_mov_b32_e32 v49, s95
; SI-NEXT: v_mov_b32_e32 v50, s94
; SI-NEXT: v_mov_b32_e32 v51, s93
; SI-NEXT: v_mov_b32_e32 v52, s92
; SI-NEXT: v_mov_b32_e32 v53, s91
; SI-NEXT: v_mov_b32_e32 v54, s90
; SI-NEXT: v_mov_b32_e32 v55, s89
; SI-NEXT: v_mov_b32_e32 v36, s88
; SI-NEXT: v_mov_b32_e32 v35, s76
; SI-NEXT: v_mov_b32_e32 v34, s74
; SI-NEXT: v_mov_b32_e32 v33, s72
; SI-NEXT: v_mov_b32_e32 v32, s62
; SI-NEXT: v_mov_b32_e32 v31, s60
; SI-NEXT: v_mov_b32_e32 v30, s58
; SI-NEXT: v_mov_b32_e32 v29, s56
; SI-NEXT: v_mov_b32_e32 v28, s46
; SI-NEXT: v_mov_b32_e32 v27, s44
; SI-NEXT: v_mov_b32_e32 v26, s42
; SI-NEXT: v_mov_b32_e32 v25, s40
; SI-NEXT: v_mov_b32_e32 v24, s14
; SI-NEXT: .LBB49_6: ; %end
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v36
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v55
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v54
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v53
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v52
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v51
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v50
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v49
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v48
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v39
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v38
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v37
; SI-NEXT: v_readlane_b32 s30, v40, 0
; SI-NEXT: v_or_b32_e32 v1, v1, v35
; SI-NEXT: v_or_b32_e32 v3, v3, v34
; SI-NEXT: v_or_b32_e32 v5, v5, v33
; SI-NEXT: v_or_b32_e32 v7, v7, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_readlane_b32 s31, v40, 1
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v48i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s9, v9
; VI-NEXT: v_readfirstlane_b32 s8, v8
; VI-NEXT: v_readfirstlane_b32 s11, v7
; VI-NEXT: v_readfirstlane_b32 s10, v6
; VI-NEXT: v_readfirstlane_b32 s13, v5
; VI-NEXT: v_readfirstlane_b32 s12, v4
; VI-NEXT: v_readfirstlane_b32 s7, v3
; VI-NEXT: v_readfirstlane_b32 s6, v2
; VI-NEXT: v_readfirstlane_b32 s5, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s4, v0
; VI-NEXT: s_cbranch_scc0 .LBB49_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s9, 16
; VI-NEXT: s_lshr_b32 s60, s8, 16
; VI-NEXT: s_lshr_b32 s41, s11, 16
; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: s_lshr_b32 s42, s13, 16
; VI-NEXT: s_lshr_b32 s62, s12, 16
; VI-NEXT: s_lshr_b32 s43, s7, 16
; VI-NEXT: s_lshr_b32 s63, s6, 16
; VI-NEXT: s_lshr_b32 s44, s5, 16
; VI-NEXT: s_lshr_b32 s72, s4, 16
; VI-NEXT: s_lshr_b32 s45, s29, 16
; VI-NEXT: s_lshr_b32 s73, s28, 16
; VI-NEXT: s_lshr_b32 s46, s27, 16
; VI-NEXT: s_lshr_b32 s74, s26, 16
; VI-NEXT: s_lshr_b32 s47, s25, 16
; VI-NEXT: s_lshr_b32 s75, s24, 16
; VI-NEXT: s_lshr_b32 s56, s23, 16
; VI-NEXT: s_lshr_b32 s76, s22, 16
; VI-NEXT: s_lshr_b32 s57, s21, 16
; VI-NEXT: s_lshr_b32 s77, s20, 16
; VI-NEXT: s_lshr_b32 s58, s19, 16
; VI-NEXT: s_lshr_b32 s78, s18, 16
; VI-NEXT: s_lshr_b32 s59, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[14:15], 0
; VI-NEXT: s_branch .LBB49_3
; VI-NEXT: .LBB49_2:
; VI-NEXT: s_mov_b64 s[14:15], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB49_3: ; %Flow
; VI-NEXT: s_and_b64 s[14:15], s[14:15], exec
; VI-NEXT: s_cselect_b32 s14, 1, 0
; VI-NEXT: s_cmp_lg_u32 s14, 1
; VI-NEXT: s_cbranch_scc1 .LBB49_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], s[8:9], 1.0
; VI-NEXT: v_add_f64 v[20:21], s[10:11], 1.0
; VI-NEXT: v_add_f64 v[18:19], s[12:13], 1.0
; VI-NEXT: v_add_f64 v[16:17], s[6:7], 1.0
; VI-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; VI-NEXT: s_branch .LBB49_6
; VI-NEXT: .LBB49_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v14, s4
; VI-NEXT: v_mov_b32_e32 v16, s6
; VI-NEXT: v_mov_b32_e32 v18, s12
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v15, s5
; VI-NEXT: v_mov_b32_e32 v17, s7
; VI-NEXT: v_mov_b32_e32 v19, s13
; VI-NEXT: v_mov_b32_e32 v20, s10
; VI-NEXT: v_mov_b32_e32 v21, s11
; VI-NEXT: v_mov_b32_e32 v22, s8
; VI-NEXT: v_mov_b32_e32 v23, s9
; VI-NEXT: v_mov_b32_e32 v53, s79
; VI-NEXT: v_mov_b32_e32 v51, s78
; VI-NEXT: v_mov_b32_e32 v49, s77
; VI-NEXT: v_mov_b32_e32 v48, s76
; VI-NEXT: v_mov_b32_e32 v38, s75
; VI-NEXT: v_mov_b32_e32 v35, s74
; VI-NEXT: v_mov_b32_e32 v33, s73
; VI-NEXT: v_mov_b32_e32 v31, s72
; VI-NEXT: v_mov_b32_e32 v29, s63
; VI-NEXT: v_mov_b32_e32 v27, s62
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v55, s59
; VI-NEXT: v_mov_b32_e32 v54, s58
; VI-NEXT: v_mov_b32_e32 v52, s57
; VI-NEXT: v_mov_b32_e32 v50, s56
; VI-NEXT: v_mov_b32_e32 v39, s47
; VI-NEXT: v_mov_b32_e32 v37, s46
; VI-NEXT: v_mov_b32_e32 v36, s45
; VI-NEXT: v_mov_b32_e32 v34, s44
; VI-NEXT: v_mov_b32_e32 v32, s43
; VI-NEXT: v_mov_b32_e32 v30, s42
; VI-NEXT: v_mov_b32_e32 v28, s41
; VI-NEXT: v_mov_b32_e32 v26, s40
; VI-NEXT: .LBB49_6: ; %end
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v55
; VI-NEXT: v_or_b32_sdwa v2, v2, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v54
; VI-NEXT: v_or_b32_sdwa v4, v4, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; VI-NEXT: v_or_b32_sdwa v6, v6, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v50
; VI-NEXT: v_or_b32_sdwa v8, v8, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v39
; VI-NEXT: v_or_b32_sdwa v10, v10, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v37
; VI-NEXT: v_or_b32_sdwa v12, v12, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v36
; VI-NEXT: v_or_b32_sdwa v14, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v34
; VI-NEXT: v_or_b32_sdwa v16, v16, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v32
; VI-NEXT: v_or_b32_sdwa v18, v18, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v30
; VI-NEXT: v_or_b32_sdwa v20, v20, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v28
; VI-NEXT: v_or_b32_sdwa v22, v22, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v26
; VI-NEXT: v_or_b32_sdwa v1, v1, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v48i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s9, v9
; GFX9-NEXT: v_readfirstlane_b32 s8, v8
; GFX9-NEXT: v_readfirstlane_b32 s11, v7
; GFX9-NEXT: v_readfirstlane_b32 s10, v6
; GFX9-NEXT: v_readfirstlane_b32 s13, v5
; GFX9-NEXT: v_readfirstlane_b32 s12, v4
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: v_readfirstlane_b32 s6, v2
; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB49_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s9, 16
; GFX9-NEXT: s_lshr_b32 s60, s8, 16
; GFX9-NEXT: s_lshr_b32 s41, s11, 16
; GFX9-NEXT: s_lshr_b32 s61, s10, 16
; GFX9-NEXT: s_lshr_b32 s42, s13, 16
; GFX9-NEXT: s_lshr_b32 s62, s12, 16
; GFX9-NEXT: s_lshr_b32 s43, s7, 16
; GFX9-NEXT: s_lshr_b32 s63, s6, 16
; GFX9-NEXT: s_lshr_b32 s44, s5, 16
; GFX9-NEXT: s_lshr_b32 s72, s4, 16
; GFX9-NEXT: s_lshr_b32 s45, s29, 16
; GFX9-NEXT: s_lshr_b32 s73, s28, 16
; GFX9-NEXT: s_lshr_b32 s46, s27, 16
; GFX9-NEXT: s_lshr_b32 s74, s26, 16
; GFX9-NEXT: s_lshr_b32 s47, s25, 16
; GFX9-NEXT: s_lshr_b32 s75, s24, 16
; GFX9-NEXT: s_lshr_b32 s56, s23, 16
; GFX9-NEXT: s_lshr_b32 s76, s22, 16
; GFX9-NEXT: s_lshr_b32 s57, s21, 16
; GFX9-NEXT: s_lshr_b32 s77, s20, 16
; GFX9-NEXT: s_lshr_b32 s58, s19, 16
; GFX9-NEXT: s_lshr_b32 s78, s18, 16
; GFX9-NEXT: s_lshr_b32 s59, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[14:15], 0
; GFX9-NEXT: s_branch .LBB49_3
; GFX9-NEXT: .LBB49_2:
; GFX9-NEXT: s_mov_b64 s[14:15], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB49_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[14:15], s[14:15], exec
; GFX9-NEXT: s_cselect_b32 s14, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s14, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB49_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], s[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], s[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], s[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], s[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX9-NEXT: s_branch .LBB49_6
; GFX9-NEXT: .LBB49_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v14, s4
; GFX9-NEXT: v_mov_b32_e32 v16, s6
; GFX9-NEXT: v_mov_b32_e32 v18, s12
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v15, s5
; GFX9-NEXT: v_mov_b32_e32 v17, s7
; GFX9-NEXT: v_mov_b32_e32 v19, s13
; GFX9-NEXT: v_mov_b32_e32 v20, s10
; GFX9-NEXT: v_mov_b32_e32 v21, s11
; GFX9-NEXT: v_mov_b32_e32 v22, s8
; GFX9-NEXT: v_mov_b32_e32 v23, s9
; GFX9-NEXT: v_mov_b32_e32 v53, s79
; GFX9-NEXT: v_mov_b32_e32 v51, s78
; GFX9-NEXT: v_mov_b32_e32 v49, s77
; GFX9-NEXT: v_mov_b32_e32 v48, s76
; GFX9-NEXT: v_mov_b32_e32 v38, s75
; GFX9-NEXT: v_mov_b32_e32 v35, s74
; GFX9-NEXT: v_mov_b32_e32 v33, s73
; GFX9-NEXT: v_mov_b32_e32 v31, s72
; GFX9-NEXT: v_mov_b32_e32 v29, s63
; GFX9-NEXT: v_mov_b32_e32 v27, s62
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v55, s59
; GFX9-NEXT: v_mov_b32_e32 v54, s58
; GFX9-NEXT: v_mov_b32_e32 v52, s57
; GFX9-NEXT: v_mov_b32_e32 v50, s56
; GFX9-NEXT: v_mov_b32_e32 v39, s47
; GFX9-NEXT: v_mov_b32_e32 v37, s46
; GFX9-NEXT: v_mov_b32_e32 v36, s45
; GFX9-NEXT: v_mov_b32_e32 v34, s44
; GFX9-NEXT: v_mov_b32_e32 v32, s43
; GFX9-NEXT: v_mov_b32_e32 v30, s42
; GFX9-NEXT: v_mov_b32_e32 v28, s41
; GFX9-NEXT: v_mov_b32_e32 v26, s40
; GFX9-NEXT: .LBB49_6: ; %end
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v53, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v55
; GFX9-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v54
; GFX9-NEXT: v_or_b32_sdwa v4, v49, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; GFX9-NEXT: v_or_b32_sdwa v6, v48, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v50
; GFX9-NEXT: v_or_b32_sdwa v8, v38, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v39
; GFX9-NEXT: v_or_b32_sdwa v10, v35, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v37
; GFX9-NEXT: v_or_b32_sdwa v12, v33, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v36
; GFX9-NEXT: v_or_b32_sdwa v14, v31, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v34
; GFX9-NEXT: v_or_b32_sdwa v16, v29, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v32
; GFX9-NEXT: v_or_b32_sdwa v18, v27, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v30
; GFX9-NEXT: v_or_b32_sdwa v20, v25, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v28
; GFX9-NEXT: v_or_b32_sdwa v22, v24, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v26
; GFX9-NEXT: v_or_b32_sdwa v1, v53, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v3, v51, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v5, v49, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v7, v48, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v9, v38, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v11, v35, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v13, v33, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v15, v31, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v17, v29, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v19, v27, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v21, v25, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v12f64_to_v48i16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s12, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB49_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s6, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s56, s4, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s9, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s8, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s28, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s26, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s25, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s60, s24, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s23, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s61, s22, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s21, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s62, s20, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s19, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s63, s18, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s17, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s72, s16, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s73, s2, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s1, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-TRUE16-NEXT: s_branch .LBB49_3
; GFX11-TRUE16-NEXT: .LBB49_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr46
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr73
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr45
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr72
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr44
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr63
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr43
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr62
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr42
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr61
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr41
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr60
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr40
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr59
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr15
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr58
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr14
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr57
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr13
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr56
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr11
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr47
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr10
; GFX11-TRUE16-NEXT: .LBB49_3: ; %Flow
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB49_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], s[6:7], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], s[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], s[8:9], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], s[28:29], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], s[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], s[0:1], 1.0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v23
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v18
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-TRUE16-NEXT: s_branch .LBB49_6
; GFX11-TRUE16-NEXT: .LBB49_5:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s8 :: v_dual_mov_b32 v19, s9
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s4 :: v_dual_mov_b32 v21, s5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s6 :: v_dual_mov_b32 v23, s7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, s74 :: v_dual_mov_b32 v24, s47
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, s73 :: v_dual_mov_b32 v54, s45
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, s72 :: v_dual_mov_b32 v52, s44
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, s63 :: v_dual_mov_b32 v50, s43
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, s62 :: v_dual_mov_b32 v48, s42
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s61 :: v_dual_mov_b32 v38, s41
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, s60 :: v_dual_mov_b32 v36, s40
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s59 :: v_dual_mov_b32 v34, s15
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, s58 :: v_dual_mov_b32 v32, s14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, s57 :: v_dual_mov_b32 v30, s13
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s56 :: v_dual_mov_b32 v28, s11
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s46 :: v_dual_mov_b32 v26, s10
; GFX11-TRUE16-NEXT: .LBB49_6: ; %end
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v53.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v51.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v54.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v52.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v39.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v37.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v48.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v34.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v32.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v25.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v24.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12f64_to_v48i16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s12, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB49_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s6, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s4, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s9, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s8, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s14, s29, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s28, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s26, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s40, s25, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s60, s24, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s41, s23, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s61, s22, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s42, s21, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s62, s20, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s19, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s63, s18, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s44, s17, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s72, s16, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s3, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s73, s2, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s1, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-FAKE16-NEXT: s_branch .LBB49_3
; GFX11-FAKE16-NEXT: .LBB49_2:
; GFX11-FAKE16-NEXT: s_mov_b32 s12, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr46
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr45
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr72
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr62
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr61
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr40
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr15
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr58
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr14
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr57
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr13
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr11
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr10
; GFX11-FAKE16-NEXT: .LBB49_3: ; %Flow
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-FAKE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB49_5
; GFX11-FAKE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_f64 v[19:20], s[6:7], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[21:22], s[4:5], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[23:24], s[8:9], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[14:15], s[28:29], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[16:17], s[26:27], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[9:10], s[24:25], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[11:12], s[22:23], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[25:26], s[20:21], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[4:5], s[18:19], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[6:7], s[16:17], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[0:1], s[2:3], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[2:3], s[0:1], 1.0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v26
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v25
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: s_branch .LBB49_6
; GFX11-FAKE16-NEXT: .LBB49_5:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v25, s20
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v11, s22
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v9, s24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s18 :: v_dual_mov_b32 v23, s8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s26 :: v_dual_mov_b32 v21, s4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s28 :: v_dual_mov_b32 v19, s6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v26, s21
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v12, s23
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, s17 :: v_dual_mov_b32 v10, s25
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, s19 :: v_dual_mov_b32 v24, s9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, s27 :: v_dual_mov_b32 v22, s5
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v15, s29 :: v_dual_mov_b32 v20, s7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, s74 :: v_dual_mov_b32 v52, s73
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, s72 :: v_dual_mov_b32 v48, s63
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s62 :: v_dual_mov_b32 v13, s60
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s61 :: v_dual_mov_b32 v33, s59
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s58 :: v_dual_mov_b32 v27, s47
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s57 :: v_dual_mov_b32 v55, s46
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v28, s56 :: v_dual_mov_b32 v51, s44
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s45 :: v_dual_mov_b32 v39, s42
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s43 :: v_dual_mov_b32 v37, s40
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, s41 :: v_dual_mov_b32 v35, s15
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s14 :: v_dual_mov_b32 v31, s13
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s11 :: v_dual_mov_b32 v29, s10
; GFX11-FAKE16-NEXT: .LBB49_6: ; %end
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v52, 16, v64
; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v39, 16, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff, v5
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v48, 16, v52
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v38, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v33, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 16, v25
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v20
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v54, 16, v65
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v51, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v50, 16, v53
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v37, 16, v48
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v35, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v34, 16, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v31, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v28, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v30, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v27, 16, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v29, 16, v25
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define <12 x double> @bitcast_v48i16_to_v12f64(<48 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v12f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v36
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v38
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v48
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v50
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v43
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v23
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v22
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v19
; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v18
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v16
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v15
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v14
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v13
; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v12
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_or_b32_e32 v1, v1, v59
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_or_b32_e32 v3, v3, v58
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_or_b32_e32 v5, v5, v57
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_or_b32_e32 v7, v7, v56
; SI-NEXT: v_or_b32_e32 v8, v8, v63
; SI-NEXT: v_or_b32_e32 v9, v9, v62
; SI-NEXT: v_or_b32_e32 v10, v10, v61
; SI-NEXT: v_or_b32_e32 v11, v11, v60
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB50_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB50_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v51
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v47
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v46
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v45
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v44
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v43
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v42
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v41
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v40
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v55
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v54
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v53
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_or_b32_e32 v0, v35, v0
; SI-NEXT: v_or_b32_e32 v1, v59, v1
; SI-NEXT: v_or_b32_e32 v2, v34, v2
; SI-NEXT: v_or_b32_e32 v3, v58, v3
; SI-NEXT: v_or_b32_e32 v4, v33, v4
; SI-NEXT: v_or_b32_e32 v5, v57, v5
; SI-NEXT: v_or_b32_e32 v6, v32, v6
; SI-NEXT: v_or_b32_e32 v7, v56, v7
; SI-NEXT: v_or_b32_e32 v8, v63, v8
; SI-NEXT: v_or_b32_e32 v9, v62, v9
; SI-NEXT: v_or_b32_e32 v10, v61, v10
; SI-NEXT: v_or_b32_e32 v11, v60, v11
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x30000, v1
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v3
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v9, vcc, 0x30000, v9
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v10
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_or_b32_e32 v12, v13, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v50
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v49
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_or_b32_e32 v14, v15, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v48
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_or_b32_e32 v15, v16, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v39
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v38
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_or_b32_e32 v17, v18, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v37
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v18, v19, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 3, v36
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x30000, v11
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v17, vcc, 0x30000, v17
; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_or_b32_e32 v20, v21, v20
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v20
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v21, vcc, 3, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v22, v21
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v21
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v22
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_i32_e32 v23, vcc, 3, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v24, v23
; SI-NEXT: v_add_i32_e32 v23, vcc, 0x30000, v23
; SI-NEXT: .LBB50_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v12f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB50_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB50_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB50_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 3
; VI-NEXT: v_add_u16_e32 v0, 3, v47
; VI-NEXT: v_add_u16_sdwa v1, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: v_add_u16_e32 v1, 3, v46
; VI-NEXT: v_add_u16_sdwa v2, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u16_e32 v2, 3, v45
; VI-NEXT: v_add_u16_sdwa v3, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v3, 3, v44
; VI-NEXT: v_add_u16_sdwa v4, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u16_e32 v4, 3, v43
; VI-NEXT: v_add_u16_sdwa v5, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u16_e32 v5, 3, v42
; VI-NEXT: v_add_u16_sdwa v6, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u16_e32 v6, 3, v41
; VI-NEXT: v_add_u16_sdwa v7, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: v_add_u16_e32 v7, 3, v40
; VI-NEXT: v_add_u16_sdwa v8, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u16_e32 v8, 3, v55
; VI-NEXT: v_add_u16_sdwa v9, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_add_u16_e32 v9, 3, v54
; VI-NEXT: v_add_u16_sdwa v10, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u16_e32 v10, 3, v53
; VI-NEXT: v_add_u16_sdwa v11, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_add_u16_e32 v11, 3, v52
; VI-NEXT: v_add_u16_sdwa v12, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u16_e32 v12, 3, v51
; VI-NEXT: v_add_u16_sdwa v13, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_add_u16_e32 v13, 3, v50
; VI-NEXT: v_add_u16_sdwa v14, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_add_u16_e32 v14, 3, v49
; VI-NEXT: v_add_u16_sdwa v15, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_add_u16_e32 v15, 3, v48
; VI-NEXT: v_add_u16_sdwa v16, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: v_add_u16_e32 v16, 3, v39
; VI-NEXT: v_add_u16_sdwa v17, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: v_add_u16_e32 v17, 3, v38
; VI-NEXT: v_add_u16_sdwa v18, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: v_add_u16_e32 v18, 3, v37
; VI-NEXT: v_add_u16_sdwa v19, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: v_add_u16_e32 v19, 3, v36
; VI-NEXT: v_add_u16_sdwa v20, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: v_add_u16_e32 v20, 3, v35
; VI-NEXT: v_add_u16_sdwa v21, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: v_add_u16_e32 v21, 3, v34
; VI-NEXT: v_add_u16_sdwa v22, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: v_add_u16_e32 v22, 3, v33
; VI-NEXT: v_add_u16_sdwa v24, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v22, v22, v24
; VI-NEXT: v_add_u16_e32 v24, 3, v32
; VI-NEXT: v_add_u16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB50_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v12f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB50_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB50_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB50_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB50_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v12f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v12f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define inreg <12 x double> @bitcast_v48i16_to_v12f64_scalar(<48 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v12f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v24, s36, 0
; SI-NEXT: v_writelane_b32 v24, s37, 1
; SI-NEXT: v_writelane_b32 v24, s38, 2
; SI-NEXT: v_writelane_b32 v24, s39, 3
; SI-NEXT: v_writelane_b32 v24, s48, 4
; SI-NEXT: v_writelane_b32 v24, s49, 5
; SI-NEXT: v_writelane_b32 v24, s50, 6
; SI-NEXT: v_writelane_b32 v24, s51, 7
; SI-NEXT: v_writelane_b32 v24, s52, 8
; SI-NEXT: v_writelane_b32 v24, s53, 9
; SI-NEXT: v_writelane_b32 v24, s54, 10
; SI-NEXT: v_writelane_b32 v24, s55, 11
; SI-NEXT: v_writelane_b32 v24, s64, 12
; SI-NEXT: v_writelane_b32 v24, s65, 13
; SI-NEXT: v_writelane_b32 v24, s66, 14
; SI-NEXT: v_writelane_b32 v24, s67, 15
; SI-NEXT: v_writelane_b32 v24, s30, 16
; SI-NEXT: v_writelane_b32 v24, s31, 17
; SI-NEXT: v_readfirstlane_b32 s7, v9
; SI-NEXT: v_readfirstlane_b32 s9, v8
; SI-NEXT: v_readfirstlane_b32 s11, v7
; SI-NEXT: v_readfirstlane_b32 s13, v6
; SI-NEXT: v_readfirstlane_b32 s15, v5
; SI-NEXT: v_readfirstlane_b32 s74, v4
; SI-NEXT: v_readfirstlane_b32 s77, v3
; SI-NEXT: v_readfirstlane_b32 s88, v2
; SI-NEXT: v_readfirstlane_b32 s91, v1
; SI-NEXT: v_readfirstlane_b32 s94, v0
; SI-NEXT: s_lshr_b32 s72, s29, 16
; SI-NEXT: s_lshr_b32 s75, s28, 16
; SI-NEXT: s_lshr_b32 s78, s27, 16
; SI-NEXT: s_lshr_b32 s89, s26, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s60, s21, 16
; SI-NEXT: s_lshr_b32 s61, s20, 16
; SI-NEXT: s_lshr_b32 s62, s19, 16
; SI-NEXT: s_lshr_b32 s63, s18, 16
; SI-NEXT: s_lshr_b32 s30, s17, 16
; SI-NEXT: s_lshr_b32 s31, s16, 16
; SI-NEXT: s_lshr_b32 s6, s7, 16
; SI-NEXT: s_lshr_b32 s8, s9, 16
; SI-NEXT: s_lshr_b32 s10, s11, 16
; SI-NEXT: s_lshr_b32 s12, s13, 16
; SI-NEXT: s_lshr_b32 s14, s15, 16
; SI-NEXT: s_lshr_b32 s73, s74, 16
; SI-NEXT: s_lshr_b32 s76, s77, 16
; SI-NEXT: s_lshr_b32 s79, s88, 16
; SI-NEXT: s_lshr_b32 s90, s91, 16
; SI-NEXT: s_lshr_b32 s93, s94, 16
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_cbranch_scc0 .LBB51_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s36, s4, s5
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s37, s4, s5
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s38, s4, s5
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s39, s4, s5
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s40, s4, s5
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s41, s4, s5
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s91, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s88, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s77, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s15, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s13, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s11, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s9, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s7, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB51_3
; SI-NEXT: .LBB51_2:
; SI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v25, s77, 0
; SI-NEXT: v_writelane_b32 v25, s74, 1
; SI-NEXT: v_writelane_b32 v25, s15, 2
; SI-NEXT: v_writelane_b32 v25, s13, 3
; SI-NEXT: s_mov_b32 s13, s11
; SI-NEXT: s_mov_b32 s11, s9
; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_mov_b32 s7, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, s95
; SI-NEXT: s_mov_b32 s95, s93
; SI-NEXT: s_mov_b32 s93, s92
; SI-NEXT: s_mov_b32 s92, s90
; SI-NEXT: s_mov_b32 s90, s89
; SI-NEXT: s_mov_b32 s89, s79
; SI-NEXT: s_mov_b32 s79, s78
; SI-NEXT: s_mov_b32 s78, s76
; SI-NEXT: s_mov_b32 s76, s75
; SI-NEXT: s_mov_b32 s75, s73
; SI-NEXT: s_mov_b32 s73, s72
; SI-NEXT: s_mov_b32 s72, s14
; SI-NEXT: s_mov_b32 s14, s12
; SI-NEXT: s_mov_b32 s12, s10
; SI-NEXT: s_mov_b32 s10, s8
; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s6, s60
; SI-NEXT: s_mov_b32 s77, s88
; SI-NEXT: s_mov_b32 s88, s61
; SI-NEXT: s_mov_b32 s74, s91
; SI-NEXT: s_mov_b32 s91, s62
; SI-NEXT: s_mov_b32 s15, s63
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: s_mov_b32 s63, s15
; SI-NEXT: s_mov_b32 s62, s91
; SI-NEXT: s_mov_b32 s91, s74
; SI-NEXT: s_mov_b32 s61, s88
; SI-NEXT: s_mov_b32 s88, s77
; SI-NEXT: s_mov_b32 s60, s6
; SI-NEXT: s_mov_b32 s6, s8
; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s10, s12
; SI-NEXT: s_mov_b32 s12, s14
; SI-NEXT: s_mov_b32 s14, s72
; SI-NEXT: s_mov_b32 s72, s73
; SI-NEXT: s_mov_b32 s73, s75
; SI-NEXT: s_mov_b32 s75, s76
; SI-NEXT: s_mov_b32 s76, s78
; SI-NEXT: s_mov_b32 s78, s79
; SI-NEXT: s_mov_b32 s79, s89
; SI-NEXT: s_mov_b32 s89, s90
; SI-NEXT: s_mov_b32 s90, s92
; SI-NEXT: s_mov_b32 s92, s93
; SI-NEXT: s_mov_b32 s93, s95
; SI-NEXT: s_mov_b32 s95, vcc_lo
; SI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; SI-NEXT: s_mov_b32 vcc_hi, s7
; SI-NEXT: s_mov_b32 s7, s9
; SI-NEXT: s_mov_b32 s9, s11
; SI-NEXT: s_mov_b32 s11, s13
; SI-NEXT: v_readlane_b32 s13, v25, 3
; SI-NEXT: v_readlane_b32 s15, v25, 2
; SI-NEXT: v_readlane_b32 s74, v25, 1
; SI-NEXT: v_readlane_b32 s77, v25, 0
; SI-NEXT: .LBB51_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB51_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_and_b32 s4, s16, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s36, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s17, 0xffff
; SI-NEXT: s_lshl_b32 s5, s30, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s37, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s18, 0xffff
; SI-NEXT: s_lshl_b32 s5, s63, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s38, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s19, 0xffff
; SI-NEXT: s_lshl_b32 s5, s62, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s39, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s20, 0xffff
; SI-NEXT: s_lshl_b32 s5, s61, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s40, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s21, 0xffff
; SI-NEXT: s_lshl_b32 s5, s60, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_add_i32 s41, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s42, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: s_add_i32 s43, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_add_i32 s44, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: s_add_i32 s45, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s89, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_add_i32 s46, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: s_add_i32 s47, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_add_i32 s48, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s72, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s94, s94, 3
; SI-NEXT: s_add_i32 s49, s4, 0x30000
; SI-NEXT: s_and_b32 s4, s94, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s50, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s91, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s51, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s88, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s79, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s52, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s77, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s76, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s53, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s74, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s54, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s15, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s14, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s55, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s13, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s12, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s56, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s11, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s10, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s9, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s8, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s58, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s7, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s6, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
; SI-NEXT: .LBB51_5: ; %end
; SI-NEXT: v_readlane_b32 s30, v24, 16
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_readlane_b32 s31, v24, 17
; SI-NEXT: v_readlane_b32 s67, v24, 15
; SI-NEXT: v_readlane_b32 s66, v24, 14
; SI-NEXT: v_readlane_b32 s65, v24, 13
; SI-NEXT: v_readlane_b32 s64, v24, 12
; SI-NEXT: v_readlane_b32 s55, v24, 11
; SI-NEXT: v_readlane_b32 s54, v24, 10
; SI-NEXT: v_readlane_b32 s53, v24, 9
; SI-NEXT: v_readlane_b32 s52, v24, 8
; SI-NEXT: v_readlane_b32 s51, v24, 7
; SI-NEXT: v_readlane_b32 s50, v24, 6
; SI-NEXT: v_readlane_b32 s49, v24, 5
; SI-NEXT: v_readlane_b32 s48, v24, 4
; SI-NEXT: v_readlane_b32 s39, v24, 3
; SI-NEXT: v_readlane_b32 s38, v24, 2
; SI-NEXT: v_readlane_b32 s37, v24, 1
; SI-NEXT: v_readlane_b32 s36, v24, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v12f64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v24, s34, 0
; VI-NEXT: v_writelane_b32 v24, s35, 1
; VI-NEXT: v_writelane_b32 v24, s36, 2
; VI-NEXT: v_writelane_b32 v24, s37, 3
; VI-NEXT: v_writelane_b32 v24, s38, 4
; VI-NEXT: v_writelane_b32 v24, s39, 5
; VI-NEXT: v_writelane_b32 v24, s48, 6
; VI-NEXT: v_writelane_b32 v24, s49, 7
; VI-NEXT: v_writelane_b32 v24, s50, 8
; VI-NEXT: v_writelane_b32 v24, s51, 9
; VI-NEXT: v_writelane_b32 v24, s52, 10
; VI-NEXT: v_writelane_b32 v24, s53, 11
; VI-NEXT: v_writelane_b32 v24, s54, 12
; VI-NEXT: v_writelane_b32 v24, s55, 13
; VI-NEXT: v_writelane_b32 v24, s64, 14
; VI-NEXT: v_writelane_b32 v24, s65, 15
; VI-NEXT: v_writelane_b32 v24, s66, 16
; VI-NEXT: v_writelane_b32 v24, s67, 17
; VI-NEXT: v_writelane_b32 v24, s30, 18
; VI-NEXT: v_writelane_b32 v24, s31, 19
; VI-NEXT: v_readfirstlane_b32 s7, v9
; VI-NEXT: v_readfirstlane_b32 s9, v8
; VI-NEXT: v_readfirstlane_b32 s11, v7
; VI-NEXT: v_readfirstlane_b32 s13, v6
; VI-NEXT: v_readfirstlane_b32 s15, v5
; VI-NEXT: v_readfirstlane_b32 s74, v4
; VI-NEXT: v_readfirstlane_b32 s77, v3
; VI-NEXT: v_readfirstlane_b32 s88, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s60, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s75, s28, 16
; VI-NEXT: s_lshr_b32 s78, s27, 16
; VI-NEXT: s_lshr_b32 s89, s26, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s25, 16
; VI-NEXT: s_lshr_b32 s61, s24, 16
; VI-NEXT: s_lshr_b32 s62, s23, 16
; VI-NEXT: s_lshr_b32 s63, s22, 16
; VI-NEXT: s_lshr_b32 s30, s21, 16
; VI-NEXT: s_lshr_b32 s31, s20, 16
; VI-NEXT: s_lshr_b32 s34, s19, 16
; VI-NEXT: s_lshr_b32 s35, s18, 16
; VI-NEXT: s_lshr_b32 s64, s17, 16
; VI-NEXT: s_lshr_b32 s65, s16, 16
; VI-NEXT: s_lshr_b32 s6, s7, 16
; VI-NEXT: s_lshr_b32 s8, s9, 16
; VI-NEXT: s_lshr_b32 s10, s11, 16
; VI-NEXT: s_lshr_b32 s12, s13, 16
; VI-NEXT: s_lshr_b32 s14, s15, 16
; VI-NEXT: s_lshr_b32 s73, s74, 16
; VI-NEXT: s_lshr_b32 s76, s77, 16
; VI-NEXT: s_lshr_b32 s79, s88, 16
; VI-NEXT: s_lshr_b32 s90, s91, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s60, 16
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: s_cbranch_scc0 .LBB51_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s36, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s17
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s37, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s18
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s38, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s19
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s39, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s20
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s40, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s21
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s41, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s22
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s42, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s23
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s43, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s24
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s44, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s25
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s45, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s26
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s46, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s27
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s47, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s28
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s48, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s29
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s49, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s60
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s88
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s77
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s74
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s15
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s13
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s11
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s9
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s7
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB51_3
; VI-NEXT: .LBB51_2:
; VI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: v_writelane_b32 v25, s77, 0
; VI-NEXT: v_writelane_b32 v25, s74, 1
; VI-NEXT: v_writelane_b32 v25, s15, 2
; VI-NEXT: v_writelane_b32 v25, s13, 3
; VI-NEXT: v_writelane_b32 v25, s11, 4
; VI-NEXT: v_writelane_b32 v25, s9, 5
; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_mov_b32 s7, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, s90
; VI-NEXT: s_mov_b32 s90, s89
; VI-NEXT: s_mov_b32 s89, s79
; VI-NEXT: s_mov_b32 s79, s78
; VI-NEXT: s_mov_b32 s78, s76
; VI-NEXT: s_mov_b32 s76, s75
; VI-NEXT: s_mov_b32 s75, s73
; VI-NEXT: s_mov_b32 s73, s72
; VI-NEXT: s_mov_b32 s72, s14
; VI-NEXT: s_mov_b32 s14, s12
; VI-NEXT: s_mov_b32 s12, s10
; VI-NEXT: s_mov_b32 s10, s8
; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s6, s60
; VI-NEXT: s_mov_b32 s77, s61
; VI-NEXT: s_mov_b32 s74, s88
; VI-NEXT: s_mov_b32 s88, s62
; VI-NEXT: s_mov_b32 s11, s63
; VI-NEXT: s_mov_b32 s15, s91
; VI-NEXT: s_mov_b32 s91, s64
; VI-NEXT: s_mov_b32 s13, s65
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: s_mov_b32 s65, s13
; VI-NEXT: s_mov_b32 s64, s91
; VI-NEXT: s_mov_b32 s91, s15
; VI-NEXT: s_mov_b32 s63, s11
; VI-NEXT: s_mov_b32 s62, s88
; VI-NEXT: s_mov_b32 s88, s74
; VI-NEXT: s_mov_b32 s61, s77
; VI-NEXT: s_mov_b32 s60, s6
; VI-NEXT: s_mov_b32 s6, s8
; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s10, s12
; VI-NEXT: s_mov_b32 s12, s14
; VI-NEXT: s_mov_b32 s14, s72
; VI-NEXT: s_mov_b32 s72, s73
; VI-NEXT: s_mov_b32 s73, s75
; VI-NEXT: s_mov_b32 s75, s76
; VI-NEXT: s_mov_b32 s76, s78
; VI-NEXT: s_mov_b32 s78, s79
; VI-NEXT: s_mov_b32 s79, s89
; VI-NEXT: s_mov_b32 s89, s90
; VI-NEXT: s_mov_b32 s90, vcc_lo
; VI-NEXT: s_mov_b32 vcc_lo, vcc_hi
; VI-NEXT: s_mov_b32 vcc_hi, s7
; VI-NEXT: s_mov_b32 s7, s9
; VI-NEXT: v_readlane_b32 s9, v25, 5
; VI-NEXT: v_readlane_b32 s11, v25, 4
; VI-NEXT: v_readlane_b32 s13, v25, 3
; VI-NEXT: v_readlane_b32 s15, v25, 2
; VI-NEXT: v_readlane_b32 s74, v25, 1
; VI-NEXT: v_readlane_b32 s77, v25, 0
; VI-NEXT: .LBB51_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB51_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_and_b32 s4, s16, 0xffff
; VI-NEXT: s_lshl_b32 s5, s65, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s36, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s17, 0xffff
; VI-NEXT: s_lshl_b32 s5, s64, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s37, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s18, 0xffff
; VI-NEXT: s_lshl_b32 s5, s35, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s38, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s19, 0xffff
; VI-NEXT: s_lshl_b32 s5, s34, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s39, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s20, 0xffff
; VI-NEXT: s_lshl_b32 s5, s31, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s40, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s21, 0xffff
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s41, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s22, 0xffff
; VI-NEXT: s_lshl_b32 s5, s63, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s42, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s23, 0xffff
; VI-NEXT: s_lshl_b32 s5, s62, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s43, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s24, 0xffff
; VI-NEXT: s_lshl_b32 s5, s61, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s44, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s25, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s45, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s26, 0xffff
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s46, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s27, 0xffff
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s47, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s28, 0xffff
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s48, s4, 0x30000
; VI-NEXT: s_and_b32 s4, s29, 0xffff
; VI-NEXT: s_lshl_b32 s5, s72, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s49, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s60, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s50, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s91, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s90, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s51, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s88, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s52, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s77, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s76, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s53, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s74, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s73, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s54, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s15, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s14, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s55, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s13, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s12, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s56, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s11, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s10, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s57, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s9, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s8, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s58, s4, 0x30000
; VI-NEXT: s_add_i32 s4, s7, 3
; VI-NEXT: s_and_b32 s4, s4, 0xffff
; VI-NEXT: s_lshl_b32 s5, s6, 16
; VI-NEXT: s_or_b32 s4, s5, s4
; VI-NEXT: s_add_i32 s59, s4, 0x30000
; VI-NEXT: .LBB51_5: ; %end
; VI-NEXT: v_readlane_b32 s30, v24, 18
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_readlane_b32 s31, v24, 19
; VI-NEXT: v_readlane_b32 s67, v24, 17
; VI-NEXT: v_readlane_b32 s66, v24, 16
; VI-NEXT: v_readlane_b32 s65, v24, 15
; VI-NEXT: v_readlane_b32 s64, v24, 14
; VI-NEXT: v_readlane_b32 s55, v24, 13
; VI-NEXT: v_readlane_b32 s54, v24, 12
; VI-NEXT: v_readlane_b32 s53, v24, 11
; VI-NEXT: v_readlane_b32 s52, v24, 10
; VI-NEXT: v_readlane_b32 s51, v24, 9
; VI-NEXT: v_readlane_b32 s50, v24, 8
; VI-NEXT: v_readlane_b32 s49, v24, 7
; VI-NEXT: v_readlane_b32 s48, v24, 6
; VI-NEXT: v_readlane_b32 s39, v24, 5
; VI-NEXT: v_readlane_b32 s38, v24, 4
; VI-NEXT: v_readlane_b32 s37, v24, 3
; VI-NEXT: v_readlane_b32 s36, v24, 2
; VI-NEXT: v_readlane_b32 s35, v24, 1
; VI-NEXT: v_readlane_b32 s34, v24, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v12f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB51_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB51_3
; GFX9-NEXT: .LBB51_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB51_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB51_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_pk_add_u16 v0, s36, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s37, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, s38, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, s39, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, s40, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, s41, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, s42, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, s43, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, s44, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, s45, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, s46, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, s47, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, s48, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, s49, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, s50, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, s51, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, s52, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, s53, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, s54, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, s55, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, s56, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, s58, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v23, s59, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB51_6
; GFX9-NEXT: .LBB51_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB51_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48i16_to_v12f64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB51_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB51_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB51_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s20, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v21, s21, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v22, s22, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v23, s23, 3 op_sel_hi:[1,0]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB51_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define <48 x half> @bitcast_v12f64_to_v48f16(<12 x double> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v48f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr30
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr29
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr28
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr27
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB52_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v39, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v50, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB52_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB52_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; SI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; SI-NEXT: v_alignbit_b32 v24, v23, v22, 16
; SI-NEXT: v_alignbit_b32 v25, v21, v20, 16
; SI-NEXT: v_alignbit_b32 v26, v19, v18, 16
; SI-NEXT: v_alignbit_b32 v27, v17, v16, 16
; SI-NEXT: v_alignbit_b32 v28, v15, v14, 16
; SI-NEXT: v_alignbit_b32 v29, v13, v12, 16
; SI-NEXT: v_alignbit_b32 v30, v11, v10, 16
; SI-NEXT: v_alignbit_b32 v31, v9, v8, 16
; SI-NEXT: v_alignbit_b32 v33, v7, v6, 16
; SI-NEXT: v_alignbit_b32 v36, v5, v4, 16
; SI-NEXT: v_alignbit_b32 v39, v3, v2, 16
; SI-NEXT: v_alignbit_b32 v50, v1, v0, 16
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; SI-NEXT: .LBB52_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v50
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v39
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v36
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v33
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v49
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v38
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v35
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v34
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: v_or_b32_e32 v1, v1, v50
; SI-NEXT: v_or_b32_e32 v3, v3, v39
; SI-NEXT: v_or_b32_e32 v5, v5, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v33
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v48f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr30
; VI-NEXT: ; implicit-def: $vgpr29
; VI-NEXT: ; implicit-def: $vgpr28
; VI-NEXT: ; implicit-def: $vgpr27
; VI-NEXT: ; implicit-def: $vgpr26
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; implicit-def: $vgpr24
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB52_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB52_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB52_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; VI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; VI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; VI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: .LBB52_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v48f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: ; implicit-def: $vgpr31
; GFX9-NEXT: ; implicit-def: $vgpr30
; GFX9-NEXT: ; implicit-def: $vgpr29
; GFX9-NEXT: ; implicit-def: $vgpr28
; GFX9-NEXT: ; implicit-def: $vgpr27
; GFX9-NEXT: ; implicit-def: $vgpr26
; GFX9-NEXT: ; implicit-def: $vgpr25
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB52_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB52_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB52_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: .LBB52_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v55, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v54, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v53, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v52, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v51, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v50, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v49, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v48, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v37, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v36, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v33, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v31, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v30, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v29, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v28, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v27, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v26, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v25, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v12f64_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB52_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-TRUE16-NEXT: .LBB52_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12f64_to_v48f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB52_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB52_2: ; %Flow
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB52_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_f64 v[22:23], v[22:23], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[20:21], v[20:21], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[18:19], v[18:19], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[16:17], v[16:17], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-FAKE16-NEXT: .LBB52_4: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v55, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v53, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v52, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v50, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v49, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v48, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v39, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v38, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v37, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v35, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v34, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v33, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v32, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v31, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v30, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v29, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v27, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v26, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v25, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v24, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define inreg <48 x half> @bitcast_v12f64_to_v48f16_scalar(<12 x double> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v12f64_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v40, s30, 0
; SI-NEXT: v_writelane_b32 v40, s31, 1
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: v_readfirstlane_b32 s13, v9
; SI-NEXT: v_readfirstlane_b32 s12, v8
; SI-NEXT: v_readfirstlane_b32 s11, v7
; SI-NEXT: v_readfirstlane_b32 s10, v6
; SI-NEXT: v_readfirstlane_b32 s9, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s7, v3
; SI-NEXT: v_readfirstlane_b32 s6, v2
; SI-NEXT: v_readfirstlane_b32 s5, v1
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: v_readfirstlane_b32 s4, v0
; SI-NEXT: s_cbranch_scc0 .LBB53_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_lshr_b32 s40, s11, 16
; SI-NEXT: s_lshr_b64 s[14:15], s[12:13], 16
; SI-NEXT: s_lshr_b32 s30, s13, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s9, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s7, 16
; SI-NEXT: s_lshr_b32 s95, s5, 16
; SI-NEXT: s_lshr_b32 s94, s29, 16
; SI-NEXT: s_lshr_b32 s93, s27, 16
; SI-NEXT: s_lshr_b32 s92, s25, 16
; SI-NEXT: s_lshr_b32 s91, s23, 16
; SI-NEXT: s_lshr_b32 s90, s21, 16
; SI-NEXT: s_lshr_b32 s89, s19, 16
; SI-NEXT: s_lshr_b32 s88, s17, 16
; SI-NEXT: s_mov_b32 s15, s40
; SI-NEXT: s_lshr_b64 s[40:41], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[42:43], s[8:9], 16
; SI-NEXT: s_lshr_b64 s[44:45], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
; SI-NEXT: s_lshr_b64 s[56:57], s[28:29], 16
; SI-NEXT: s_lshr_b64 s[58:59], s[26:27], 16
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[16:17], 16
; SI-NEXT: s_mov_b64 s[78:79], 0
; SI-NEXT: s_branch .LBB53_3
; SI-NEXT: .LBB53_2:
; SI-NEXT: s_mov_b64 s[78:79], -1
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr89
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr91
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $sgpr93
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr95
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $vcc_hi
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr15
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: .LBB53_3: ; %Flow
; SI-NEXT: s_and_b64 s[78:79], s[78:79], exec
; SI-NEXT: s_cselect_b32 s41, 1, 0
; SI-NEXT: s_cmp_lg_u32 s41, 1
; SI-NEXT: s_cbranch_scc1 .LBB53_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_add_f64 v[22:23], s[12:13], 1.0
; SI-NEXT: v_add_f64 v[20:21], s[10:11], 1.0
; SI-NEXT: v_add_f64 v[18:19], s[8:9], 1.0
; SI-NEXT: v_lshr_b64 v[24:25], v[22:23], 16
; SI-NEXT: v_add_f64 v[16:17], s[6:7], 1.0
; SI-NEXT: v_lshr_b64 v[25:26], v[20:21], 16
; SI-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
; SI-NEXT: v_lshr_b64 v[26:27], v[18:19], 16
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
; SI-NEXT: v_lshr_b64 v[27:28], v[16:17], 16
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; SI-NEXT: v_lshr_b64 v[28:29], v[14:15], 16
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; SI-NEXT: v_lshr_b64 v[29:30], v[12:13], 16
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; SI-NEXT: v_lshr_b64 v[30:31], v[10:11], 16
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; SI-NEXT: v_lshr_b64 v[31:32], v[8:9], 16
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; SI-NEXT: v_lshr_b64 v[32:33], v[6:7], 16
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
; SI-NEXT: v_lshr_b64 v[33:34], v[4:5], 16
; SI-NEXT: v_lshr_b64 v[34:35], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[35:36], v[0:1], 16
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v5
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v1
; SI-NEXT: s_branch .LBB53_6
; SI-NEXT: .LBB53_5:
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v23, s13
; SI-NEXT: v_mov_b32_e32 v21, s11
; SI-NEXT: v_mov_b32_e32 v19, s9
; SI-NEXT: v_mov_b32_e32 v17, s7
; SI-NEXT: v_mov_b32_e32 v15, s5
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v10, s26
; SI-NEXT: v_mov_b32_e32 v12, s28
; SI-NEXT: v_mov_b32_e32 v14, s4
; SI-NEXT: v_mov_b32_e32 v16, s6
; SI-NEXT: v_mov_b32_e32 v18, s8
; SI-NEXT: v_mov_b32_e32 v20, s10
; SI-NEXT: v_mov_b32_e32 v22, s12
; SI-NEXT: v_mov_b32_e32 v37, s30
; SI-NEXT: v_mov_b32_e32 v38, s15
; SI-NEXT: v_mov_b32_e32 v39, vcc_hi
; SI-NEXT: v_mov_b32_e32 v48, vcc_lo
; SI-NEXT: v_mov_b32_e32 v49, s95
; SI-NEXT: v_mov_b32_e32 v50, s94
; SI-NEXT: v_mov_b32_e32 v51, s93
; SI-NEXT: v_mov_b32_e32 v52, s92
; SI-NEXT: v_mov_b32_e32 v53, s91
; SI-NEXT: v_mov_b32_e32 v54, s90
; SI-NEXT: v_mov_b32_e32 v55, s89
; SI-NEXT: v_mov_b32_e32 v36, s88
; SI-NEXT: v_mov_b32_e32 v35, s76
; SI-NEXT: v_mov_b32_e32 v34, s74
; SI-NEXT: v_mov_b32_e32 v33, s72
; SI-NEXT: v_mov_b32_e32 v32, s62
; SI-NEXT: v_mov_b32_e32 v31, s60
; SI-NEXT: v_mov_b32_e32 v30, s58
; SI-NEXT: v_mov_b32_e32 v29, s56
; SI-NEXT: v_mov_b32_e32 v28, s46
; SI-NEXT: v_mov_b32_e32 v27, s44
; SI-NEXT: v_mov_b32_e32 v26, s42
; SI-NEXT: v_mov_b32_e32 v25, s40
; SI-NEXT: v_mov_b32_e32 v24, s14
; SI-NEXT: .LBB53_6: ; %end
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v0, v0, v35
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v36
; SI-NEXT: v_or_b32_e32 v2, v2, v34
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v55
; SI-NEXT: v_or_b32_e32 v4, v4, v33
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v54
; SI-NEXT: v_or_b32_e32 v6, v6, v32
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v53
; SI-NEXT: v_or_b32_e32 v8, v8, v31
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v52
; SI-NEXT: v_or_b32_e32 v10, v10, v30
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v51
; SI-NEXT: v_or_b32_e32 v12, v12, v29
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v50
; SI-NEXT: v_or_b32_e32 v14, v14, v28
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v49
; SI-NEXT: v_or_b32_e32 v16, v16, v27
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v48
; SI-NEXT: v_or_b32_e32 v18, v18, v26
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v39
; SI-NEXT: v_or_b32_e32 v20, v20, v25
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v38
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v37
; SI-NEXT: v_readlane_b32 s30, v40, 0
; SI-NEXT: v_or_b32_e32 v1, v1, v35
; SI-NEXT: v_or_b32_e32 v3, v3, v34
; SI-NEXT: v_or_b32_e32 v5, v5, v33
; SI-NEXT: v_or_b32_e32 v7, v7, v32
; SI-NEXT: v_or_b32_e32 v9, v9, v31
; SI-NEXT: v_or_b32_e32 v11, v11, v30
; SI-NEXT: v_or_b32_e32 v13, v13, v29
; SI-NEXT: v_or_b32_e32 v15, v15, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v26
; SI-NEXT: v_or_b32_e32 v21, v21, v25
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: v_readlane_b32 s31, v40, 1
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v12f64_to_v48f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: v_readfirstlane_b32 s9, v9
; VI-NEXT: v_readfirstlane_b32 s8, v8
; VI-NEXT: v_readfirstlane_b32 s11, v7
; VI-NEXT: v_readfirstlane_b32 s10, v6
; VI-NEXT: v_readfirstlane_b32 s13, v5
; VI-NEXT: v_readfirstlane_b32 s12, v4
; VI-NEXT: v_readfirstlane_b32 s7, v3
; VI-NEXT: v_readfirstlane_b32 s6, v2
; VI-NEXT: v_readfirstlane_b32 s5, v1
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: v_readfirstlane_b32 s4, v0
; VI-NEXT: s_cbranch_scc0 .LBB53_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_lshr_b32 s40, s9, 16
; VI-NEXT: s_lshr_b32 s60, s8, 16
; VI-NEXT: s_lshr_b32 s41, s11, 16
; VI-NEXT: s_lshr_b32 s61, s10, 16
; VI-NEXT: s_lshr_b32 s42, s13, 16
; VI-NEXT: s_lshr_b32 s62, s12, 16
; VI-NEXT: s_lshr_b32 s43, s7, 16
; VI-NEXT: s_lshr_b32 s63, s6, 16
; VI-NEXT: s_lshr_b32 s44, s5, 16
; VI-NEXT: s_lshr_b32 s72, s4, 16
; VI-NEXT: s_lshr_b32 s45, s29, 16
; VI-NEXT: s_lshr_b32 s73, s28, 16
; VI-NEXT: s_lshr_b32 s46, s27, 16
; VI-NEXT: s_lshr_b32 s74, s26, 16
; VI-NEXT: s_lshr_b32 s47, s25, 16
; VI-NEXT: s_lshr_b32 s75, s24, 16
; VI-NEXT: s_lshr_b32 s56, s23, 16
; VI-NEXT: s_lshr_b32 s76, s22, 16
; VI-NEXT: s_lshr_b32 s57, s21, 16
; VI-NEXT: s_lshr_b32 s77, s20, 16
; VI-NEXT: s_lshr_b32 s58, s19, 16
; VI-NEXT: s_lshr_b32 s78, s18, 16
; VI-NEXT: s_lshr_b32 s59, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_mov_b64 s[14:15], 0
; VI-NEXT: s_branch .LBB53_3
; VI-NEXT: .LBB53_2:
; VI-NEXT: s_mov_b64 s[14:15], -1
; VI-NEXT: ; implicit-def: $sgpr79
; VI-NEXT: ; implicit-def: $sgpr59
; VI-NEXT: ; implicit-def: $sgpr78
; VI-NEXT: ; implicit-def: $sgpr58
; VI-NEXT: ; implicit-def: $sgpr77
; VI-NEXT: ; implicit-def: $sgpr57
; VI-NEXT: ; implicit-def: $sgpr76
; VI-NEXT: ; implicit-def: $sgpr56
; VI-NEXT: ; implicit-def: $sgpr75
; VI-NEXT: ; implicit-def: $sgpr47
; VI-NEXT: ; implicit-def: $sgpr74
; VI-NEXT: ; implicit-def: $sgpr46
; VI-NEXT: ; implicit-def: $sgpr73
; VI-NEXT: ; implicit-def: $sgpr45
; VI-NEXT: ; implicit-def: $sgpr72
; VI-NEXT: ; implicit-def: $sgpr44
; VI-NEXT: ; implicit-def: $sgpr63
; VI-NEXT: ; implicit-def: $sgpr43
; VI-NEXT: ; implicit-def: $sgpr62
; VI-NEXT: ; implicit-def: $sgpr42
; VI-NEXT: ; implicit-def: $sgpr61
; VI-NEXT: ; implicit-def: $sgpr41
; VI-NEXT: ; implicit-def: $sgpr60
; VI-NEXT: ; implicit-def: $sgpr40
; VI-NEXT: .LBB53_3: ; %Flow
; VI-NEXT: s_and_b64 s[14:15], s[14:15], exec
; VI-NEXT: s_cselect_b32 s14, 1, 0
; VI-NEXT: s_cmp_lg_u32 s14, 1
; VI-NEXT: s_cbranch_scc1 .LBB53_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_add_f64 v[22:23], s[8:9], 1.0
; VI-NEXT: v_add_f64 v[20:21], s[10:11], 1.0
; VI-NEXT: v_add_f64 v[18:19], s[12:13], 1.0
; VI-NEXT: v_add_f64 v[16:17], s[6:7], 1.0
; VI-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; VI-NEXT: s_branch .LBB53_6
; VI-NEXT: .LBB53_5:
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v14, s4
; VI-NEXT: v_mov_b32_e32 v16, s6
; VI-NEXT: v_mov_b32_e32 v18, s12
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v15, s5
; VI-NEXT: v_mov_b32_e32 v17, s7
; VI-NEXT: v_mov_b32_e32 v19, s13
; VI-NEXT: v_mov_b32_e32 v20, s10
; VI-NEXT: v_mov_b32_e32 v21, s11
; VI-NEXT: v_mov_b32_e32 v22, s8
; VI-NEXT: v_mov_b32_e32 v23, s9
; VI-NEXT: v_mov_b32_e32 v53, s79
; VI-NEXT: v_mov_b32_e32 v51, s78
; VI-NEXT: v_mov_b32_e32 v49, s77
; VI-NEXT: v_mov_b32_e32 v48, s76
; VI-NEXT: v_mov_b32_e32 v38, s75
; VI-NEXT: v_mov_b32_e32 v35, s74
; VI-NEXT: v_mov_b32_e32 v33, s73
; VI-NEXT: v_mov_b32_e32 v31, s72
; VI-NEXT: v_mov_b32_e32 v29, s63
; VI-NEXT: v_mov_b32_e32 v27, s62
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v55, s59
; VI-NEXT: v_mov_b32_e32 v54, s58
; VI-NEXT: v_mov_b32_e32 v52, s57
; VI-NEXT: v_mov_b32_e32 v50, s56
; VI-NEXT: v_mov_b32_e32 v39, s47
; VI-NEXT: v_mov_b32_e32 v37, s46
; VI-NEXT: v_mov_b32_e32 v36, s45
; VI-NEXT: v_mov_b32_e32 v34, s44
; VI-NEXT: v_mov_b32_e32 v32, s43
; VI-NEXT: v_mov_b32_e32 v30, s42
; VI-NEXT: v_mov_b32_e32 v28, s41
; VI-NEXT: v_mov_b32_e32 v26, s40
; VI-NEXT: .LBB53_6: ; %end
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v55
; VI-NEXT: v_or_b32_sdwa v2, v2, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v54
; VI-NEXT: v_or_b32_sdwa v4, v4, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; VI-NEXT: v_or_b32_sdwa v6, v6, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v50
; VI-NEXT: v_or_b32_sdwa v8, v8, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v39
; VI-NEXT: v_or_b32_sdwa v10, v10, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v37
; VI-NEXT: v_or_b32_sdwa v12, v12, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v36
; VI-NEXT: v_or_b32_sdwa v14, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v34
; VI-NEXT: v_or_b32_sdwa v16, v16, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v32
; VI-NEXT: v_or_b32_sdwa v18, v18, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v30
; VI-NEXT: v_or_b32_sdwa v20, v20, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v28
; VI-NEXT: v_or_b32_sdwa v22, v22, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v26
; VI-NEXT: v_or_b32_sdwa v1, v1, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v12f64_to_v48f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: v_readfirstlane_b32 s9, v9
; GFX9-NEXT: v_readfirstlane_b32 s8, v8
; GFX9-NEXT: v_readfirstlane_b32 s11, v7
; GFX9-NEXT: v_readfirstlane_b32 s10, v6
; GFX9-NEXT: v_readfirstlane_b32 s13, v5
; GFX9-NEXT: v_readfirstlane_b32 s12, v4
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: v_readfirstlane_b32 s6, v2
; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB53_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_lshr_b32 s40, s9, 16
; GFX9-NEXT: s_lshr_b32 s60, s8, 16
; GFX9-NEXT: s_lshr_b32 s41, s11, 16
; GFX9-NEXT: s_lshr_b32 s61, s10, 16
; GFX9-NEXT: s_lshr_b32 s42, s13, 16
; GFX9-NEXT: s_lshr_b32 s62, s12, 16
; GFX9-NEXT: s_lshr_b32 s43, s7, 16
; GFX9-NEXT: s_lshr_b32 s63, s6, 16
; GFX9-NEXT: s_lshr_b32 s44, s5, 16
; GFX9-NEXT: s_lshr_b32 s72, s4, 16
; GFX9-NEXT: s_lshr_b32 s45, s29, 16
; GFX9-NEXT: s_lshr_b32 s73, s28, 16
; GFX9-NEXT: s_lshr_b32 s46, s27, 16
; GFX9-NEXT: s_lshr_b32 s74, s26, 16
; GFX9-NEXT: s_lshr_b32 s47, s25, 16
; GFX9-NEXT: s_lshr_b32 s75, s24, 16
; GFX9-NEXT: s_lshr_b32 s56, s23, 16
; GFX9-NEXT: s_lshr_b32 s76, s22, 16
; GFX9-NEXT: s_lshr_b32 s57, s21, 16
; GFX9-NEXT: s_lshr_b32 s77, s20, 16
; GFX9-NEXT: s_lshr_b32 s58, s19, 16
; GFX9-NEXT: s_lshr_b32 s78, s18, 16
; GFX9-NEXT: s_lshr_b32 s59, s17, 16
; GFX9-NEXT: s_lshr_b32 s79, s16, 16
; GFX9-NEXT: s_mov_b64 s[14:15], 0
; GFX9-NEXT: s_branch .LBB53_3
; GFX9-NEXT: .LBB53_2:
; GFX9-NEXT: s_mov_b64 s[14:15], -1
; GFX9-NEXT: ; implicit-def: $sgpr79
; GFX9-NEXT: ; implicit-def: $sgpr59
; GFX9-NEXT: ; implicit-def: $sgpr78
; GFX9-NEXT: ; implicit-def: $sgpr58
; GFX9-NEXT: ; implicit-def: $sgpr77
; GFX9-NEXT: ; implicit-def: $sgpr57
; GFX9-NEXT: ; implicit-def: $sgpr76
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: ; implicit-def: $sgpr75
; GFX9-NEXT: ; implicit-def: $sgpr47
; GFX9-NEXT: ; implicit-def: $sgpr74
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr73
; GFX9-NEXT: ; implicit-def: $sgpr45
; GFX9-NEXT: ; implicit-def: $sgpr72
; GFX9-NEXT: ; implicit-def: $sgpr44
; GFX9-NEXT: ; implicit-def: $sgpr63
; GFX9-NEXT: ; implicit-def: $sgpr43
; GFX9-NEXT: ; implicit-def: $sgpr62
; GFX9-NEXT: ; implicit-def: $sgpr42
; GFX9-NEXT: ; implicit-def: $sgpr61
; GFX9-NEXT: ; implicit-def: $sgpr41
; GFX9-NEXT: ; implicit-def: $sgpr60
; GFX9-NEXT: ; implicit-def: $sgpr40
; GFX9-NEXT: .LBB53_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[14:15], s[14:15], exec
; GFX9-NEXT: s_cselect_b32 s14, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s14, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB53_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_add_f64 v[22:23], s[8:9], 1.0
; GFX9-NEXT: v_add_f64 v[20:21], s[10:11], 1.0
; GFX9-NEXT: v_add_f64 v[18:19], s[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[16:17], s[6:7], 1.0
; GFX9-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX9-NEXT: s_branch .LBB53_6
; GFX9-NEXT: .LBB53_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v14, s4
; GFX9-NEXT: v_mov_b32_e32 v16, s6
; GFX9-NEXT: v_mov_b32_e32 v18, s12
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v15, s5
; GFX9-NEXT: v_mov_b32_e32 v17, s7
; GFX9-NEXT: v_mov_b32_e32 v19, s13
; GFX9-NEXT: v_mov_b32_e32 v20, s10
; GFX9-NEXT: v_mov_b32_e32 v21, s11
; GFX9-NEXT: v_mov_b32_e32 v22, s8
; GFX9-NEXT: v_mov_b32_e32 v23, s9
; GFX9-NEXT: v_mov_b32_e32 v53, s79
; GFX9-NEXT: v_mov_b32_e32 v51, s78
; GFX9-NEXT: v_mov_b32_e32 v49, s77
; GFX9-NEXT: v_mov_b32_e32 v48, s76
; GFX9-NEXT: v_mov_b32_e32 v38, s75
; GFX9-NEXT: v_mov_b32_e32 v35, s74
; GFX9-NEXT: v_mov_b32_e32 v33, s73
; GFX9-NEXT: v_mov_b32_e32 v31, s72
; GFX9-NEXT: v_mov_b32_e32 v29, s63
; GFX9-NEXT: v_mov_b32_e32 v27, s62
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v55, s59
; GFX9-NEXT: v_mov_b32_e32 v54, s58
; GFX9-NEXT: v_mov_b32_e32 v52, s57
; GFX9-NEXT: v_mov_b32_e32 v50, s56
; GFX9-NEXT: v_mov_b32_e32 v39, s47
; GFX9-NEXT: v_mov_b32_e32 v37, s46
; GFX9-NEXT: v_mov_b32_e32 v36, s45
; GFX9-NEXT: v_mov_b32_e32 v34, s44
; GFX9-NEXT: v_mov_b32_e32 v32, s43
; GFX9-NEXT: v_mov_b32_e32 v30, s42
; GFX9-NEXT: v_mov_b32_e32 v28, s41
; GFX9-NEXT: v_mov_b32_e32 v26, s40
; GFX9-NEXT: .LBB53_6: ; %end
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v53, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v55
; GFX9-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v54
; GFX9-NEXT: v_or_b32_sdwa v4, v49, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v52
; GFX9-NEXT: v_or_b32_sdwa v6, v48, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v50
; GFX9-NEXT: v_or_b32_sdwa v8, v38, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v39
; GFX9-NEXT: v_or_b32_sdwa v10, v35, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v37
; GFX9-NEXT: v_or_b32_sdwa v12, v33, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v36
; GFX9-NEXT: v_or_b32_sdwa v14, v31, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v34
; GFX9-NEXT: v_or_b32_sdwa v16, v29, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v32
; GFX9-NEXT: v_or_b32_sdwa v18, v27, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v30
; GFX9-NEXT: v_or_b32_sdwa v20, v25, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v28
; GFX9-NEXT: v_or_b32_sdwa v22, v24, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v26
; GFX9-NEXT: v_or_b32_sdwa v1, v53, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v3, v51, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v5, v49, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v7, v48, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v9, v38, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v11, v35, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v13, v33, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v15, v31, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v17, v29, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v19, v27, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v21, v25, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v12f64_to_v48f16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s12, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB53_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s6, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s56, s4, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s9, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s8, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s28, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s26, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s25, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s60, s24, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s23, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s61, s22, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s21, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s62, s20, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s19, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s63, s18, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s17, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s72, s16, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s73, s2, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s1, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-TRUE16-NEXT: s_branch .LBB53_3
; GFX11-TRUE16-NEXT: .LBB53_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s12, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr46
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr73
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr45
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr72
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr44
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr63
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr43
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr62
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr42
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr61
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr41
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr60
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr40
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr59
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr15
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr58
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr14
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr57
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr13
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr56
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr11
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr47
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr10
; GFX11-TRUE16-NEXT: .LBB53_3: ; %Flow
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB53_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-TRUE16-NEXT: v_add_f64 v[22:23], s[6:7], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[20:21], s[4:5], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[18:19], s[8:9], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[16:17], s[28:29], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[2:3], s[2:3], 1.0
; GFX11-TRUE16-NEXT: v_add_f64 v[0:1], s[0:1], 1.0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v23
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v19
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v18
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-TRUE16-NEXT: s_branch .LBB53_6
; GFX11-TRUE16-NEXT: .LBB53_5:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s8 :: v_dual_mov_b32 v19, s9
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s4 :: v_dual_mov_b32 v21, s5
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s6 :: v_dual_mov_b32 v23, s7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, s74 :: v_dual_mov_b32 v24, s47
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, s73 :: v_dual_mov_b32 v54, s45
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, s72 :: v_dual_mov_b32 v52, s44
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, s63 :: v_dual_mov_b32 v50, s43
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, s62 :: v_dual_mov_b32 v48, s42
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s61 :: v_dual_mov_b32 v38, s41
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v33, s60 :: v_dual_mov_b32 v36, s40
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s59 :: v_dual_mov_b32 v34, s15
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, s58 :: v_dual_mov_b32 v32, s14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, s57 :: v_dual_mov_b32 v30, s13
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s56 :: v_dual_mov_b32 v28, s11
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s46 :: v_dual_mov_b32 v26, s10
; GFX11-TRUE16-NEXT: .LBB53_6: ; %end
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v53.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v55.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v51.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v54.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v52.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v39.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v37.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v48.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v34.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v32.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v25.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v24.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v26.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v12f64_to_v48f16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v6
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s10, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s12, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB53_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s6, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s5, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s4, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s9, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s8, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s14, s29, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s28, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s26, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s40, s25, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s60, s24, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s41, s23, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s61, s22, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s42, s21, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s62, s20, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s19, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s63, s18, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s44, s17, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s72, s16, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s3, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s73, s2, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s1, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s74, s0, 16
; GFX11-FAKE16-NEXT: s_branch .LBB53_3
; GFX11-FAKE16-NEXT: .LBB53_2:
; GFX11-FAKE16-NEXT: s_mov_b32 s12, -1
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr46
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr73
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr45
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr72
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr44
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr63
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr43
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr62
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr42
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr61
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr41
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr60
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr40
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr59
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr15
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr58
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr14
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr57
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr13
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr56
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr11
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr47
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr10
; GFX11-FAKE16-NEXT: .LBB53_3: ; %Flow
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s12, s12, exec_lo
; GFX11-FAKE16-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s12, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB53_5
; GFX11-FAKE16-NEXT: ; %bb.4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_f64 v[19:20], s[6:7], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[21:22], s[4:5], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[23:24], s[8:9], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[14:15], s[28:29], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[16:17], s[26:27], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[9:10], s[24:25], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[11:12], s[22:23], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[25:26], s[20:21], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[4:5], s[18:19], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[6:7], s[16:17], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[0:1], s[2:3], 1.0
; GFX11-FAKE16-NEXT: v_add_f64 v[2:3], s[0:1], 1.0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v24
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v26
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v25
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-FAKE16-NEXT: s_branch .LBB53_6
; GFX11-FAKE16-NEXT: .LBB53_5:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v25, s20
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v11, s22
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v9, s24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s18 :: v_dual_mov_b32 v23, s8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s26 :: v_dual_mov_b32 v21, s4
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s28 :: v_dual_mov_b32 v19, s6
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v26, s21
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v12, s23
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, s17 :: v_dual_mov_b32 v10, s25
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, s19 :: v_dual_mov_b32 v24, s9
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, s27 :: v_dual_mov_b32 v22, s5
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v15, s29 :: v_dual_mov_b32 v20, s7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, s74 :: v_dual_mov_b32 v52, s73
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, s72 :: v_dual_mov_b32 v48, s63
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s62 :: v_dual_mov_b32 v13, s60
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s61 :: v_dual_mov_b32 v33, s59
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s58 :: v_dual_mov_b32 v27, s47
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s57 :: v_dual_mov_b32 v55, s46
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v28, s56 :: v_dual_mov_b32 v51, s44
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s45 :: v_dual_mov_b32 v39, s42
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s43 :: v_dual_mov_b32 v37, s40
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, s41 :: v_dual_mov_b32 v35, s15
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s14 :: v_dual_mov_b32 v31, s13
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s11 :: v_dual_mov_b32 v29, s10
; GFX11-FAKE16-NEXT: .LBB53_6: ; %end
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v53, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v52, 16, v64
; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v39, 16, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff, v5
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v48, 16, v52
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v10
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v38, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v15
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v33, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 16, v25
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v20
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v54, 16, v65
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v51, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v50, 16, v53
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v37, 16, v48
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v35, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v34, 16, v26
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v31, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v28, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v30, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v27, 16, v24
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v29, 16, v25
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <12 x double> %a, splat (double 1.000000e+00)
%a2 = bitcast <12 x double> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <12 x double> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define <12 x double> @bitcast_v48f16_to_v12f64(<48 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v12f64:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_mov_b32_e32 v47, v0
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v22
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v21
; SI-NEXT: v_mov_b32_e32 v36, v19
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v20
; SI-NEXT: v_mov_b32_e32 v37, v18
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; SI-NEXT: v_mov_b32_e32 v38, v17
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; SI-NEXT: v_mov_b32_e32 v39, v16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; SI-NEXT: v_mov_b32_e32 v48, v15
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; SI-NEXT: v_mov_b32_e32 v49, v14
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; SI-NEXT: v_mov_b32_e32 v50, v13
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; SI-NEXT: v_mov_b32_e32 v51, v12
; SI-NEXT: v_mov_b32_e32 v52, v11
; SI-NEXT: v_mov_b32_e32 v53, v10
; SI-NEXT: v_mov_b32_e32 v54, v9
; SI-NEXT: v_mov_b32_e32 v55, v8
; SI-NEXT: v_mov_b32_e32 v40, v7
; SI-NEXT: v_mov_b32_e32 v41, v6
; SI-NEXT: v_mov_b32_e32 v42, v5
; SI-NEXT: v_mov_b32_e32 v43, v4
; SI-NEXT: v_mov_b32_e32 v44, v3
; SI-NEXT: v_mov_b32_e32 v45, v2
; SI-NEXT: v_mov_b32_e32 v46, v1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v52
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v54
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v41
; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v42
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v43
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v44
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v45
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v47
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB54_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v47
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v59
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v46
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_or_b32_e32 v1, v2, v3
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v45
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v58
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v33
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v42
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v57
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v41
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v40
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v56
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v55
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v63
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v54
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v62
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v53
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v61
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v60
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v51
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr53
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr34
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr32
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v50
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v49
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v48
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v39
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v38
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v37
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: ; implicit-def: $vgpr50
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr39
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr37
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: .LBB54_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB54_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v59
; SI-NEXT: v_cvt_f32_f16_e32 v2, v35
; SI-NEXT: v_cvt_f32_f16_e32 v1, v47
; SI-NEXT: v_cvt_f32_f16_e32 v3, v46
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_or_b32_e32 v1, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, v34
; SI-NEXT: v_cvt_f32_f16_e32 v3, v45
; SI-NEXT: v_cvt_f32_f16_e32 v4, v44
; SI-NEXT: v_cvt_f32_f16_e32 v5, v43
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v3, v58
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v42
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v7, v41
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: v_or_b32_e32 v3, v4, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, v33
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v40
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v9, v55
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_cvt_f32_f16_e32 v5, v57
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v54
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v11, v53
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_or_b32_e32 v5, v6, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, v32
; SI-NEXT: v_cvt_f32_f16_e32 v12, v60
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f32_f16_e32 v13, v52
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_cvt_f32_f16_e32 v7, v56
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f32_f16_e32 v14, v51
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v16, v49
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_cvt_f32_f16_e32 v8, v63
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v17, v48
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v19, v38
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_cvt_f32_f16_e32 v9, v62
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_cvt_f32_f16_e32 v20, v37
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v10, v9
; SI-NEXT: v_cvt_f32_f16_e32 v10, v61
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_cvt_f32_f16_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, v50
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, v39
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, v36
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: .LBB54_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v12f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v32, v23
; VI-NEXT: v_mov_b32_e32 v33, v22
; VI-NEXT: v_mov_b32_e32 v34, v21
; VI-NEXT: v_mov_b32_e32 v35, v20
; VI-NEXT: v_mov_b32_e32 v36, v19
; VI-NEXT: v_mov_b32_e32 v37, v18
; VI-NEXT: v_mov_b32_e32 v38, v17
; VI-NEXT: v_mov_b32_e32 v39, v16
; VI-NEXT: v_mov_b32_e32 v48, v15
; VI-NEXT: v_mov_b32_e32 v49, v14
; VI-NEXT: v_mov_b32_e32 v50, v13
; VI-NEXT: v_mov_b32_e32 v51, v12
; VI-NEXT: v_mov_b32_e32 v52, v11
; VI-NEXT: v_mov_b32_e32 v53, v10
; VI-NEXT: v_mov_b32_e32 v54, v9
; VI-NEXT: v_mov_b32_e32 v55, v8
; VI-NEXT: v_mov_b32_e32 v40, v7
; VI-NEXT: v_mov_b32_e32 v41, v6
; VI-NEXT: v_mov_b32_e32 v42, v5
; VI-NEXT: v_mov_b32_e32 v43, v4
; VI-NEXT: v_mov_b32_e32 v44, v3
; VI-NEXT: v_mov_b32_e32 v45, v2
; VI-NEXT: v_mov_b32_e32 v46, v1
; VI-NEXT: v_mov_b32_e32 v47, v0
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_cbranch_execz .LBB54_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: v_mov_b32_e32 v23, 16
; VI-NEXT: v_lshlrev_b32_sdwa v0, v23, v47 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v1, v23, v46 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v2, v23, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v3, v23, v44 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v4, v23, v43 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v5, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v6, v23, v41 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v7, v23, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v8, v23, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v9, v23, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v10, v23, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v11, v23, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v12, v23, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v13, v23, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v14, v23, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v15, v23, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v16, v23, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v17, v23, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v18, v23, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v19, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v20, v23, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v21, v23, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v22, v23, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_lshlrev_b32_sdwa v23, v23, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; VI-NEXT: v_or_b32_sdwa v0, v47, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v46, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v44, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v43, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v42, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v41, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v55, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v53, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v52, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v51, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v50, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v49, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v48, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v39, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v38, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v37, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v36, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v35, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v34, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v33, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v32, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: ; implicit-def: $vgpr47
; VI-NEXT: ; implicit-def: $vgpr46
; VI-NEXT: ; implicit-def: $vgpr45
; VI-NEXT: ; implicit-def: $vgpr44
; VI-NEXT: ; implicit-def: $vgpr43
; VI-NEXT: ; implicit-def: $vgpr42
; VI-NEXT: ; implicit-def: $vgpr41
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; implicit-def: $vgpr55
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: ; implicit-def: $vgpr51
; VI-NEXT: ; implicit-def: $vgpr50
; VI-NEXT: ; implicit-def: $vgpr49
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr35
; VI-NEXT: ; implicit-def: $vgpr34
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: .LBB54_2: ; %Flow
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB54_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_add_f16_sdwa v0, v47, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, 0x200, v47
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_add_f16_sdwa v1, v46, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v2, 0x200, v46
; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_f16_sdwa v2, v45, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, 0x200, v45
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_add_f16_sdwa v3, v44, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, 0x200, v44
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_add_f16_sdwa v4, v43, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, 0x200, v43
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_add_f16_sdwa v5, v42, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v42
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_add_f16_sdwa v6, v41, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v41
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_add_f16_sdwa v7, v40, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, 0x200, v40
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_add_f16_sdwa v8, v55, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, 0x200, v55
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_add_f16_sdwa v9, v54, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, 0x200, v54
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_add_f16_sdwa v10, v53, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, 0x200, v53
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_add_f16_sdwa v11, v52, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, 0x200, v52
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_add_f16_sdwa v12, v51, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, 0x200, v51
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_add_f16_sdwa v13, v50, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v50
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_add_f16_sdwa v14, v49, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, 0x200, v49
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_add_f16_sdwa v15, v48, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, 0x200, v48
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_add_f16_sdwa v16, v39, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, 0x200, v39
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_add_f16_sdwa v17, v38, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, 0x200, v38
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_add_f16_sdwa v18, v37, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, 0x200, v37
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_add_f16_sdwa v19, v36, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, 0x200, v36
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_add_f16_sdwa v20, v35, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, 0x200, v35
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_add_f16_sdwa v21, v34, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, 0x200, v34
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_add_f16_sdwa v22, v33, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v33
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_add_f16_sdwa v23, v32, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, 0x200, v32
; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: .LBB54_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v12f64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v33, v22
; GFX9-NEXT: v_mov_b32_e32 v47, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v34, v21
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v33
; GFX9-NEXT: v_mov_b32_e32 v35, v20
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v34
; GFX9-NEXT: v_mov_b32_e32 v36, v19
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v35
; GFX9-NEXT: v_mov_b32_e32 v37, v18
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v36
; GFX9-NEXT: v_mov_b32_e32 v38, v17
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v37
; GFX9-NEXT: v_mov_b32_e32 v39, v16
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v38
; GFX9-NEXT: v_mov_b32_e32 v48, v15
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v39
; GFX9-NEXT: v_mov_b32_e32 v49, v14
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v13
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v49
; GFX9-NEXT: v_mov_b32_e32 v51, v12
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v50
; GFX9-NEXT: v_mov_b32_e32 v52, v11
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v51
; GFX9-NEXT: v_mov_b32_e32 v53, v10
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v52
; GFX9-NEXT: v_mov_b32_e32 v54, v9
; GFX9-NEXT: v_mov_b32_e32 v55, v8
; GFX9-NEXT: v_mov_b32_e32 v40, v7
; GFX9-NEXT: v_mov_b32_e32 v41, v6
; GFX9-NEXT: v_mov_b32_e32 v42, v5
; GFX9-NEXT: v_mov_b32_e32 v43, v4
; GFX9-NEXT: v_mov_b32_e32 v44, v3
; GFX9-NEXT: v_mov_b32_e32 v45, v2
; GFX9-NEXT: v_mov_b32_e32 v46, v1
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v53
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v40
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v42
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v43
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v44
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v47
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB54_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v54
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v51
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v50
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v49
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v39
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v35
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v34
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v33
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: ; implicit-def: $vgpr47
; GFX9-NEXT: ; implicit-def: $vgpr46
; GFX9-NEXT: ; implicit-def: $vgpr45
; GFX9-NEXT: ; implicit-def: $vgpr44
; GFX9-NEXT: ; implicit-def: $vgpr43
; GFX9-NEXT: ; implicit-def: $vgpr42
; GFX9-NEXT: ; implicit-def: $vgpr41
; GFX9-NEXT: ; implicit-def: $vgpr40
; GFX9-NEXT: ; implicit-def: $vgpr55
; GFX9-NEXT: ; implicit-def: $vgpr54
; GFX9-NEXT: ; implicit-def: $vgpr53
; GFX9-NEXT: ; implicit-def: $vgpr52
; GFX9-NEXT: ; implicit-def: $vgpr51
; GFX9-NEXT: ; implicit-def: $vgpr50
; GFX9-NEXT: ; implicit-def: $vgpr49
; GFX9-NEXT: ; implicit-def: $vgpr48
; GFX9-NEXT: ; implicit-def: $vgpr39
; GFX9-NEXT: ; implicit-def: $vgpr38
; GFX9-NEXT: ; implicit-def: $vgpr37
; GFX9-NEXT: ; implicit-def: $vgpr36
; GFX9-NEXT: ; implicit-def: $vgpr35
; GFX9-NEXT: ; implicit-def: $vgpr34
; GFX9-NEXT: ; implicit-def: $vgpr33
; GFX9-NEXT: ; implicit-def: $vgpr63
; GFX9-NEXT: ; implicit-def: $vgpr56
; GFX9-NEXT: ; implicit-def: $vgpr57
; GFX9-NEXT: ; implicit-def: $vgpr58
; GFX9-NEXT: ; implicit-def: $vgpr59
; GFX9-NEXT: ; implicit-def: $vgpr60
; GFX9-NEXT: ; implicit-def: $vgpr61
; GFX9-NEXT: ; implicit-def: $vgpr62
; GFX9-NEXT: ; implicit-def: $vgpr32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: ; implicit-def: $vgpr24
; GFX9-NEXT: ; kill: killed $vgpr24
; GFX9-NEXT: .LBB54_2: ; %Flow
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB54_4
; GFX9-NEXT: ; %bb.3: ; %cmp.true
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v32, v47, s6
; GFX9-NEXT: s_movk_i32 s7, 0x200
; GFX9-NEXT: v_perm_b32 v1, v62, v46, s6
; GFX9-NEXT: v_perm_b32 v2, v61, v45, s6
; GFX9-NEXT: v_perm_b32 v3, v60, v44, s6
; GFX9-NEXT: v_perm_b32 v4, v59, v43, s6
; GFX9-NEXT: v_perm_b32 v5, v58, v42, s6
; GFX9-NEXT: v_perm_b32 v6, v57, v41, s6
; GFX9-NEXT: v_perm_b32 v7, v56, v40, s6
; GFX9-NEXT: v_perm_b32 v8, v63, v55, s6
; GFX9-NEXT: v_pk_add_f16 v0, v0, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: s_waitcnt vmcnt(15)
; GFX9-NEXT: v_perm_b32 v9, v9, v54, s6
; GFX9-NEXT: s_waitcnt vmcnt(14)
; GFX9-NEXT: v_perm_b32 v10, v10, v53, s6
; GFX9-NEXT: s_waitcnt vmcnt(13)
; GFX9-NEXT: v_perm_b32 v11, v11, v52, s6
; GFX9-NEXT: s_waitcnt vmcnt(12)
; GFX9-NEXT: v_perm_b32 v12, v12, v51, s6
; GFX9-NEXT: s_waitcnt vmcnt(11)
; GFX9-NEXT: v_perm_b32 v13, v13, v50, s6
; GFX9-NEXT: s_waitcnt vmcnt(10)
; GFX9-NEXT: v_perm_b32 v14, v14, v49, s6
; GFX9-NEXT: s_waitcnt vmcnt(9)
; GFX9-NEXT: v_perm_b32 v15, v15, v48, s6
; GFX9-NEXT: s_waitcnt vmcnt(8)
; GFX9-NEXT: v_perm_b32 v16, v16, v39, s6
; GFX9-NEXT: s_waitcnt vmcnt(7)
; GFX9-NEXT: v_perm_b32 v17, v17, v38, s6
; GFX9-NEXT: s_waitcnt vmcnt(6)
; GFX9-NEXT: v_perm_b32 v18, v18, v37, s6
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_perm_b32 v19, v19, v36, s6
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v20, v20, v35, s6
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v21, v21, v34, s6
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v22, v22, v33, s6
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, v14, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, v15, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, v16, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, v17, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, v18, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, v19, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, v20, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
; GFX9-NEXT: .LBB54_4: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v12f64:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB54_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB54_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v12f64:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v53, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v54, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v55, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v64, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v52, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v51, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v50, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v49, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v48, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v39, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v38, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v37, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v36, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v35, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v34, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v32, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v30, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v29, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v28, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v26, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v25, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB54_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: .LBB54_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define inreg <12 x double> @bitcast_v48f16_to_v12f64_scalar(<48 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v12f64_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v32, s34, 0
; SI-NEXT: v_writelane_b32 v32, s35, 1
; SI-NEXT: v_writelane_b32 v32, s36, 2
; SI-NEXT: v_writelane_b32 v32, s37, 3
; SI-NEXT: v_writelane_b32 v32, s38, 4
; SI-NEXT: v_writelane_b32 v32, s39, 5
; SI-NEXT: v_writelane_b32 v32, s48, 6
; SI-NEXT: v_writelane_b32 v32, s49, 7
; SI-NEXT: v_writelane_b32 v32, s50, 8
; SI-NEXT: v_writelane_b32 v32, s51, 9
; SI-NEXT: v_writelane_b32 v32, s52, 10
; SI-NEXT: v_writelane_b32 v32, s53, 11
; SI-NEXT: v_writelane_b32 v32, s54, 12
; SI-NEXT: v_writelane_b32 v32, s55, 13
; SI-NEXT: v_writelane_b32 v32, s64, 14
; SI-NEXT: v_writelane_b32 v32, s65, 15
; SI-NEXT: v_writelane_b32 v32, s66, 16
; SI-NEXT: v_writelane_b32 v32, s67, 17
; SI-NEXT: v_writelane_b32 v32, s68, 18
; SI-NEXT: v_writelane_b32 v32, s69, 19
; SI-NEXT: v_writelane_b32 v32, s30, 20
; SI-NEXT: v_writelane_b32 v32, s31, 21
; SI-NEXT: v_readfirstlane_b32 s6, v9
; SI-NEXT: v_readfirstlane_b32 s8, v8
; SI-NEXT: v_readfirstlane_b32 s10, v7
; SI-NEXT: v_readfirstlane_b32 s12, v6
; SI-NEXT: v_readfirstlane_b32 s14, v5
; SI-NEXT: v_readfirstlane_b32 s72, v4
; SI-NEXT: v_readfirstlane_b32 s74, v3
; SI-NEXT: v_readfirstlane_b32 s76, v2
; SI-NEXT: v_readfirstlane_b32 s79, v1
; SI-NEXT: v_readfirstlane_b32 s89, v0
; SI-NEXT: s_lshr_b32 s78, s29, 16
; SI-NEXT: s_lshr_b32 s90, s28, 16
; SI-NEXT: s_lshr_b32 s92, s27, 16
; SI-NEXT: s_lshr_b32 s93, s26, 16
; SI-NEXT: s_lshr_b32 s94, s25, 16
; SI-NEXT: s_lshr_b32 s95, s24, 16
; SI-NEXT: s_lshr_b32 vcc_lo, s23, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s22, 16
; SI-NEXT: s_lshr_b32 s4, s21, 16
; SI-NEXT: s_lshr_b32 s30, s20, 16
; SI-NEXT: s_lshr_b32 s31, s19, 16
; SI-NEXT: s_lshr_b32 s34, s18, 16
; SI-NEXT: s_lshr_b32 s68, s17, 16
; SI-NEXT: s_lshr_b32 s69, s16, 16
; SI-NEXT: s_lshr_b32 s35, s6, 16
; SI-NEXT: s_lshr_b32 s9, s8, 16
; SI-NEXT: s_lshr_b32 s11, s10, 16
; SI-NEXT: s_lshr_b32 s13, s12, 16
; SI-NEXT: s_lshr_b32 s15, s14, 16
; SI-NEXT: s_lshr_b32 s73, s72, 16
; SI-NEXT: s_lshr_b32 s75, s74, 16
; SI-NEXT: s_lshr_b32 s77, s76, 16
; SI-NEXT: s_lshr_b32 s88, s79, 16
; SI-NEXT: s_lshr_b32 s91, s89, 16
; SI-NEXT: v_readfirstlane_b32 s5, v10
; SI-NEXT: s_cmp_lg_u32 s5, 0
; SI-NEXT: s_cbranch_scc0 .LBB55_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s5, s16, 0xffff
; SI-NEXT: s_lshl_b32 s7, s69, 16
; SI-NEXT: s_or_b32 s36, s5, s7
; SI-NEXT: s_and_b32 s5, s17, 0xffff
; SI-NEXT: s_lshl_b32 s7, s68, 16
; SI-NEXT: s_or_b32 s37, s5, s7
; SI-NEXT: s_and_b32 s5, s18, 0xffff
; SI-NEXT: s_lshl_b32 s7, s34, 16
; SI-NEXT: s_or_b32 s38, s5, s7
; SI-NEXT: s_and_b32 s5, s19, 0xffff
; SI-NEXT: s_lshl_b32 s7, s31, 16
; SI-NEXT: s_or_b32 s39, s5, s7
; SI-NEXT: s_and_b32 s5, s20, 0xffff
; SI-NEXT: s_lshl_b32 s7, s30, 16
; SI-NEXT: s_or_b32 s40, s5, s7
; SI-NEXT: s_and_b32 s5, s21, 0xffff
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_or_b32 s41, s5, s4
; SI-NEXT: s_and_b32 s4, s22, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s42, s4, s5
; SI-NEXT: s_and_b32 s4, s23, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; SI-NEXT: s_or_b32 s43, s4, s5
; SI-NEXT: s_and_b32 s4, s24, 0xffff
; SI-NEXT: s_lshl_b32 s5, s95, 16
; SI-NEXT: s_or_b32 s44, s4, s5
; SI-NEXT: s_and_b32 s4, s25, 0xffff
; SI-NEXT: s_lshl_b32 s5, s94, 16
; SI-NEXT: s_or_b32 s45, s4, s5
; SI-NEXT: s_and_b32 s4, s26, 0xffff
; SI-NEXT: s_lshl_b32 s5, s93, 16
; SI-NEXT: s_or_b32 s46, s4, s5
; SI-NEXT: s_and_b32 s4, s27, 0xffff
; SI-NEXT: s_lshl_b32 s5, s92, 16
; SI-NEXT: s_or_b32 s47, s4, s5
; SI-NEXT: s_and_b32 s4, s28, 0xffff
; SI-NEXT: s_lshl_b32 s5, s90, 16
; SI-NEXT: s_or_b32 s48, s4, s5
; SI-NEXT: s_and_b32 s4, s29, 0xffff
; SI-NEXT: s_lshl_b32 s5, s78, 16
; SI-NEXT: s_or_b32 s49, s4, s5
; SI-NEXT: s_and_b32 s4, s89, 0xffff
; SI-NEXT: s_lshl_b32 s5, s91, 16
; SI-NEXT: s_or_b32 s50, s4, s5
; SI-NEXT: s_and_b32 s4, s79, 0xffff
; SI-NEXT: s_lshl_b32 s5, s88, 16
; SI-NEXT: s_or_b32 s51, s4, s5
; SI-NEXT: s_and_b32 s4, s76, 0xffff
; SI-NEXT: s_lshl_b32 s5, s77, 16
; SI-NEXT: s_or_b32 s52, s4, s5
; SI-NEXT: s_and_b32 s4, s74, 0xffff
; SI-NEXT: s_lshl_b32 s5, s75, 16
; SI-NEXT: s_or_b32 s53, s4, s5
; SI-NEXT: s_and_b32 s4, s72, 0xffff
; SI-NEXT: s_lshl_b32 s5, s73, 16
; SI-NEXT: s_or_b32 s54, s4, s5
; SI-NEXT: s_and_b32 s4, s14, 0xffff
; SI-NEXT: s_lshl_b32 s5, s15, 16
; SI-NEXT: s_or_b32 s55, s4, s5
; SI-NEXT: s_and_b32 s4, s12, 0xffff
; SI-NEXT: s_lshl_b32 s5, s13, 16
; SI-NEXT: s_or_b32 s56, s4, s5
; SI-NEXT: s_and_b32 s4, s10, 0xffff
; SI-NEXT: s_lshl_b32 s5, s11, 16
; SI-NEXT: s_or_b32 s57, s4, s5
; SI-NEXT: s_and_b32 s4, s8, 0xffff
; SI-NEXT: s_lshl_b32 s5, s9, 16
; SI-NEXT: s_or_b32 s58, s4, s5
; SI-NEXT: s_and_b32 s4, s6, 0xffff
; SI-NEXT: s_lshl_b32 s5, s35, 16
; SI-NEXT: s_or_b32 s59, s4, s5
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB55_3
; SI-NEXT: .LBB55_2:
; SI-NEXT: s_mov_b32 s7, s4
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; SI-NEXT: .LBB55_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB55_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v0, s69
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
; SI-NEXT: v_cvt_f32_f16_e32 v2, s68
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, s34
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
; SI-NEXT: v_or_b32_e32 v1, v3, v1
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_cvt_f32_f16_e32 v4, s31
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v6, s30
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; SI-NEXT: v_or_b32_e32 v3, v5, v3
; SI-NEXT: v_cvt_f32_f16_e32 v4, s20
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, s7
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; SI-NEXT: v_cvt_f32_f16_e32 v6, vcc_hi
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_or_b32_e32 v5, v7, v5
; SI-NEXT: v_cvt_f32_f16_e32 v7, vcc_lo
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_or_b32_e32 v6, v8, v6
; SI-NEXT: v_cvt_f32_f16_e32 v8, s23
; SI-NEXT: v_cvt_f32_f16_e32 v9, s95
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: v_cvt_f32_f16_e32 v10, s24
; SI-NEXT: v_or_b32_e32 v7, v8, v7
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; SI-NEXT: v_cvt_f32_f16_e32 v9, s94
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_or_b32_e32 v8, v10, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, s93
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: v_or_b32_e32 v9, v11, v9
; SI-NEXT: v_cvt_f32_f16_e32 v11, s26
; SI-NEXT: v_cvt_f32_f16_e32 v12, s92
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_cvt_f32_f16_e32 v13, s27
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
; SI-NEXT: v_cvt_f32_f16_e32 v12, s90
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_or_b32_e32 v11, v13, v11
; SI-NEXT: v_cvt_f32_f16_e32 v13, s78
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_or_b32_e32 v12, v14, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, s29
; SI-NEXT: v_cvt_f32_f16_e32 v15, s91
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: v_cvt_f32_f16_e32 v16, s89
; SI-NEXT: v_or_b32_e32 v13, v14, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; SI-NEXT: v_cvt_f32_f16_e32 v15, s88
; SI-NEXT: v_cvt_f32_f16_e32 v17, s79
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_or_b32_e32 v14, v16, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, s77
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: v_or_b32_e32 v15, v17, v15
; SI-NEXT: v_cvt_f32_f16_e32 v17, s76
; SI-NEXT: v_cvt_f32_f16_e32 v18, s75
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v19, s74
; SI-NEXT: v_or_b32_e32 v16, v17, v16
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
; SI-NEXT: v_cvt_f32_f16_e32 v18, s73
; SI-NEXT: v_cvt_f32_f16_e32 v20, s72
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_or_b32_e32 v17, v19, v17
; SI-NEXT: v_cvt_f32_f16_e32 v19, s15
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_or_b32_e32 v18, v20, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, s14
; SI-NEXT: v_cvt_f32_f16_e32 v21, s13
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: v_cvt_f32_f16_e32 v22, s12
; SI-NEXT: v_or_b32_e32 v19, v20, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; SI-NEXT: v_cvt_f32_f16_e32 v21, s11
; SI-NEXT: v_cvt_f32_f16_e32 v23, s10
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_or_b32_e32 v20, v22, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, s9
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: v_or_b32_e32 v21, v23, v21
; SI-NEXT: v_cvt_f32_f16_e32 v23, s8
; SI-NEXT: v_cvt_f32_f16_e32 v24, s35
; SI-NEXT: v_cvt_f32_f16_e32 v25, s6
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v22, v23, v22
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v25, v23
; SI-NEXT: s_branch .LBB55_6
; SI-NEXT: .LBB55_5:
; SI-NEXT: v_mov_b32_e32 v0, s36
; SI-NEXT: v_mov_b32_e32 v1, s37
; SI-NEXT: v_mov_b32_e32 v2, s38
; SI-NEXT: v_mov_b32_e32 v3, s39
; SI-NEXT: v_mov_b32_e32 v4, s40
; SI-NEXT: v_mov_b32_e32 v5, s41
; SI-NEXT: v_mov_b32_e32 v6, s42
; SI-NEXT: v_mov_b32_e32 v7, s43
; SI-NEXT: v_mov_b32_e32 v8, s44
; SI-NEXT: v_mov_b32_e32 v9, s45
; SI-NEXT: v_mov_b32_e32 v10, s46
; SI-NEXT: v_mov_b32_e32 v11, s47
; SI-NEXT: v_mov_b32_e32 v12, s48
; SI-NEXT: v_mov_b32_e32 v13, s49
; SI-NEXT: v_mov_b32_e32 v14, s50
; SI-NEXT: v_mov_b32_e32 v15, s51
; SI-NEXT: v_mov_b32_e32 v16, s52
; SI-NEXT: v_mov_b32_e32 v17, s53
; SI-NEXT: v_mov_b32_e32 v18, s54
; SI-NEXT: v_mov_b32_e32 v19, s55
; SI-NEXT: v_mov_b32_e32 v20, s56
; SI-NEXT: v_mov_b32_e32 v21, s57
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v23, s59
; SI-NEXT: v_mov_b32_e32 v24, s60
; SI-NEXT: v_mov_b32_e32 v25, s61
; SI-NEXT: v_mov_b32_e32 v26, s62
; SI-NEXT: v_mov_b32_e32 v27, s63
; SI-NEXT: v_mov_b32_e32 v28, s64
; SI-NEXT: v_mov_b32_e32 v29, s65
; SI-NEXT: v_mov_b32_e32 v30, s66
; SI-NEXT: v_mov_b32_e32 v31, s67
; SI-NEXT: .LBB55_6: ; %end
; SI-NEXT: v_readlane_b32 s30, v32, 20
; SI-NEXT: v_readlane_b32 s31, v32, 21
; SI-NEXT: v_readlane_b32 s69, v32, 19
; SI-NEXT: v_readlane_b32 s68, v32, 18
; SI-NEXT: v_readlane_b32 s67, v32, 17
; SI-NEXT: v_readlane_b32 s66, v32, 16
; SI-NEXT: v_readlane_b32 s65, v32, 15
; SI-NEXT: v_readlane_b32 s64, v32, 14
; SI-NEXT: v_readlane_b32 s55, v32, 13
; SI-NEXT: v_readlane_b32 s54, v32, 12
; SI-NEXT: v_readlane_b32 s53, v32, 11
; SI-NEXT: v_readlane_b32 s52, v32, 10
; SI-NEXT: v_readlane_b32 s51, v32, 9
; SI-NEXT: v_readlane_b32 s50, v32, 8
; SI-NEXT: v_readlane_b32 s49, v32, 7
; SI-NEXT: v_readlane_b32 s48, v32, 6
; SI-NEXT: v_readlane_b32 s39, v32, 5
; SI-NEXT: v_readlane_b32 s38, v32, 4
; SI-NEXT: v_readlane_b32 s37, v32, 3
; SI-NEXT: v_readlane_b32 s36, v32, 2
; SI-NEXT: v_readlane_b32 s35, v32, 1
; SI-NEXT: v_readlane_b32 s34, v32, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v12f64_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: v_writelane_b32 v32, s34, 0
; VI-NEXT: v_writelane_b32 v32, s35, 1
; VI-NEXT: v_writelane_b32 v32, s36, 2
; VI-NEXT: v_writelane_b32 v32, s37, 3
; VI-NEXT: v_writelane_b32 v32, s38, 4
; VI-NEXT: v_writelane_b32 v32, s39, 5
; VI-NEXT: v_writelane_b32 v32, s48, 6
; VI-NEXT: v_writelane_b32 v32, s49, 7
; VI-NEXT: v_writelane_b32 v32, s50, 8
; VI-NEXT: v_writelane_b32 v32, s51, 9
; VI-NEXT: v_writelane_b32 v32, s52, 10
; VI-NEXT: v_writelane_b32 v32, s53, 11
; VI-NEXT: v_writelane_b32 v32, s54, 12
; VI-NEXT: v_writelane_b32 v32, s55, 13
; VI-NEXT: v_writelane_b32 v32, s64, 14
; VI-NEXT: v_writelane_b32 v32, s65, 15
; VI-NEXT: v_writelane_b32 v32, s66, 16
; VI-NEXT: v_writelane_b32 v32, s67, 17
; VI-NEXT: v_writelane_b32 v32, s68, 18
; VI-NEXT: v_writelane_b32 v32, s69, 19
; VI-NEXT: v_writelane_b32 v32, s70, 20
; VI-NEXT: v_writelane_b32 v32, s71, 21
; VI-NEXT: v_writelane_b32 v32, s80, 22
; VI-NEXT: v_writelane_b32 v32, s81, 23
; VI-NEXT: v_writelane_b32 v32, s30, 24
; VI-NEXT: v_writelane_b32 v32, s31, 25
; VI-NEXT: v_readfirstlane_b32 s6, v9
; VI-NEXT: v_readfirstlane_b32 s8, v8
; VI-NEXT: v_readfirstlane_b32 s10, v7
; VI-NEXT: v_readfirstlane_b32 s12, v6
; VI-NEXT: v_readfirstlane_b32 s14, v5
; VI-NEXT: v_readfirstlane_b32 s73, v4
; VI-NEXT: v_readfirstlane_b32 s76, v3
; VI-NEXT: v_readfirstlane_b32 s79, v2
; VI-NEXT: v_readfirstlane_b32 s91, v1
; VI-NEXT: v_readfirstlane_b32 s4, v0
; VI-NEXT: s_lshr_b32 s72, s29, 16
; VI-NEXT: s_lshr_b32 s74, s28, 16
; VI-NEXT: s_lshr_b32 s77, s27, 16
; VI-NEXT: s_lshr_b32 s88, s26, 16
; VI-NEXT: s_lshr_b32 s90, s25, 16
; VI-NEXT: s_lshr_b32 vcc_hi, s24, 16
; VI-NEXT: s_lshr_b32 s31, s23, 16
; VI-NEXT: s_lshr_b32 s34, s22, 16
; VI-NEXT: s_lshr_b32 s35, s21, 16
; VI-NEXT: s_lshr_b32 s68, s20, 16
; VI-NEXT: s_lshr_b32 s69, s19, 16
; VI-NEXT: s_lshr_b32 s70, s18, 16
; VI-NEXT: s_lshr_b32 s71, s17, 16
; VI-NEXT: s_lshr_b32 s80, s16, 16
; VI-NEXT: s_lshr_b32 s81, s6, 16
; VI-NEXT: s_lshr_b32 s9, s8, 16
; VI-NEXT: s_lshr_b32 s11, s10, 16
; VI-NEXT: s_lshr_b32 s13, s12, 16
; VI-NEXT: s_lshr_b32 s15, s14, 16
; VI-NEXT: s_lshr_b32 s75, s73, 16
; VI-NEXT: s_lshr_b32 s78, s76, 16
; VI-NEXT: s_lshr_b32 s89, s79, 16
; VI-NEXT: s_lshr_b32 vcc_lo, s91, 16
; VI-NEXT: s_lshr_b32 s30, s4, 16
; VI-NEXT: v_readfirstlane_b32 s5, v10
; VI-NEXT: s_cmp_lg_u32 s5, 0
; VI-NEXT: s_cbranch_scc0 .LBB55_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_and_b32 s5, 0xffff, s16
; VI-NEXT: s_lshl_b32 s7, s80, 16
; VI-NEXT: s_or_b32 s36, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s7, s71, 16
; VI-NEXT: s_or_b32 s37, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s18
; VI-NEXT: s_lshl_b32 s7, s70, 16
; VI-NEXT: s_or_b32 s38, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s19
; VI-NEXT: s_lshl_b32 s7, s69, 16
; VI-NEXT: s_or_b32 s39, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s20
; VI-NEXT: s_lshl_b32 s7, s68, 16
; VI-NEXT: s_or_b32 s40, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s21
; VI-NEXT: s_lshl_b32 s7, s35, 16
; VI-NEXT: s_or_b32 s41, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s22
; VI-NEXT: s_lshl_b32 s7, s34, 16
; VI-NEXT: s_or_b32 s42, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s23
; VI-NEXT: s_lshl_b32 s7, s31, 16
; VI-NEXT: s_or_b32 s43, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s24
; VI-NEXT: s_lshl_b32 s7, vcc_hi, 16
; VI-NEXT: s_or_b32 s44, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s25
; VI-NEXT: s_lshl_b32 s7, s90, 16
; VI-NEXT: s_or_b32 s45, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s26
; VI-NEXT: s_lshl_b32 s7, s88, 16
; VI-NEXT: s_or_b32 s46, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s27
; VI-NEXT: s_lshl_b32 s7, s77, 16
; VI-NEXT: s_or_b32 s47, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s28
; VI-NEXT: s_lshl_b32 s7, s74, 16
; VI-NEXT: s_or_b32 s48, s5, s7
; VI-NEXT: s_and_b32 s5, 0xffff, s29
; VI-NEXT: s_lshl_b32 s7, s72, 16
; VI-NEXT: s_or_b32 s49, s5, s7
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_and_b32 s4, 0xffff, s4
; VI-NEXT: s_lshl_b32 s5, s30, 16
; VI-NEXT: s_or_b32 s50, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s91
; VI-NEXT: s_lshl_b32 s5, vcc_lo, 16
; VI-NEXT: s_or_b32 s51, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s79
; VI-NEXT: s_lshl_b32 s5, s89, 16
; VI-NEXT: s_or_b32 s52, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s76
; VI-NEXT: s_lshl_b32 s5, s78, 16
; VI-NEXT: s_or_b32 s53, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s73
; VI-NEXT: s_lshl_b32 s5, s75, 16
; VI-NEXT: s_or_b32 s54, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s14
; VI-NEXT: s_lshl_b32 s5, s15, 16
; VI-NEXT: s_or_b32 s55, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s12
; VI-NEXT: s_lshl_b32 s5, s13, 16
; VI-NEXT: s_or_b32 s56, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s10
; VI-NEXT: s_lshl_b32 s5, s11, 16
; VI-NEXT: s_or_b32 s57, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s8
; VI-NEXT: s_lshl_b32 s5, s9, 16
; VI-NEXT: s_or_b32 s58, s4, s5
; VI-NEXT: s_and_b32 s4, 0xffff, s6
; VI-NEXT: s_lshl_b32 s5, s81, 16
; VI-NEXT: s_or_b32 s59, s4, s5
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB55_3
; VI-NEXT: .LBB55_2:
; VI-NEXT: s_mov_b32 s7, s4
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
; VI-NEXT: .LBB55_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB55_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v23, 0x200
; VI-NEXT: v_mov_b32_e32 v0, s80
; VI-NEXT: v_mov_b32_e32 v2, s71
; VI-NEXT: v_add_f16_sdwa v0, v0, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v1, s16, v23
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s17, v23
; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_or_b32_e32 v1, v3, v2
; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_add_f16_sdwa v2, v2, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v3, s18, v23
; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_mov_b32_e32 v3, s69
; VI-NEXT: v_add_f16_sdwa v3, v3, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v4, s19, v23
; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_mov_b32_e32 v4, s68
; VI-NEXT: v_add_f16_sdwa v4, v4, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v5, s20, v23
; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_mov_b32_e32 v5, s35
; VI-NEXT: v_add_f16_sdwa v5, v5, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, s21, v23
; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_mov_b32_e32 v6, s34
; VI-NEXT: v_add_f16_sdwa v6, v6, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, s22, v23
; VI-NEXT: v_or_b32_e32 v6, v7, v6
; VI-NEXT: v_mov_b32_e32 v7, s31
; VI-NEXT: v_add_f16_sdwa v7, v7, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, s23, v23
; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: v_mov_b32_e32 v8, vcc_hi
; VI-NEXT: v_add_f16_sdwa v8, v8, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v9, s24, v23
; VI-NEXT: v_or_b32_e32 v8, v9, v8
; VI-NEXT: v_mov_b32_e32 v9, s90
; VI-NEXT: v_add_f16_sdwa v9, v9, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v10, s25, v23
; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_mov_b32_e32 v10, s88
; VI-NEXT: v_add_f16_sdwa v10, v10, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v11, s26, v23
; VI-NEXT: v_or_b32_e32 v10, v11, v10
; VI-NEXT: v_mov_b32_e32 v11, s77
; VI-NEXT: v_add_f16_sdwa v11, v11, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v12, s27, v23
; VI-NEXT: v_or_b32_e32 v11, v12, v11
; VI-NEXT: v_mov_b32_e32 v12, s74
; VI-NEXT: v_add_f16_sdwa v12, v12, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v13, s28, v23
; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_mov_b32_e32 v13, s72
; VI-NEXT: v_add_f16_sdwa v13, v13, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, s29, v23
; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_mov_b32_e32 v14, s30
; VI-NEXT: v_add_f16_sdwa v14, v14, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v15, s7, v23
; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_mov_b32_e32 v15, vcc_lo
; VI-NEXT: v_add_f16_sdwa v15, v15, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, s91, v23
; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_mov_b32_e32 v16, s89
; VI-NEXT: v_add_f16_sdwa v16, v16, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, s79, v23
; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_mov_b32_e32 v17, s78
; VI-NEXT: v_add_f16_sdwa v17, v17, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v18, s76, v23
; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_mov_b32_e32 v18, s75
; VI-NEXT: v_add_f16_sdwa v18, v18, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, s73, v23
; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_mov_b32_e32 v19, s15
; VI-NEXT: v_add_f16_sdwa v19, v19, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v20, s14, v23
; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_mov_b32_e32 v20, s13
; VI-NEXT: v_add_f16_sdwa v20, v20, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, s12, v23
; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_mov_b32_e32 v21, s11
; VI-NEXT: v_add_f16_sdwa v21, v21, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v22, s10, v23
; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_mov_b32_e32 v22, s9
; VI-NEXT: v_add_f16_sdwa v22, v22, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v24, s8, v23
; VI-NEXT: v_or_b32_e32 v22, v24, v22
; VI-NEXT: v_mov_b32_e32 v24, s81
; VI-NEXT: v_add_f16_sdwa v24, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, s6, v23
; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: s_branch .LBB55_6
; VI-NEXT: .LBB55_5:
; VI-NEXT: v_mov_b32_e32 v0, s36
; VI-NEXT: v_mov_b32_e32 v1, s37
; VI-NEXT: v_mov_b32_e32 v2, s38
; VI-NEXT: v_mov_b32_e32 v3, s39
; VI-NEXT: v_mov_b32_e32 v4, s40
; VI-NEXT: v_mov_b32_e32 v5, s41
; VI-NEXT: v_mov_b32_e32 v6, s42
; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_mov_b32_e32 v8, s44
; VI-NEXT: v_mov_b32_e32 v9, s45
; VI-NEXT: v_mov_b32_e32 v10, s46
; VI-NEXT: v_mov_b32_e32 v11, s47
; VI-NEXT: v_mov_b32_e32 v12, s48
; VI-NEXT: v_mov_b32_e32 v13, s49
; VI-NEXT: v_mov_b32_e32 v14, s50
; VI-NEXT: v_mov_b32_e32 v15, s51
; VI-NEXT: v_mov_b32_e32 v16, s52
; VI-NEXT: v_mov_b32_e32 v17, s53
; VI-NEXT: v_mov_b32_e32 v18, s54
; VI-NEXT: v_mov_b32_e32 v19, s55
; VI-NEXT: v_mov_b32_e32 v20, s56
; VI-NEXT: v_mov_b32_e32 v21, s57
; VI-NEXT: v_mov_b32_e32 v22, s58
; VI-NEXT: v_mov_b32_e32 v23, s59
; VI-NEXT: v_mov_b32_e32 v24, s60
; VI-NEXT: v_mov_b32_e32 v25, s61
; VI-NEXT: v_mov_b32_e32 v26, s62
; VI-NEXT: v_mov_b32_e32 v27, s63
; VI-NEXT: v_mov_b32_e32 v28, s64
; VI-NEXT: v_mov_b32_e32 v29, s65
; VI-NEXT: v_mov_b32_e32 v30, s66
; VI-NEXT: v_mov_b32_e32 v31, s67
; VI-NEXT: .LBB55_6: ; %end
; VI-NEXT: v_readlane_b32 s30, v32, 24
; VI-NEXT: v_readlane_b32 s31, v32, 25
; VI-NEXT: v_readlane_b32 s81, v32, 23
; VI-NEXT: v_readlane_b32 s80, v32, 22
; VI-NEXT: v_readlane_b32 s71, v32, 21
; VI-NEXT: v_readlane_b32 s70, v32, 20
; VI-NEXT: v_readlane_b32 s69, v32, 19
; VI-NEXT: v_readlane_b32 s68, v32, 18
; VI-NEXT: v_readlane_b32 s67, v32, 17
; VI-NEXT: v_readlane_b32 s66, v32, 16
; VI-NEXT: v_readlane_b32 s65, v32, 15
; VI-NEXT: v_readlane_b32 s64, v32, 14
; VI-NEXT: v_readlane_b32 s55, v32, 13
; VI-NEXT: v_readlane_b32 s54, v32, 12
; VI-NEXT: v_readlane_b32 s53, v32, 11
; VI-NEXT: v_readlane_b32 s52, v32, 10
; VI-NEXT: v_readlane_b32 s51, v32, 9
; VI-NEXT: v_readlane_b32 s50, v32, 8
; VI-NEXT: v_readlane_b32 s49, v32, 7
; VI-NEXT: v_readlane_b32 s48, v32, 6
; VI-NEXT: v_readlane_b32 s39, v32, 5
; VI-NEXT: v_readlane_b32 s38, v32, 4
; VI-NEXT: v_readlane_b32 s37, v32, 3
; VI-NEXT: v_readlane_b32 s36, v32, 2
; VI-NEXT: v_readlane_b32 s35, v32, 1
; VI-NEXT: v_readlane_b32 s34, v32, 0
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b64 exec, s[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v12f64_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: v_writelane_b32 v32, s36, 0
; GFX9-NEXT: v_writelane_b32 v32, s37, 1
; GFX9-NEXT: v_writelane_b32 v32, s38, 2
; GFX9-NEXT: v_writelane_b32 v32, s39, 3
; GFX9-NEXT: v_writelane_b32 v32, s48, 4
; GFX9-NEXT: v_writelane_b32 v32, s49, 5
; GFX9-NEXT: v_writelane_b32 v32, s50, 6
; GFX9-NEXT: v_writelane_b32 v32, s51, 7
; GFX9-NEXT: v_writelane_b32 v32, s52, 8
; GFX9-NEXT: v_writelane_b32 v32, s53, 9
; GFX9-NEXT: v_writelane_b32 v32, s54, 10
; GFX9-NEXT: v_writelane_b32 v32, s55, 11
; GFX9-NEXT: s_lshr_b32 s41, s16, 16
; GFX9-NEXT: s_lshr_b32 s40, s17, 16
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
; GFX9-NEXT: v_readfirstlane_b32 s58, v8
; GFX9-NEXT: v_readfirstlane_b32 s57, v7
; GFX9-NEXT: v_readfirstlane_b32 s56, v6
; GFX9-NEXT: v_readfirstlane_b32 s72, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s76, v3
; GFX9-NEXT: v_readfirstlane_b32 s78, v2
; GFX9-NEXT: v_readfirstlane_b32 s88, v1
; GFX9-NEXT: s_pack_ll_b32_b16 s36, s16, s41
; GFX9-NEXT: v_readfirstlane_b32 s16, v0
; GFX9-NEXT: s_lshr_b32 s4, s29, 16
; GFX9-NEXT: s_lshr_b32 s5, s28, 16
; GFX9-NEXT: s_lshr_b32 s6, s27, 16
; GFX9-NEXT: s_lshr_b32 s7, s26, 16
; GFX9-NEXT: s_lshr_b32 s8, s25, 16
; GFX9-NEXT: s_lshr_b32 s9, s24, 16
; GFX9-NEXT: s_lshr_b32 s10, s23, 16
; GFX9-NEXT: s_lshr_b32 s11, s22, 16
; GFX9-NEXT: s_lshr_b32 s12, s21, 16
; GFX9-NEXT: s_lshr_b32 s13, s20, 16
; GFX9-NEXT: s_lshr_b32 s14, s19, 16
; GFX9-NEXT: s_lshr_b32 s15, s18, 16
; GFX9-NEXT: s_lshr_b32 s60, s59, 16
; GFX9-NEXT: s_lshr_b32 s61, s58, 16
; GFX9-NEXT: s_lshr_b32 s62, s57, 16
; GFX9-NEXT: s_lshr_b32 s63, s56, 16
; GFX9-NEXT: s_lshr_b32 s73, s72, 16
; GFX9-NEXT: s_lshr_b32 s75, s74, 16
; GFX9-NEXT: s_lshr_b32 s77, s76, 16
; GFX9-NEXT: s_lshr_b32 s79, s78, 16
; GFX9-NEXT: s_lshr_b32 s89, s88, 16
; GFX9-NEXT: s_pack_ll_b32_b16 s37, s17, s40
; GFX9-NEXT: s_lshr_b32 s17, s16, 16
; GFX9-NEXT: v_readfirstlane_b32 s40, v10
; GFX9-NEXT: s_cmp_lg_u32 s40, 0
; GFX9-NEXT: s_pack_ll_b32_b16 s38, s18, s15
; GFX9-NEXT: s_pack_ll_b32_b16 s39, s19, s14
; GFX9-NEXT: s_pack_ll_b32_b16 s40, s20, s13
; GFX9-NEXT: s_pack_ll_b32_b16 s41, s21, s12
; GFX9-NEXT: s_pack_ll_b32_b16 s42, s22, s11
; GFX9-NEXT: s_pack_ll_b32_b16 s43, s23, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s44, s24, s9
; GFX9-NEXT: s_pack_ll_b32_b16 s45, s25, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s46, s26, s7
; GFX9-NEXT: s_pack_ll_b32_b16 s47, s27, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s48, s28, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s49, s29, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s50, s16, s17
; GFX9-NEXT: s_pack_ll_b32_b16 s51, s88, s89
; GFX9-NEXT: s_pack_ll_b32_b16 s52, s78, s79
; GFX9-NEXT: s_pack_ll_b32_b16 s53, s76, s77
; GFX9-NEXT: s_pack_ll_b32_b16 s54, s74, s75
; GFX9-NEXT: s_pack_ll_b32_b16 s55, s72, s73
; GFX9-NEXT: s_pack_ll_b32_b16 s56, s56, s63
; GFX9-NEXT: s_pack_ll_b32_b16 s57, s57, s62
; GFX9-NEXT: s_pack_ll_b32_b16 s58, s58, s61
; GFX9-NEXT: s_pack_ll_b32_b16 s59, s59, s60
; GFX9-NEXT: s_cbranch_scc0 .LBB55_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB55_3
; GFX9-NEXT: .LBB55_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB55_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB55_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: v_mov_b32_e32 v23, 0x200
; GFX9-NEXT: v_pk_add_f16 v0, s36, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s37, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, s38, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, s39, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, s40, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, s41, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, s42, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, s43, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, s44, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, s45, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, s46, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, s47, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, s48, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, s49, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, s50, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, s51, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, s52, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, s53, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, s54, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, s55, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, s56, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, s57, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, s58, v23 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v23, s59, v23 op_sel_hi:[1,0]
; GFX9-NEXT: s_branch .LBB55_6
; GFX9-NEXT: .LBB55_5:
; GFX9-NEXT: v_mov_b32_e32 v0, s36
; GFX9-NEXT: v_mov_b32_e32 v1, s37
; GFX9-NEXT: v_mov_b32_e32 v2, s38
; GFX9-NEXT: v_mov_b32_e32 v3, s39
; GFX9-NEXT: v_mov_b32_e32 v4, s40
; GFX9-NEXT: v_mov_b32_e32 v5, s41
; GFX9-NEXT: v_mov_b32_e32 v6, s42
; GFX9-NEXT: v_mov_b32_e32 v7, s43
; GFX9-NEXT: v_mov_b32_e32 v8, s44
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_mov_b32_e32 v10, s46
; GFX9-NEXT: v_mov_b32_e32 v11, s47
; GFX9-NEXT: v_mov_b32_e32 v12, s48
; GFX9-NEXT: v_mov_b32_e32 v13, s49
; GFX9-NEXT: v_mov_b32_e32 v14, s50
; GFX9-NEXT: v_mov_b32_e32 v15, s51
; GFX9-NEXT: v_mov_b32_e32 v16, s52
; GFX9-NEXT: v_mov_b32_e32 v17, s53
; GFX9-NEXT: v_mov_b32_e32 v18, s54
; GFX9-NEXT: v_mov_b32_e32 v19, s55
; GFX9-NEXT: v_mov_b32_e32 v20, s56
; GFX9-NEXT: v_mov_b32_e32 v21, s57
; GFX9-NEXT: v_mov_b32_e32 v22, s58
; GFX9-NEXT: v_mov_b32_e32 v23, s59
; GFX9-NEXT: v_mov_b32_e32 v24, s60
; GFX9-NEXT: v_mov_b32_e32 v25, s61
; GFX9-NEXT: v_mov_b32_e32 v26, s62
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v28, s64
; GFX9-NEXT: v_mov_b32_e32 v29, s65
; GFX9-NEXT: v_mov_b32_e32 v30, s66
; GFX9-NEXT: v_mov_b32_e32 v31, s67
; GFX9-NEXT: .LBB55_6: ; %end
; GFX9-NEXT: v_readlane_b32 s55, v32, 11
; GFX9-NEXT: v_readlane_b32 s54, v32, 10
; GFX9-NEXT: v_readlane_b32 s53, v32, 9
; GFX9-NEXT: v_readlane_b32 s52, v32, 8
; GFX9-NEXT: v_readlane_b32 s51, v32, 7
; GFX9-NEXT: v_readlane_b32 s50, v32, 6
; GFX9-NEXT: v_readlane_b32 s49, v32, 5
; GFX9-NEXT: v_readlane_b32 s48, v32, 4
; GFX9-NEXT: v_readlane_b32 s39, v32, 3
; GFX9-NEXT: v_readlane_b32 s38, v32, 2
; GFX9-NEXT: v_readlane_b32 s37, v32, 1
; GFX9-NEXT: v_readlane_b32 s36, v32, 0
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: bitcast_v48f16_to_v12f64_scalar:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s44, v5
; GFX11-NEXT: v_readfirstlane_b32 s46, v4
; GFX11-NEXT: v_readfirstlane_b32 s58, v3
; GFX11-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-NEXT: v_readfirstlane_b32 s62, v0
; GFX11-NEXT: v_readfirstlane_b32 s72, v6
; GFX11-NEXT: s_lshr_b32 s41, s29, 16
; GFX11-NEXT: s_lshr_b32 s42, s28, 16
; GFX11-NEXT: s_lshr_b32 s15, s27, 16
; GFX11-NEXT: s_lshr_b32 s14, s26, 16
; GFX11-NEXT: s_lshr_b32 s13, s25, 16
; GFX11-NEXT: s_lshr_b32 s12, s24, 16
; GFX11-NEXT: s_lshr_b32 s11, s23, 16
; GFX11-NEXT: s_lshr_b32 s10, s22, 16
; GFX11-NEXT: s_lshr_b32 s9, s21, 16
; GFX11-NEXT: s_lshr_b32 s8, s20, 16
; GFX11-NEXT: s_lshr_b32 s7, s19, 16
; GFX11-NEXT: s_lshr_b32 s6, s18, 16
; GFX11-NEXT: s_lshr_b32 s5, s17, 16
; GFX11-NEXT: s_lshr_b32 s4, s16, 16
; GFX11-NEXT: s_lshr_b32 s43, s3, 16
; GFX11-NEXT: s_lshr_b32 s45, s2, 16
; GFX11-NEXT: s_lshr_b32 s47, s1, 16
; GFX11-NEXT: s_lshr_b32 s56, s0, 16
; GFX11-NEXT: s_lshr_b32 s57, s44, 16
; GFX11-NEXT: s_lshr_b32 s59, s46, 16
; GFX11-NEXT: s_lshr_b32 s63, s58, 16
; GFX11-NEXT: s_lshr_b32 s73, s60, 16
; GFX11-NEXT: s_lshr_b32 s74, s61, 16
; GFX11-NEXT: s_lshr_b32 s75, s62, 16
; GFX11-NEXT: s_mov_b32 s40, 0
; GFX11-NEXT: s_cmp_lg_u32 s72, 0
; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s56
; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s47
; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s45
; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s43
; GFX11-NEXT: s_pack_ll_b32_b16 s4, s16, s4
; GFX11-NEXT: s_pack_ll_b32_b16 s5, s17, s5
; GFX11-NEXT: s_pack_ll_b32_b16 s6, s18, s6
; GFX11-NEXT: s_pack_ll_b32_b16 s7, s19, s7
; GFX11-NEXT: s_pack_ll_b32_b16 s8, s20, s8
; GFX11-NEXT: s_pack_ll_b32_b16 s9, s21, s9
; GFX11-NEXT: s_pack_ll_b32_b16 s10, s22, s10
; GFX11-NEXT: s_pack_ll_b32_b16 s11, s23, s11
; GFX11-NEXT: s_pack_ll_b32_b16 s12, s24, s12
; GFX11-NEXT: s_pack_ll_b32_b16 s13, s25, s13
; GFX11-NEXT: s_pack_ll_b32_b16 s14, s26, s14
; GFX11-NEXT: s_pack_ll_b32_b16 s15, s27, s15
; GFX11-NEXT: s_pack_ll_b32_b16 s16, s28, s42
; GFX11-NEXT: s_pack_ll_b32_b16 s17, s29, s41
; GFX11-NEXT: s_pack_ll_b32_b16 s18, s62, s75
; GFX11-NEXT: s_pack_ll_b32_b16 s19, s61, s74
; GFX11-NEXT: s_pack_ll_b32_b16 s20, s60, s73
; GFX11-NEXT: s_pack_ll_b32_b16 s21, s58, s63
; GFX11-NEXT: s_pack_ll_b32_b16 s22, s46, s59
; GFX11-NEXT: s_pack_ll_b32_b16 s23, s44, s57
; GFX11-NEXT: s_cbranch_scc1 .LBB55_2
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: s_mov_b32 s40, -1
; GFX11-NEXT: .LBB55_2: ; %Flow
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s40, s40, exec_lo
; GFX11-NEXT: s_cselect_b32 s40, 1, 0
; GFX11-NEXT: s_cmp_lg_u32 s40, 1
; GFX11-NEXT: s_cbranch_scc1 .LBB55_4
; GFX11-NEXT: ; %bb.3: ; %cmp.true
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s20 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s21 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s22 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s23 op_sel_hi:[0,1]
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB55_4:
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
; GFX11-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <12 x double>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <12 x double>
br label %end
end:
%phi = phi <12 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <12 x double> %phi
}
define <48 x half> @bitcast_v48i16_to_v48f16(<48 x i16> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v48f16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v1
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v3
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v53
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v50
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v39
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v37
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v11
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v34
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v22
; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v18
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v16
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v14
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v12
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v10
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v8
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v0
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v54
; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v52
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v51
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v49
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v48
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v30
; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v38
; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v29
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v35
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v28
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v33
; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v27
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v25
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v41
; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v26
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v55
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v31
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr46
; SI-NEXT: ; implicit-def: $vgpr44
; SI-NEXT: ; implicit-def: $vgpr43
; SI-NEXT: ; implicit-def: $vgpr41
; SI-NEXT: ; implicit-def: $vgpr55
; SI-NEXT: ; implicit-def: $vgpr52
; SI-NEXT: ; implicit-def: $vgpr49
; SI-NEXT: ; implicit-def: $vgpr38
; SI-NEXT: ; implicit-def: $vgpr35
; SI-NEXT: ; implicit-def: $vgpr33
; SI-NEXT: ; implicit-def: $vgpr31
; SI-NEXT: ; kill: killed $vgpr24
; SI-NEXT: ; implicit-def: $vgpr24
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v53
; SI-NEXT: v_or_b32_e32 v46, v1, v24
; SI-NEXT: v_alignbit_b32 v1, v46, v58, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50
; SI-NEXT: v_or_b32_e32 v44, v1, v3
; SI-NEXT: v_alignbit_b32 v1, v44, v60, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v39
; SI-NEXT: v_or_b32_e32 v43, v1, v3
; SI-NEXT: v_alignbit_b32 v1, v43, v61, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37
; SI-NEXT: v_or_b32_e32 v41, v1, v3
; SI-NEXT: v_alignbit_b32 v1, v41, v36, 16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34
; SI-NEXT: v_or_b32_e32 v55, v1, v3
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_alignbit_b32 v1, v55, v51, 16
; SI-NEXT: v_or_b32_e32 v0, v0, v58
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v52, v1, v3
; SI-NEXT: v_or_b32_e32 v0, v0, v60
; SI-NEXT: v_alignbit_b32 v1, v52, v40, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
; SI-NEXT: v_or_b32_e32 v0, v0, v61
; SI-NEXT: v_or_b32_e32 v49, v1, v62
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
; SI-NEXT: v_alignbit_b32 v1, v49, v45, 16
; SI-NEXT: v_or_b32_e32 v0, v0, v36
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v38, v1, v57
; SI-NEXT: v_or_b32_e32 v0, v0, v51
; SI-NEXT: v_alignbit_b32 v1, v38, v59, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17
; SI-NEXT: v_or_b32_e32 v0, v0, v40
; SI-NEXT: v_or_b32_e32 v35, v1, v54
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
; SI-NEXT: v_alignbit_b32 v1, v35, v63, 16
; SI-NEXT: v_or_b32_e32 v0, v0, v45
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v33, v1, v47
; SI-NEXT: v_or_b32_e32 v0, v0, v59
; SI-NEXT: v_alignbit_b32 v1, v33, v48, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v16
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21
; SI-NEXT: v_or_b32_e32 v0, v0, v63
; SI-NEXT: v_or_b32_e32 v31, v1, v25
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v18
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: v_or_b32_e32 v0, v0, v48
; SI-NEXT: ; kill: killed $vgpr25
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: v_alignbit_b32 v1, v31, v42, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v20
; SI-NEXT: ; kill: killed $vgpr25
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v0, v0, v42
; SI-NEXT: ; kill: killed $vgpr25
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: v_or_b32_e32 v24, v1, v26
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v22
; SI-NEXT: ; kill: killed $vgpr25
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: v_alignbit_b32 v1, v24, v56, 16
; SI-NEXT: v_or_b32_e32 v0, v0, v56
; SI-NEXT: ; kill: killed $vgpr25
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: ; implicit-def: $vgpr0
; SI-NEXT: ; implicit-def: $vgpr1
; SI-NEXT: ; implicit-def: $vgpr2
; SI-NEXT: ; implicit-def: $vgpr3
; SI-NEXT: ; implicit-def: $vgpr4
; SI-NEXT: ; implicit-def: $vgpr5
; SI-NEXT: ; implicit-def: $vgpr6
; SI-NEXT: ; implicit-def: $vgpr7
; SI-NEXT: ; implicit-def: $vgpr8
; SI-NEXT: ; implicit-def: $vgpr9
; SI-NEXT: ; implicit-def: $vgpr10
; SI-NEXT: ; implicit-def: $vgpr11
; SI-NEXT: ; implicit-def: $vgpr12
; SI-NEXT: ; implicit-def: $vgpr13
; SI-NEXT: ; implicit-def: $vgpr14
; SI-NEXT: ; implicit-def: $vgpr15
; SI-NEXT: ; implicit-def: $vgpr16
; SI-NEXT: ; implicit-def: $vgpr17
; SI-NEXT: ; implicit-def: $vgpr18
; SI-NEXT: ; implicit-def: $vgpr19
; SI-NEXT: ; implicit-def: $vgpr20
; SI-NEXT: ; implicit-def: $vgpr21
; SI-NEXT: ; implicit-def: $vgpr22
; SI-NEXT: ; implicit-def: $vgpr23
; SI-NEXT: ; implicit-def: $vgpr58
; SI-NEXT: ; implicit-def: $vgpr60
; SI-NEXT: ; implicit-def: $vgpr61
; SI-NEXT: ; implicit-def: $vgpr36
; SI-NEXT: ; implicit-def: $vgpr51
; SI-NEXT: ; kill: killed $vgpr25
; SI-NEXT: ; implicit-def: $vgpr40
; SI-NEXT: ; implicit-def: $vgpr62
; SI-NEXT: ; implicit-def: $vgpr45
; SI-NEXT: ; implicit-def: $vgpr57
; SI-NEXT: ; implicit-def: $vgpr59
; SI-NEXT: ; implicit-def: $vgpr54
; SI-NEXT: ; implicit-def: $vgpr63
; SI-NEXT: ; implicit-def: $vgpr47
; SI-NEXT: ; implicit-def: $vgpr48
; SI-NEXT: ; implicit-def: $vgpr25
; SI-NEXT: ; implicit-def: $vgpr42
; SI-NEXT: ; implicit-def: $vgpr26
; SI-NEXT: ; implicit-def: $vgpr56
; SI-NEXT: .LBB56_2: ; %Flow
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB56_4
; SI-NEXT: ; %bb.3: ; %cmp.true
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v56, v22
; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 3, v23
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v20
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v22, v26, v22
; SI-NEXT: v_or_b32_e32 v20, v42, v20
; SI-NEXT: s_waitcnt expcnt(2)
; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v22
; SI-NEXT: v_add_i32_e32 v22, vcc, 0x30000, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 3, v21
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v18
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v20, v25, v20
; SI-NEXT: v_or_b32_e32 v18, v48, v18
; SI-NEXT: v_add_i32_e32 v31, vcc, 0x30000, v20
; SI-NEXT: v_add_i32_e32 v20, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v19
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v18, v47, v18
; SI-NEXT: v_or_b32_e32 v16, v63, v16
; SI-NEXT: v_add_i32_e32 v33, vcc, 0x30000, v18
; SI-NEXT: v_add_i32_e32 v18, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v17
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v16, v54, v16
; SI-NEXT: v_or_b32_e32 v14, v59, v14
; SI-NEXT: v_add_i32_e32 v35, vcc, 0x30000, v16
; SI-NEXT: v_add_i32_e32 v16, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v14, v57, v14
; SI-NEXT: v_or_b32_e32 v12, v45, v12
; SI-NEXT: v_add_i32_e32 v38, vcc, 0x30000, v14
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v12, v62, v12
; SI-NEXT: v_or_b32_e32 v10, v40, v10
; SI-NEXT: v_add_i32_e32 v49, vcc, 0x30000, v12
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v51, v8
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v36, v6
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v61, v4
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v60, v2
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v0, v58, v0
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v49
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v38
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v35
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v10, v11, v10
; SI-NEXT: v_add_i32_e32 v52, vcc, 0x30000, v10
; SI-NEXT: v_add_i32_e32 v10, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v52
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v8, v9, v8
; SI-NEXT: v_add_i32_e32 v55, vcc, 0x30000, v8
; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v55
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v6, v7, v6
; SI-NEXT: v_add_i32_e32 v41, vcc, 0x30000, v6
; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v41
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v4, v5, v4
; SI-NEXT: v_add_i32_e32 v43, vcc, 0x30000, v4
; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v43
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_or_b32_e32 v2, v3, v2
; SI-NEXT: v_add_i32_e32 v44, vcc, 0x30000, v2
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x30000, v0
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v44
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: v_add_i32_e32 v46, vcc, 0x30000, v0
; SI-NEXT: v_alignbit_b32 v0, v46, v2, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v44, v4, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v43, v6, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v41, v8, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v55, v10, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v52, v12, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v49, v14, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v38, v16, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v35, v18, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v33, v20, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v31, v22, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_alignbit_b32 v0, v24, v27, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v31
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v46
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v33
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v24
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; SI-NEXT: .LBB56_4: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v53
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v50
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v39
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v37
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v32
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v30
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v28
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v27
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(13)
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v46
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(12)
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; SI-NEXT: s_waitcnt vmcnt(11)
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; SI-NEXT: s_waitcnt vmcnt(10)
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; SI-NEXT: s_waitcnt vmcnt(9)
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; SI-NEXT: s_waitcnt vmcnt(8)
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; SI-NEXT: s_waitcnt vmcnt(7)
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; SI-NEXT: s_waitcnt vmcnt(6)
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; SI-NEXT: s_waitcnt vmcnt(5)
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; SI-NEXT: s_waitcnt vmcnt(4)
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_or_b32_e32 v2, v2, v3
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v44
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_or_b32_e32 v4, v4, v5
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v43
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_or_b32_e32 v6, v6, v7
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v41
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(14)
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_or_b32_e32 v8, v8, v9
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v55
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_or_b32_e32 v10, v10, v11
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v52
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_or_b32_e32 v12, v12, v13
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v49
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_or_b32_e32 v14, v14, v15
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v38
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_or_b32_e32 v16, v16, v17
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v35
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_or_b32_e32 v18, v18, v19
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v33
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_or_b32_e32 v20, v20, v21
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v31
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_or_b32_e32 v22, v22, v23
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v24
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v48f16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB56_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_u16_e32 v0, 3, v0
; VI-NEXT: v_add_u16_e32 v55, 3, v55
; VI-NEXT: v_add_u16_e32 v1, 3, v1
; VI-NEXT: v_add_u16_e32 v54, 3, v54
; VI-NEXT: v_add_u16_e32 v2, 3, v2
; VI-NEXT: v_add_u16_e32 v53, 3, v53
; VI-NEXT: v_add_u16_e32 v3, 3, v3
; VI-NEXT: v_add_u16_e32 v52, 3, v52
; VI-NEXT: v_add_u16_e32 v4, 3, v4
; VI-NEXT: v_add_u16_e32 v24, 3, v24
; VI-NEXT: v_add_u16_e32 v5, 3, v5
; VI-NEXT: v_add_u16_e32 v51, 3, v51
; VI-NEXT: v_add_u16_e32 v6, 3, v6
; VI-NEXT: v_add_u16_e32 v50, 3, v50
; VI-NEXT: v_add_u16_e32 v7, 3, v7
; VI-NEXT: v_add_u16_e32 v49, 3, v49
; VI-NEXT: v_add_u16_e32 v8, 3, v8
; VI-NEXT: v_add_u16_e32 v48, 3, v48
; VI-NEXT: v_add_u16_e32 v9, 3, v9
; VI-NEXT: v_add_u16_e32 v39, 3, v39
; VI-NEXT: v_add_u16_e32 v10, 3, v10
; VI-NEXT: v_add_u16_e32 v38, 3, v38
; VI-NEXT: v_add_u16_e32 v11, 3, v11
; VI-NEXT: v_add_u16_e32 v37, 3, v37
; VI-NEXT: v_add_u16_e32 v12, 3, v12
; VI-NEXT: v_add_u16_e32 v36, 3, v36
; VI-NEXT: v_add_u16_e32 v13, 3, v13
; VI-NEXT: v_add_u16_e32 v35, 3, v35
; VI-NEXT: v_add_u16_e32 v14, 3, v14
; VI-NEXT: v_add_u16_e32 v34, 3, v34
; VI-NEXT: v_add_u16_e32 v15, 3, v15
; VI-NEXT: v_add_u16_e32 v33, 3, v33
; VI-NEXT: v_add_u16_e32 v16, 3, v16
; VI-NEXT: v_add_u16_e32 v32, 3, v32
; VI-NEXT: v_add_u16_e32 v17, 3, v17
; VI-NEXT: v_add_u16_e32 v31, 3, v31
; VI-NEXT: v_add_u16_e32 v18, 3, v18
; VI-NEXT: v_add_u16_e32 v30, 3, v30
; VI-NEXT: v_add_u16_e32 v19, 3, v19
; VI-NEXT: v_add_u16_e32 v29, 3, v29
; VI-NEXT: v_add_u16_e32 v20, 3, v20
; VI-NEXT: v_add_u16_e32 v28, 3, v28
; VI-NEXT: v_add_u16_e32 v21, 3, v21
; VI-NEXT: v_add_u16_e32 v27, 3, v27
; VI-NEXT: v_add_u16_e32 v22, 3, v22
; VI-NEXT: v_add_u16_e32 v26, 3, v26
; VI-NEXT: v_add_u16_e32 v23, 3, v23
; VI-NEXT: v_add_u16_e32 v25, 3, v25
; VI-NEXT: .LBB56_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v4, v4, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v51
; VI-NEXT: v_or_b32_sdwa v5, v5, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v50
; VI-NEXT: v_or_b32_sdwa v6, v6, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v49
; VI-NEXT: v_or_b32_sdwa v7, v7, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v48
; VI-NEXT: v_or_b32_sdwa v8, v8, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v39
; VI-NEXT: v_or_b32_sdwa v9, v9, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v38
; VI-NEXT: v_or_b32_sdwa v10, v10, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v37
; VI-NEXT: v_or_b32_sdwa v11, v11, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
; VI-NEXT: v_or_b32_sdwa v12, v12, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v35
; VI-NEXT: v_or_b32_sdwa v13, v13, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v34
; VI-NEXT: v_or_b32_sdwa v14, v14, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v33
; VI-NEXT: v_or_b32_sdwa v15, v15, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; VI-NEXT: v_or_b32_sdwa v16, v16, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v31
; VI-NEXT: v_or_b32_sdwa v17, v17, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
; VI-NEXT: v_or_b32_sdwa v18, v18, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v29
; VI-NEXT: v_or_b32_sdwa v19, v19, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v28
; VI-NEXT: v_or_b32_sdwa v20, v20, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v27
; VI-NEXT: v_or_b32_sdwa v21, v21, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_or_b32_sdwa v22, v22, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v25
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v48f16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v5
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB56_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v23, v55, v23, s6
; GFX9-NEXT: v_perm_b32 v22, v54, v22, s6
; GFX9-NEXT: v_perm_b32 v21, v53, v21, s6
; GFX9-NEXT: v_perm_b32 v20, v52, v20, s6
; GFX9-NEXT: v_perm_b32 v19, v51, v19, s6
; GFX9-NEXT: v_perm_b32 v18, v50, v18, s6
; GFX9-NEXT: v_perm_b32 v17, v49, v17, s6
; GFX9-NEXT: v_perm_b32 v16, v48, v16, s6
; GFX9-NEXT: v_perm_b32 v15, v39, v15, s6
; GFX9-NEXT: v_perm_b32 v14, v38, v14, s6
; GFX9-NEXT: v_perm_b32 v13, v37, v13, s6
; GFX9-NEXT: v_perm_b32 v12, v36, v12, s6
; GFX9-NEXT: v_perm_b32 v11, v35, v11, s6
; GFX9-NEXT: v_perm_b32 v10, v34, v10, s6
; GFX9-NEXT: v_perm_b32 v9, v33, v9, s6
; GFX9-NEXT: v_perm_b32 v8, v32, v8, s6
; GFX9-NEXT: v_perm_b32 v7, v31, v7, s6
; GFX9-NEXT: v_perm_b32 v6, v30, v6, s6
; GFX9-NEXT: v_perm_b32 v5, v28, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v29, v4, s6
; GFX9-NEXT: v_perm_b32 v3, v27, v3, s6
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s6
; GFX9-NEXT: v_perm_b32 v1, v25, v1, s6
; GFX9-NEXT: v_perm_b32 v0, v24, v0, s6
; GFX9-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v23
; GFX9-NEXT: .LBB56_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v24, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v25, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v27, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v29, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v28, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v30, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v31, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v32, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v33, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v34, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v35, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v36, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v37, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v38, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v39, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v48, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v49, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v50, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v51, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v52, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v53, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v54, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v55, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v48f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: .LBB56_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v48f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB56_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v64, v23, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v54, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v53, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v51, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v50, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v49, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v39, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v38, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v37, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v34, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v31, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v30, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v25, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v26, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v27, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v28, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v29, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
; GFX11-FAKE16-NEXT: .LBB56_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v25, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v26, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v27, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v28, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v29, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v30, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v31, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v34, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v37, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v38, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v39, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v49, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v50, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v51, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v53, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v54, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v64, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define inreg <48 x half> @bitcast_v48i16_to_v48f16_scalar(<48 x i16> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48i16_to_v48f16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_writelane_b32 v24, s34, 0
; SI-NEXT: v_writelane_b32 v24, s35, 1
; SI-NEXT: v_writelane_b32 v24, s36, 2
; SI-NEXT: v_writelane_b32 v24, s37, 3
; SI-NEXT: v_writelane_b32 v24, s38, 4
; SI-NEXT: v_writelane_b32 v24, s39, 5
; SI-NEXT: v_writelane_b32 v24, s48, 6
; SI-NEXT: v_writelane_b32 v24, s49, 7
; SI-NEXT: v_writelane_b32 v24, s50, 8
; SI-NEXT: v_writelane_b32 v24, s51, 9
; SI-NEXT: v_writelane_b32 v24, s52, 10
; SI-NEXT: v_writelane_b32 v24, s53, 11
; SI-NEXT: v_writelane_b32 v24, s30, 12
; SI-NEXT: v_writelane_b32 v24, s31, 13
; SI-NEXT: s_lshr_b32 s8, s24, 16
; SI-NEXT: ; implicit-def: $vgpr25 : SGPR spill to VGPR lane
; SI-NEXT: s_lshr_b32 s6, s26, 16
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_writelane_b32 v25, s8, 0
; SI-NEXT: s_lshr_b32 s4, s28, 16
; SI-NEXT: v_readfirstlane_b32 s58, v0
; SI-NEXT: v_writelane_b32 v25, s6, 1
; SI-NEXT: s_lshr_b32 s57, s58, 16
; SI-NEXT: v_writelane_b32 v25, s4, 2
; SI-NEXT: v_readfirstlane_b32 s47, v2
; SI-NEXT: v_writelane_b32 v25, s57, 3
; SI-NEXT: s_lshr_b32 s56, s47, 16
; SI-NEXT: v_writelane_b32 v25, s58, 4
; SI-NEXT: v_readfirstlane_b32 s45, v4
; SI-NEXT: v_writelane_b32 v25, s56, 5
; SI-NEXT: s_lshr_b32 s41, s45, 16
; SI-NEXT: v_writelane_b32 v25, s47, 6
; SI-NEXT: v_readfirstlane_b32 s48, v6
; SI-NEXT: v_writelane_b32 v25, s41, 7
; SI-NEXT: s_lshr_b32 s15, s48, 16
; SI-NEXT: v_writelane_b32 v25, s45, 8
; SI-NEXT: v_readfirstlane_b32 s43, v1
; SI-NEXT: v_writelane_b32 v25, s15, 9
; SI-NEXT: v_readfirstlane_b32 s13, v3
; SI-NEXT: v_writelane_b32 v25, s43, 10
; SI-NEXT: v_readfirstlane_b32 s11, v5
; SI-NEXT: v_writelane_b32 v25, s13, 11
; SI-NEXT: v_readfirstlane_b32 s5, v9
; SI-NEXT: v_readfirstlane_b32 s37, v8
; SI-NEXT: v_readfirstlane_b32 s9, v7
; SI-NEXT: v_writelane_b32 v25, s11, 12
; SI-NEXT: s_lshr_b32 s89, s29, 16
; SI-NEXT: s_lshr_b32 s79, s27, 16
; SI-NEXT: s_lshr_b32 s77, s25, 16
; SI-NEXT: s_lshr_b32 s75, s23, 16
; SI-NEXT: s_lshr_b32 s39, s22, 16
; SI-NEXT: s_lshr_b32 s73, s21, 16
; SI-NEXT: s_lshr_b32 s38, s20, 16
; SI-NEXT: s_lshr_b32 s63, s19, 16
; SI-NEXT: s_lshr_b32 s50, s18, 16
; SI-NEXT: s_lshr_b32 s61, s17, 16
; SI-NEXT: s_lshr_b32 s36, s16, 16
; SI-NEXT: s_lshr_b32 s31, s5, 16
; SI-NEXT: s_lshr_b32 s7, s37, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s9, 16
; SI-NEXT: s_lshr_b32 s51, s11, 16
; SI-NEXT: s_lshr_b32 s49, s13, 16
; SI-NEXT: s_lshr_b32 s91, s43, 16
; SI-NEXT: v_readfirstlane_b32 s10, v10
; SI-NEXT: v_writelane_b32 v25, s9, 13
; SI-NEXT: s_cmp_lg_u32 s10, 0
; SI-NEXT: v_writelane_b32 v25, s5, 14
; SI-NEXT: v_writelane_b32 v25, s7, 15
; SI-NEXT: s_cbranch_scc0 .LBB57_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_and_b32 s10, s16, 0xffff
; SI-NEXT: s_lshl_b32 s60, s36, 16
; SI-NEXT: s_or_b32 s46, s10, s60
; SI-NEXT: s_and_b32 s10, s18, 0xffff
; SI-NEXT: s_lshl_b32 s62, s50, 16
; SI-NEXT: s_or_b32 s44, s10, s62
; SI-NEXT: s_and_b32 s10, s20, 0xffff
; SI-NEXT: s_lshl_b32 s72, s38, 16
; SI-NEXT: s_or_b32 s42, s10, s72
; SI-NEXT: s_and_b32 s10, s22, 0xffff
; SI-NEXT: s_lshl_b32 s74, s39, 16
; SI-NEXT: s_lshl_b32 s76, s8, 16
; SI-NEXT: s_and_b32 s8, s26, 0xffff
; SI-NEXT: s_lshl_b32 s78, s6, 16
; SI-NEXT: s_lshl_b32 s88, s4, 16
; SI-NEXT: s_and_b32 s4, s58, 0xffff
; SI-NEXT: s_lshl_b32 s90, s57, 16
; SI-NEXT: s_or_b32 s40, s10, s74
; SI-NEXT: s_and_b32 s10, s24, 0xffff
; SI-NEXT: s_or_b32 s12, s8, s78
; SI-NEXT: s_and_b32 s6, s28, 0xffff
; SI-NEXT: s_or_b32 s8, s4, s90
; SI-NEXT: s_and_b32 s4, s47, 0xffff
; SI-NEXT: s_lshl_b32 s92, s56, 16
; SI-NEXT: s_or_b32 s14, s10, s76
; SI-NEXT: s_or_b32 s10, s6, s88
; SI-NEXT: s_or_b32 s6, s4, s92
; SI-NEXT: s_and_b32 s4, s45, 0xffff
; SI-NEXT: s_lshl_b32 s58, s41, 16
; SI-NEXT: s_and_b32 s41, s17, 0xffff
; SI-NEXT: s_lshl_b32 s45, s61, 16
; SI-NEXT: s_lshl_b32 s56, s15, 16
; SI-NEXT: s_mov_b32 s15, s61
; SI-NEXT: s_or_b32 s61, s41, s45
; SI-NEXT: s_and_b32 s45, s19, 0xffff
; SI-NEXT: s_lshl_b32 s47, s63, 16
; SI-NEXT: s_mov_b32 s41, s63
; SI-NEXT: s_or_b32 s63, s45, s47
; SI-NEXT: s_and_b32 s45, s21, 0xffff
; SI-NEXT: s_lshl_b32 s47, s73, 16
; SI-NEXT: s_mov_b32 s94, s73
; SI-NEXT: s_or_b32 s73, s45, s47
; SI-NEXT: s_and_b32 s45, s23, 0xffff
; SI-NEXT: s_lshl_b32 s47, s75, 16
; SI-NEXT: s_mov_b32 vcc_lo, s75
; SI-NEXT: s_or_b32 s75, s45, s47
; SI-NEXT: s_and_b32 s45, s25, 0xffff
; SI-NEXT: s_lshl_b32 s47, s77, 16
; SI-NEXT: s_mov_b32 s30, s77
; SI-NEXT: s_or_b32 s77, s45, s47
; SI-NEXT: s_and_b32 s45, s27, 0xffff
; SI-NEXT: s_lshl_b32 s47, s79, 16
; SI-NEXT: s_mov_b32 s34, s79
; SI-NEXT: s_or_b32 s79, s45, s47
; SI-NEXT: s_and_b32 s45, s29, 0xffff
; SI-NEXT: s_lshl_b32 s47, s89, 16
; SI-NEXT: s_mov_b32 s35, s89
; SI-NEXT: s_or_b32 s89, s45, s47
; SI-NEXT: s_and_b32 s43, s43, 0xffff
; SI-NEXT: s_lshl_b32 s45, s91, 16
; SI-NEXT: s_mov_b32 s95, s37
; SI-NEXT: s_mov_b32 s37, s48
; SI-NEXT: s_mov_b32 s48, s91
; SI-NEXT: s_or_b32 s91, s43, s45
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s43, s49, 16
; SI-NEXT: s_or_b32 s93, s13, s43
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_lshl_b32 s13, s51, 16
; SI-NEXT: s_or_b32 s59, s11, s13
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s11, vcc_hi, 16
; SI-NEXT: s_or_b32 s57, s9, s11
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s9, s31, 16
; SI-NEXT: s_or_b32 s53, s5, s9
; SI-NEXT: s_mov_b32 s45, s63
; SI-NEXT: s_lshr_b64 s[62:63], s[62:63], 16
; SI-NEXT: s_mov_b32 s43, s73
; SI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16
; SI-NEXT: s_mov_b32 s9, s91
; SI-NEXT: s_lshr_b64 s[90:91], s[90:91], 16
; SI-NEXT: s_mov_b32 s47, s61
; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
; SI-NEXT: s_mov_b32 s63, s41
; SI-NEXT: s_mov_b32 s73, s94
; SI-NEXT: s_mov_b32 s41, s75
; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
; SI-NEXT: s_mov_b32 s91, s48
; SI-NEXT: s_mov_b32 s48, s37
; SI-NEXT: s_mov_b32 s37, s95
; SI-NEXT: s_lshr_b64 s[94:95], s[58:59], 16
; SI-NEXT: s_or_b32 s4, s4, s58
; SI-NEXT: s_lshl_b32 s52, s7, 16
; SI-NEXT: s_mov_b32 s61, s15
; SI-NEXT: s_mov_b32 s75, vcc_lo
; SI-NEXT: s_mov_b32 s15, s77
; SI-NEXT: s_lshr_b64 s[76:77], s[76:77], 16
; SI-NEXT: s_and_b32 s58, s48, 0xffff
; SI-NEXT: s_mov_b32 s95, vcc_hi
; SI-NEXT: s_lshr_b64 vcc, s[56:57], 16
; SI-NEXT: s_mov_b32 s77, s30
; SI-NEXT: s_mov_b32 s13, s79
; SI-NEXT: s_lshr_b64 s[78:79], s[78:79], 16
; SI-NEXT: s_mov_b32 s11, s89
; SI-NEXT: s_lshr_b64 s[88:89], s[88:89], 16
; SI-NEXT: s_or_b32 s58, s58, s56
; SI-NEXT: s_mov_b32 vcc_hi, s95
; SI-NEXT: s_and_b32 s56, s37, 0xffff
; SI-NEXT: s_mov_b32 s95, s31
; SI-NEXT: s_lshr_b64 s[30:31], s[52:53], 16
; SI-NEXT: s_mov_b32 s79, s34
; SI-NEXT: s_mov_b32 s89, s35
; SI-NEXT: s_mov_b32 s7, s93
; SI-NEXT: s_lshr_b64 s[92:93], s[92:93], 16
; SI-NEXT: s_mov_b32 s5, s59
; SI-NEXT: s_mov_b32 s59, s57
; SI-NEXT: s_or_b32 s56, s56, s52
; SI-NEXT: s_mov_b32 s57, s53
; SI-NEXT: s_mov_b32 s31, s95
; SI-NEXT: s_mov_b64 s[34:35], 0
; SI-NEXT: s_branch .LBB57_3
; SI-NEXT: .LBB57_2:
; SI-NEXT: s_mov_b64 s[34:35], -1
; SI-NEXT: ; implicit-def: $sgpr46
; SI-NEXT: ; implicit-def: $sgpr60
; SI-NEXT: ; implicit-def: $sgpr44
; SI-NEXT: ; implicit-def: $sgpr62
; SI-NEXT: ; implicit-def: $sgpr42
; SI-NEXT: ; implicit-def: $sgpr72
; SI-NEXT: ; implicit-def: $sgpr40
; SI-NEXT: ; implicit-def: $sgpr74
; SI-NEXT: ; implicit-def: $sgpr14
; SI-NEXT: ; implicit-def: $sgpr76
; SI-NEXT: ; implicit-def: $sgpr12
; SI-NEXT: ; implicit-def: $sgpr78
; SI-NEXT: ; implicit-def: $sgpr10
; SI-NEXT: ; implicit-def: $sgpr88
; SI-NEXT: ; implicit-def: $sgpr8
; SI-NEXT: ; implicit-def: $sgpr90
; SI-NEXT: ; implicit-def: $sgpr6
; SI-NEXT: ; implicit-def: $sgpr92
; SI-NEXT: ; implicit-def: $sgpr4
; SI-NEXT: ; implicit-def: $sgpr94
; SI-NEXT: ; implicit-def: $sgpr58
; SI-NEXT: ; implicit-def: $vcc_lo
; SI-NEXT: ; implicit-def: $sgpr56
; SI-NEXT: ; implicit-def: $sgpr30
; SI-NEXT: .LBB57_3: ; %Flow
; SI-NEXT: s_and_b64 s[34:35], s[34:35], exec
; SI-NEXT: s_cselect_b32 s95, 1, 0
; SI-NEXT: s_cmp_lg_u32 s95, 1
; SI-NEXT: s_cbranch_scc1 .LBB57_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: s_add_i32 s4, s37, 3
; SI-NEXT: s_and_b32 s5, s4, 0xffff
; SI-NEXT: v_readlane_b32 s4, v25, 15
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_add_i32 s56, s4, 0x30000
; SI-NEXT: v_readlane_b32 s4, v25, 14
; SI-NEXT: s_add_i32 s4, s4, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, s31, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s57, s4, 0x30000
; SI-NEXT: s_add_i32 s4, s48, 3
; SI-NEXT: s_and_b32 s5, s4, 0xffff
; SI-NEXT: v_readlane_b32 s4, v25, 9
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: s_add_i32 s58, s4, 0x30000
; SI-NEXT: v_readlane_b32 s4, v25, 13
; SI-NEXT: s_add_i32 s4, s4, 3
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s5, vcc_hi, 16
; SI-NEXT: s_or_b32 s4, s5, s4
; SI-NEXT: s_add_i32 s59, s4, 0x30000
; SI-NEXT: v_readlane_b32 s4, v25, 8
; SI-NEXT: s_add_i32 s4, s4, 3
; SI-NEXT: s_and_b32 s5, s4, 0xffff
; SI-NEXT: v_readlane_b32 s4, v25, 7
; SI-NEXT: s_lshl_b32 s4, s4, 16
; SI-NEXT: s_or_b32 s4, s4, s5
; SI-NEXT: v_readlane_b32 s5, v25, 12
; SI-NEXT: s_add_i32 s5, s5, 3
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s6, s51, 16
; SI-NEXT: s_or_b32 s5, s6, s5
; SI-NEXT: v_readlane_b32 s6, v25, 6
; SI-NEXT: s_add_i32 s6, s6, 3
; SI-NEXT: s_and_b32 s7, s6, 0xffff
; SI-NEXT: v_readlane_b32 s6, v25, 5
; SI-NEXT: s_lshl_b32 s6, s6, 16
; SI-NEXT: s_or_b32 s6, s6, s7
; SI-NEXT: v_readlane_b32 s7, v25, 11
; SI-NEXT: s_add_i32 s7, s7, 3
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s8, s49, 16
; SI-NEXT: s_or_b32 s7, s8, s7
; SI-NEXT: v_readlane_b32 s8, v25, 4
; SI-NEXT: s_add_i32 s8, s8, 3
; SI-NEXT: s_and_b32 s9, s8, 0xffff
; SI-NEXT: v_readlane_b32 s8, v25, 3
; SI-NEXT: s_lshl_b32 s8, s8, 16
; SI-NEXT: s_or_b32 s8, s8, s9
; SI-NEXT: v_readlane_b32 s9, v25, 10
; SI-NEXT: s_add_i32 s9, s9, 3
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s10, s91, 16
; SI-NEXT: s_or_b32 s9, s10, s9
; SI-NEXT: s_add_i32 s28, s28, 3
; SI-NEXT: v_readlane_b32 s10, v25, 2
; SI-NEXT: s_and_b32 s11, s28, 0xffff
; SI-NEXT: s_lshl_b32 s10, s10, 16
; SI-NEXT: s_add_i32 s29, s29, 3
; SI-NEXT: s_or_b32 s10, s10, s11
; SI-NEXT: s_and_b32 s11, s29, 0xffff
; SI-NEXT: s_lshl_b32 s12, s89, 16
; SI-NEXT: s_or_b32 s11, s12, s11
; SI-NEXT: s_add_i32 s26, s26, 3
; SI-NEXT: v_readlane_b32 s12, v25, 1
; SI-NEXT: s_and_b32 s13, s26, 0xffff
; SI-NEXT: s_lshl_b32 s12, s12, 16
; SI-NEXT: s_add_i32 s27, s27, 3
; SI-NEXT: s_or_b32 s12, s12, s13
; SI-NEXT: s_and_b32 s13, s27, 0xffff
; SI-NEXT: s_lshl_b32 s14, s79, 16
; SI-NEXT: s_or_b32 s13, s14, s13
; SI-NEXT: s_add_i32 s24, s24, 3
; SI-NEXT: v_readlane_b32 s14, v25, 0
; SI-NEXT: s_and_b32 s15, s24, 0xffff
; SI-NEXT: s_lshl_b32 s14, s14, 16
; SI-NEXT: s_add_i32 s25, s25, 3
; SI-NEXT: s_or_b32 s14, s14, s15
; SI-NEXT: s_and_b32 s15, s25, 0xffff
; SI-NEXT: s_lshl_b32 s24, s77, 16
; SI-NEXT: s_add_i32 s22, s22, 3
; SI-NEXT: s_or_b32 s15, s24, s15
; SI-NEXT: s_and_b32 s22, s22, 0xffff
; SI-NEXT: s_lshl_b32 s24, s39, 16
; SI-NEXT: s_or_b32 s22, s24, s22
; SI-NEXT: s_add_i32 s23, s23, 3
; SI-NEXT: s_add_i32 s40, s22, 0x30000
; SI-NEXT: s_and_b32 s22, s23, 0xffff
; SI-NEXT: s_lshl_b32 s23, s75, 16
; SI-NEXT: s_or_b32 s22, s23, s22
; SI-NEXT: s_add_i32 s20, s20, 3
; SI-NEXT: s_add_i32 s41, s22, 0x30000
; SI-NEXT: s_and_b32 s20, s20, 0xffff
; SI-NEXT: s_lshl_b32 s22, s38, 16
; SI-NEXT: s_or_b32 s20, s22, s20
; SI-NEXT: s_add_i32 s21, s21, 3
; SI-NEXT: s_add_i32 s42, s20, 0x30000
; SI-NEXT: s_and_b32 s20, s21, 0xffff
; SI-NEXT: s_lshl_b32 s21, s73, 16
; SI-NEXT: s_or_b32 s20, s21, s20
; SI-NEXT: s_add_i32 s18, s18, 3
; SI-NEXT: s_add_i32 s43, s20, 0x30000
; SI-NEXT: s_and_b32 s18, s18, 0xffff
; SI-NEXT: s_lshl_b32 s20, s50, 16
; SI-NEXT: s_or_b32 s18, s20, s18
; SI-NEXT: s_add_i32 s19, s19, 3
; SI-NEXT: s_add_i32 s44, s18, 0x30000
; SI-NEXT: s_and_b32 s18, s19, 0xffff
; SI-NEXT: s_lshl_b32 s19, s63, 16
; SI-NEXT: s_or_b32 s18, s19, s18
; SI-NEXT: s_add_i32 s16, s16, 3
; SI-NEXT: s_add_i32 s45, s18, 0x30000
; SI-NEXT: s_and_b32 s16, s16, 0xffff
; SI-NEXT: s_lshl_b32 s18, s36, 16
; SI-NEXT: s_or_b32 s16, s18, s16
; SI-NEXT: s_add_i32 s17, s17, 3
; SI-NEXT: s_add_i32 s46, s16, 0x30000
; SI-NEXT: s_and_b32 s16, s17, 0xffff
; SI-NEXT: s_lshl_b32 s17, s61, 16
; SI-NEXT: s_or_b32 s16, s17, s16
; SI-NEXT: s_add_i32 s8, s8, 0x30000
; SI-NEXT: s_add_i32 s9, s9, 0x30000
; SI-NEXT: s_add_i32 s10, s10, 0x30000
; SI-NEXT: s_add_i32 s11, s11, 0x30000
; SI-NEXT: s_add_i32 s12, s12, 0x30000
; SI-NEXT: s_add_i32 s13, s13, 0x30000
; SI-NEXT: s_add_i32 s14, s14, 0x30000
; SI-NEXT: s_add_i32 s15, s15, 0x30000
; SI-NEXT: s_add_i32 s47, s16, 0x30000
; SI-NEXT: s_add_i32 s4, s4, 0x30000
; SI-NEXT: s_add_i32 s5, s5, 0x30000
; SI-NEXT: s_add_i32 s6, s6, 0x30000
; SI-NEXT: s_add_i32 s7, s7, 0x30000
; SI-NEXT: s_lshr_b64 s[60:61], s[46:47], 16
; SI-NEXT: s_lshr_b64 s[62:63], s[44:45], 16
; SI-NEXT: s_lshr_b64 s[72:73], s[42:43], 16
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 16
; SI-NEXT: s_lshr_b64 s[76:77], s[14:15], 16
; SI-NEXT: s_lshr_b64 s[78:79], s[12:13], 16
; SI-NEXT: s_lshr_b64 s[88:89], s[10:11], 16
; SI-NEXT: s_lshr_b64 s[90:91], s[8:9], 16
; SI-NEXT: s_lshr_b64 vcc, s[58:59], 16
; SI-NEXT: s_lshr_b64 s[30:31], s[56:57], 16
; SI-NEXT: s_lshr_b64 s[92:93], s[6:7], 16
; SI-NEXT: s_lshr_b64 s[94:95], s[4:5], 16
; SI-NEXT: s_lshr_b32 s61, s47, 16
; SI-NEXT: s_lshr_b32 s63, s45, 16
; SI-NEXT: s_lshr_b32 s73, s43, 16
; SI-NEXT: s_lshr_b32 s75, s41, 16
; SI-NEXT: s_lshr_b32 s77, s15, 16
; SI-NEXT: s_lshr_b32 s79, s13, 16
; SI-NEXT: s_lshr_b32 s89, s11, 16
; SI-NEXT: s_lshr_b32 s91, s9, 16
; SI-NEXT: s_lshr_b32 s49, s7, 16
; SI-NEXT: s_lshr_b32 s51, s5, 16
; SI-NEXT: s_lshr_b32 vcc_hi, s59, 16
; SI-NEXT: s_lshr_b32 s31, s57, 16
; SI-NEXT: .LBB57_5: ; %end
; SI-NEXT: s_and_b32 s16, s46, 0xffff
; SI-NEXT: s_lshl_b32 s17, s60, 16
; SI-NEXT: s_or_b32 s16, s16, s17
; SI-NEXT: s_and_b32 s17, s47, 0xffff
; SI-NEXT: s_lshl_b32 s18, s61, 16
; SI-NEXT: s_or_b32 s17, s17, s18
; SI-NEXT: s_and_b32 s18, s44, 0xffff
; SI-NEXT: s_lshl_b32 s19, s62, 16
; SI-NEXT: s_or_b32 s18, s18, s19
; SI-NEXT: s_and_b32 s19, s45, 0xffff
; SI-NEXT: s_lshl_b32 s20, s63, 16
; SI-NEXT: s_or_b32 s19, s19, s20
; SI-NEXT: s_and_b32 s20, s42, 0xffff
; SI-NEXT: s_lshl_b32 s21, s72, 16
; SI-NEXT: s_or_b32 s20, s20, s21
; SI-NEXT: s_and_b32 s21, s43, 0xffff
; SI-NEXT: s_lshl_b32 s22, s73, 16
; SI-NEXT: s_or_b32 s21, s21, s22
; SI-NEXT: s_and_b32 s22, s40, 0xffff
; SI-NEXT: s_lshl_b32 s23, s74, 16
; SI-NEXT: s_or_b32 s22, s22, s23
; SI-NEXT: s_and_b32 s23, s41, 0xffff
; SI-NEXT: s_lshl_b32 s24, s75, 16
; SI-NEXT: s_or_b32 s23, s23, s24
; SI-NEXT: s_and_b32 s14, s14, 0xffff
; SI-NEXT: s_lshl_b32 s24, s76, 16
; SI-NEXT: s_or_b32 s14, s14, s24
; SI-NEXT: s_and_b32 s15, s15, 0xffff
; SI-NEXT: s_lshl_b32 s24, s77, 16
; SI-NEXT: s_or_b32 s15, s15, s24
; SI-NEXT: s_and_b32 s12, s12, 0xffff
; SI-NEXT: s_lshl_b32 s24, s78, 16
; SI-NEXT: s_or_b32 s12, s12, s24
; SI-NEXT: s_and_b32 s13, s13, 0xffff
; SI-NEXT: s_lshl_b32 s24, s79, 16
; SI-NEXT: s_or_b32 s13, s13, s24
; SI-NEXT: s_and_b32 s10, s10, 0xffff
; SI-NEXT: s_lshl_b32 s24, s88, 16
; SI-NEXT: s_or_b32 s10, s10, s24
; SI-NEXT: s_and_b32 s11, s11, 0xffff
; SI-NEXT: s_lshl_b32 s24, s89, 16
; SI-NEXT: s_or_b32 s11, s11, s24
; SI-NEXT: s_and_b32 s8, s8, 0xffff
; SI-NEXT: s_lshl_b32 s24, s90, 16
; SI-NEXT: s_or_b32 s8, s8, s24
; SI-NEXT: s_and_b32 s9, s9, 0xffff
; SI-NEXT: s_lshl_b32 s24, s91, 16
; SI-NEXT: s_or_b32 s9, s9, s24
; SI-NEXT: s_and_b32 s6, s6, 0xffff
; SI-NEXT: s_lshl_b32 s24, s92, 16
; SI-NEXT: s_or_b32 s6, s6, s24
; SI-NEXT: s_and_b32 s7, s7, 0xffff
; SI-NEXT: s_lshl_b32 s24, s49, 16
; SI-NEXT: s_or_b32 s7, s7, s24
; SI-NEXT: s_and_b32 s4, s4, 0xffff
; SI-NEXT: s_lshl_b32 s24, s94, 16
; SI-NEXT: s_or_b32 s4, s4, s24
; SI-NEXT: s_and_b32 s5, s5, 0xffff
; SI-NEXT: s_lshl_b32 s24, s51, 16
; SI-NEXT: s_or_b32 s5, s5, s24
; SI-NEXT: s_and_b32 s24, s58, 0xffff
; SI-NEXT: s_lshl_b32 s25, vcc_lo, 16
; SI-NEXT: s_or_b32 s24, s24, s25
; SI-NEXT: s_and_b32 s25, s59, 0xffff
; SI-NEXT: s_lshl_b32 s26, vcc_hi, 16
; SI-NEXT: s_or_b32 s25, s25, s26
; SI-NEXT: s_and_b32 s26, s56, 0xffff
; SI-NEXT: s_lshl_b32 s27, s30, 16
; SI-NEXT: s_or_b32 s26, s26, s27
; SI-NEXT: s_and_b32 s27, s57, 0xffff
; SI-NEXT: s_lshl_b32 s28, s31, 16
; SI-NEXT: s_or_b32 s27, s27, s28
; SI-NEXT: v_readlane_b32 s30, v24, 12
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v2, s18
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v6, s22
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v8, s14
; SI-NEXT: v_mov_b32_e32 v9, s15
; SI-NEXT: v_mov_b32_e32 v10, s12
; SI-NEXT: v_mov_b32_e32 v11, s13
; SI-NEXT: v_mov_b32_e32 v12, s10
; SI-NEXT: v_mov_b32_e32 v13, s11
; SI-NEXT: v_mov_b32_e32 v14, s8
; SI-NEXT: v_mov_b32_e32 v15, s9
; SI-NEXT: v_mov_b32_e32 v16, s6
; SI-NEXT: v_mov_b32_e32 v17, s7
; SI-NEXT: v_mov_b32_e32 v18, s4
; SI-NEXT: v_mov_b32_e32 v19, s5
; SI-NEXT: v_mov_b32_e32 v20, s24
; SI-NEXT: v_mov_b32_e32 v21, s25
; SI-NEXT: v_mov_b32_e32 v22, s26
; SI-NEXT: v_mov_b32_e32 v23, s27
; SI-NEXT: v_readlane_b32 s31, v24, 13
; SI-NEXT: v_readlane_b32 s53, v24, 11
; SI-NEXT: v_readlane_b32 s52, v24, 10
; SI-NEXT: v_readlane_b32 s51, v24, 9
; SI-NEXT: v_readlane_b32 s50, v24, 8
; SI-NEXT: v_readlane_b32 s49, v24, 7
; SI-NEXT: v_readlane_b32 s48, v24, 6
; SI-NEXT: v_readlane_b32 s39, v24, 5
; SI-NEXT: v_readlane_b32 s38, v24, 4
; SI-NEXT: v_readlane_b32 s37, v24, 3
; SI-NEXT: v_readlane_b32 s36, v24, 2
; SI-NEXT: v_readlane_b32 s35, v24, 1
; SI-NEXT: v_readlane_b32 s34, v24, 0
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: s_mov_b64 exec, s[4:5]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48i16_to_v48f16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s7, v9
; VI-NEXT: v_readfirstlane_b32 s8, v8
; VI-NEXT: v_readfirstlane_b32 s10, v7
; VI-NEXT: v_readfirstlane_b32 s13, v6
; VI-NEXT: v_readfirstlane_b32 s40, v5
; VI-NEXT: v_readfirstlane_b32 s43, v4
; VI-NEXT: v_readfirstlane_b32 s46, v3
; VI-NEXT: v_readfirstlane_b32 s58, v2
; VI-NEXT: v_readfirstlane_b32 s61, v1
; VI-NEXT: v_readfirstlane_b32 s72, v0
; VI-NEXT: s_lshr_b32 s12, s29, 16
; VI-NEXT: s_lshr_b32 s15, s28, 16
; VI-NEXT: s_lshr_b32 s42, s27, 16
; VI-NEXT: s_lshr_b32 s45, s26, 16
; VI-NEXT: s_lshr_b32 s56, s25, 16
; VI-NEXT: s_lshr_b32 s57, s24, 16
; VI-NEXT: s_lshr_b32 s60, s23, 16
; VI-NEXT: s_lshr_b32 s63, s22, 16
; VI-NEXT: s_lshr_b32 s74, s21, 16
; VI-NEXT: s_lshr_b32 s75, s20, 16
; VI-NEXT: s_lshr_b32 s76, s19, 16
; VI-NEXT: s_lshr_b32 s77, s18, 16
; VI-NEXT: s_lshr_b32 s78, s17, 16
; VI-NEXT: s_lshr_b32 s79, s16, 16
; VI-NEXT: s_lshr_b32 s6, s7, 16
; VI-NEXT: s_lshr_b32 s9, s8, 16
; VI-NEXT: s_lshr_b32 s11, s10, 16
; VI-NEXT: s_lshr_b32 s14, s13, 16
; VI-NEXT: s_lshr_b32 s41, s40, 16
; VI-NEXT: s_lshr_b32 s44, s43, 16
; VI-NEXT: s_lshr_b32 s47, s46, 16
; VI-NEXT: s_lshr_b32 s59, s58, 16
; VI-NEXT: s_lshr_b32 s62, s61, 16
; VI-NEXT: s_lshr_b32 s73, s72, 16
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: s_cbranch_scc0 .LBB57_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB57_3
; VI-NEXT: .LBB57_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB57_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB57_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
; VI-NEXT: s_add_i32 s79, s79, 3
; VI-NEXT: s_add_i32 s17, s17, 3
; VI-NEXT: s_add_i32 s78, s78, 3
; VI-NEXT: s_add_i32 s18, s18, 3
; VI-NEXT: s_add_i32 s77, s77, 3
; VI-NEXT: s_add_i32 s19, s19, 3
; VI-NEXT: s_add_i32 s76, s76, 3
; VI-NEXT: s_add_i32 s20, s20, 3
; VI-NEXT: s_add_i32 s75, s75, 3
; VI-NEXT: s_add_i32 s21, s21, 3
; VI-NEXT: s_add_i32 s74, s74, 3
; VI-NEXT: s_add_i32 s22, s22, 3
; VI-NEXT: s_add_i32 s63, s63, 3
; VI-NEXT: s_add_i32 s23, s23, 3
; VI-NEXT: s_add_i32 s60, s60, 3
; VI-NEXT: s_add_i32 s24, s24, 3
; VI-NEXT: s_add_i32 s57, s57, 3
; VI-NEXT: s_add_i32 s25, s25, 3
; VI-NEXT: s_add_i32 s56, s56, 3
; VI-NEXT: s_add_i32 s26, s26, 3
; VI-NEXT: s_add_i32 s45, s45, 3
; VI-NEXT: s_add_i32 s27, s27, 3
; VI-NEXT: s_add_i32 s42, s42, 3
; VI-NEXT: s_add_i32 s28, s28, 3
; VI-NEXT: s_add_i32 s15, s15, 3
; VI-NEXT: s_add_i32 s29, s29, 3
; VI-NEXT: s_add_i32 s12, s12, 3
; VI-NEXT: s_add_i32 s72, s72, 3
; VI-NEXT: s_add_i32 s73, s73, 3
; VI-NEXT: s_add_i32 s61, s61, 3
; VI-NEXT: s_add_i32 s62, s62, 3
; VI-NEXT: s_add_i32 s58, s58, 3
; VI-NEXT: s_add_i32 s59, s59, 3
; VI-NEXT: s_add_i32 s46, s46, 3
; VI-NEXT: s_add_i32 s47, s47, 3
; VI-NEXT: s_add_i32 s43, s43, 3
; VI-NEXT: s_add_i32 s44, s44, 3
; VI-NEXT: s_add_i32 s40, s40, 3
; VI-NEXT: s_add_i32 s41, s41, 3
; VI-NEXT: s_add_i32 s13, s13, 3
; VI-NEXT: s_add_i32 s14, s14, 3
; VI-NEXT: s_add_i32 s10, s10, 3
; VI-NEXT: s_add_i32 s11, s11, 3
; VI-NEXT: s_add_i32 s8, s8, 3
; VI-NEXT: s_add_i32 s9, s9, 3
; VI-NEXT: s_add_i32 s7, s7, 3
; VI-NEXT: s_add_i32 s6, s6, 3
; VI-NEXT: .LBB57_5: ; %end
; VI-NEXT: s_and_b32 s4, 0xffff, s16
; VI-NEXT: s_lshl_b32 s5, s79, 16
; VI-NEXT: s_or_b32 s4, s4, s5
; VI-NEXT: s_and_b32 s5, 0xffff, s17
; VI-NEXT: s_lshl_b32 s16, s78, 16
; VI-NEXT: s_or_b32 s5, s5, s16
; VI-NEXT: s_and_b32 s16, 0xffff, s18
; VI-NEXT: s_lshl_b32 s17, s77, 16
; VI-NEXT: s_or_b32 s16, s16, s17
; VI-NEXT: s_and_b32 s17, 0xffff, s19
; VI-NEXT: s_lshl_b32 s18, s76, 16
; VI-NEXT: s_or_b32 s17, s17, s18
; VI-NEXT: s_and_b32 s18, 0xffff, s20
; VI-NEXT: s_lshl_b32 s19, s75, 16
; VI-NEXT: s_or_b32 s18, s18, s19
; VI-NEXT: s_and_b32 s19, 0xffff, s21
; VI-NEXT: s_lshl_b32 s20, s74, 16
; VI-NEXT: s_or_b32 s19, s19, s20
; VI-NEXT: s_and_b32 s20, 0xffff, s22
; VI-NEXT: s_lshl_b32 s21, s63, 16
; VI-NEXT: s_or_b32 s20, s20, s21
; VI-NEXT: s_and_b32 s21, 0xffff, s23
; VI-NEXT: s_lshl_b32 s22, s60, 16
; VI-NEXT: s_or_b32 s21, s21, s22
; VI-NEXT: s_and_b32 s22, 0xffff, s24
; VI-NEXT: s_lshl_b32 s23, s57, 16
; VI-NEXT: s_or_b32 s22, s22, s23
; VI-NEXT: s_and_b32 s23, 0xffff, s25
; VI-NEXT: s_lshl_b32 s24, s56, 16
; VI-NEXT: s_or_b32 s23, s23, s24
; VI-NEXT: s_and_b32 s24, 0xffff, s26
; VI-NEXT: s_lshl_b32 s25, s45, 16
; VI-NEXT: s_or_b32 s24, s24, s25
; VI-NEXT: s_and_b32 s25, 0xffff, s27
; VI-NEXT: s_lshl_b32 s26, s42, 16
; VI-NEXT: s_or_b32 s25, s25, s26
; VI-NEXT: s_and_b32 s26, 0xffff, s28
; VI-NEXT: s_lshl_b32 s15, s15, 16
; VI-NEXT: s_or_b32 s15, s26, s15
; VI-NEXT: s_and_b32 s26, 0xffff, s29
; VI-NEXT: s_lshl_b32 s12, s12, 16
; VI-NEXT: s_or_b32 s12, s26, s12
; VI-NEXT: s_and_b32 s26, 0xffff, s72
; VI-NEXT: s_lshl_b32 s27, s73, 16
; VI-NEXT: s_or_b32 s26, s26, s27
; VI-NEXT: s_and_b32 s27, 0xffff, s61
; VI-NEXT: s_lshl_b32 s28, s62, 16
; VI-NEXT: s_or_b32 s27, s27, s28
; VI-NEXT: s_and_b32 s28, 0xffff, s58
; VI-NEXT: s_lshl_b32 s29, s59, 16
; VI-NEXT: s_or_b32 s28, s28, s29
; VI-NEXT: s_and_b32 s29, 0xffff, s46
; VI-NEXT: s_lshl_b32 s42, s47, 16
; VI-NEXT: s_or_b32 s29, s29, s42
; VI-NEXT: s_and_b32 s42, 0xffff, s43
; VI-NEXT: s_lshl_b32 s43, s44, 16
; VI-NEXT: s_and_b32 s40, 0xffff, s40
; VI-NEXT: s_lshl_b32 s41, s41, 16
; VI-NEXT: s_and_b32 s13, 0xffff, s13
; VI-NEXT: s_lshl_b32 s14, s14, 16
; VI-NEXT: s_and_b32 s10, 0xffff, s10
; VI-NEXT: s_lshl_b32 s11, s11, 16
; VI-NEXT: s_and_b32 s8, 0xffff, s8
; VI-NEXT: s_lshl_b32 s9, s9, 16
; VI-NEXT: s_and_b32 s7, 0xffff, s7
; VI-NEXT: s_lshl_b32 s6, s6, 16
; VI-NEXT: s_or_b32 s42, s42, s43
; VI-NEXT: s_or_b32 s40, s40, s41
; VI-NEXT: s_or_b32 s13, s13, s14
; VI-NEXT: s_or_b32 s10, s10, s11
; VI-NEXT: s_or_b32 s8, s8, s9
; VI-NEXT: s_or_b32 s6, s7, s6
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s17
; VI-NEXT: v_mov_b32_e32 v4, s18
; VI-NEXT: v_mov_b32_e32 v5, s19
; VI-NEXT: v_mov_b32_e32 v6, s20
; VI-NEXT: v_mov_b32_e32 v7, s21
; VI-NEXT: v_mov_b32_e32 v8, s22
; VI-NEXT: v_mov_b32_e32 v9, s23
; VI-NEXT: v_mov_b32_e32 v10, s24
; VI-NEXT: v_mov_b32_e32 v11, s25
; VI-NEXT: v_mov_b32_e32 v12, s15
; VI-NEXT: v_mov_b32_e32 v13, s12
; VI-NEXT: v_mov_b32_e32 v14, s26
; VI-NEXT: v_mov_b32_e32 v15, s27
; VI-NEXT: v_mov_b32_e32 v16, s28
; VI-NEXT: v_mov_b32_e32 v17, s29
; VI-NEXT: v_mov_b32_e32 v18, s42
; VI-NEXT: v_mov_b32_e32 v19, s40
; VI-NEXT: v_mov_b32_e32 v20, s13
; VI-NEXT: v_mov_b32_e32 v21, s10
; VI-NEXT: v_mov_b32_e32 v22, s8
; VI-NEXT: v_mov_b32_e32 v23, s6
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48i16_to_v48f16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s79, v9
; GFX9-NEXT: v_readfirstlane_b32 s78, v8
; GFX9-NEXT: v_readfirstlane_b32 s77, v7
; GFX9-NEXT: v_readfirstlane_b32 s76, v6
; GFX9-NEXT: v_readfirstlane_b32 s75, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s73, v3
; GFX9-NEXT: v_readfirstlane_b32 s72, v2
; GFX9-NEXT: v_readfirstlane_b32 s63, v1
; GFX9-NEXT: v_readfirstlane_b32 s62, v0
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
; GFX9-NEXT: s_lshr_b32 s41, s27, 16
; GFX9-NEXT: s_lshr_b32 s40, s26, 16
; GFX9-NEXT: s_lshr_b32 s15, s25, 16
; GFX9-NEXT: s_lshr_b32 s14, s24, 16
; GFX9-NEXT: s_lshr_b32 s13, s23, 16
; GFX9-NEXT: s_lshr_b32 s12, s22, 16
; GFX9-NEXT: s_lshr_b32 s11, s21, 16
; GFX9-NEXT: s_lshr_b32 s10, s20, 16
; GFX9-NEXT: s_lshr_b32 s9, s19, 16
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
; GFX9-NEXT: s_lshr_b32 s61, s79, 16
; GFX9-NEXT: s_lshr_b32 s60, s78, 16
; GFX9-NEXT: s_lshr_b32 s59, s77, 16
; GFX9-NEXT: s_lshr_b32 s58, s76, 16
; GFX9-NEXT: s_lshr_b32 s57, s75, 16
; GFX9-NEXT: s_lshr_b32 s56, s74, 16
; GFX9-NEXT: s_lshr_b32 s47, s73, 16
; GFX9-NEXT: s_lshr_b32 s46, s72, 16
; GFX9-NEXT: s_lshr_b32 s45, s63, 16
; GFX9-NEXT: s_lshr_b32 s44, s62, 16
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB57_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB57_3
; GFX9-NEXT: .LBB57_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB57_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB57_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s79, s61
; GFX9-NEXT: v_pk_add_u16 v23, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s78, s60
; GFX9-NEXT: v_pk_add_u16 v22, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s77, s59
; GFX9-NEXT: v_pk_add_u16 v21, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s76, s58
; GFX9-NEXT: v_pk_add_u16 v20, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s75, s57
; GFX9-NEXT: v_pk_add_u16 v19, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s74, s56
; GFX9-NEXT: v_pk_add_u16 v18, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s73, s47
; GFX9-NEXT: v_pk_add_u16 v17, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s72, s46
; GFX9-NEXT: v_pk_add_u16 v16, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s63, s45
; GFX9-NEXT: v_pk_add_u16 v15, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s62, s44
; GFX9-NEXT: v_pk_add_u16 v14, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s29, s43
; GFX9-NEXT: v_pk_add_u16 v13, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s28, s42
; GFX9-NEXT: v_pk_add_u16 v12, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s27, s41
; GFX9-NEXT: v_pk_add_u16 v11, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s26, s40
; GFX9-NEXT: v_pk_add_u16 v10, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s25, s15
; GFX9-NEXT: v_pk_add_u16 v9, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s24, s14
; GFX9-NEXT: v_pk_add_u16 v8, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s23, s13
; GFX9-NEXT: v_pk_add_u16 v7, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s22, s12
; GFX9-NEXT: v_pk_add_u16 v6, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s21, s11
; GFX9-NEXT: v_pk_add_u16 v5, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s20, s10
; GFX9-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s19, s9
; GFX9-NEXT: v_pk_add_u16 v3, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s18, s8
; GFX9-NEXT: v_pk_add_u16 v2, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s17, s7
; GFX9-NEXT: v_pk_add_u16 v1, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s6
; GFX9-NEXT: v_pk_add_u16 v0, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: s_branch .LBB57_6
; GFX9-NEXT: .LBB57_5:
; GFX9-NEXT: v_mov_b32_e32 v23, s79
; GFX9-NEXT: v_mov_b32_e32 v22, s78
; GFX9-NEXT: v_mov_b32_e32 v21, s77
; GFX9-NEXT: v_mov_b32_e32 v20, s76
; GFX9-NEXT: v_mov_b32_e32 v19, s75
; GFX9-NEXT: v_mov_b32_e32 v18, s74
; GFX9-NEXT: v_mov_b32_e32 v17, s73
; GFX9-NEXT: v_mov_b32_e32 v16, s72
; GFX9-NEXT: v_mov_b32_e32 v15, s63
; GFX9-NEXT: v_mov_b32_e32 v14, s62
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v24, s61
; GFX9-NEXT: v_mov_b32_e32 v25, s60
; GFX9-NEXT: v_mov_b32_e32 v26, s59
; GFX9-NEXT: v_mov_b32_e32 v27, s58
; GFX9-NEXT: v_mov_b32_e32 v28, s57
; GFX9-NEXT: v_mov_b32_e32 v29, s56
; GFX9-NEXT: v_mov_b32_e32 v30, s47
; GFX9-NEXT: v_mov_b32_e32 v31, s46
; GFX9-NEXT: v_mov_b32_e32 v32, s45
; GFX9-NEXT: v_mov_b32_e32 v33, s44
; GFX9-NEXT: v_mov_b32_e32 v34, s43
; GFX9-NEXT: v_mov_b32_e32 v35, s42
; GFX9-NEXT: v_mov_b32_e32 v36, s41
; GFX9-NEXT: v_mov_b32_e32 v37, s40
; GFX9-NEXT: v_mov_b32_e32 v38, s15
; GFX9-NEXT: v_mov_b32_e32 v39, s14
; GFX9-NEXT: v_mov_b32_e32 v48, s13
; GFX9-NEXT: v_mov_b32_e32 v49, s12
; GFX9-NEXT: v_mov_b32_e32 v50, s11
; GFX9-NEXT: v_mov_b32_e32 v51, s10
; GFX9-NEXT: v_mov_b32_e32 v52, s9
; GFX9-NEXT: v_mov_b32_e32 v53, s8
; GFX9-NEXT: v_mov_b32_e32 v54, s7
; GFX9-NEXT: v_mov_b32_e32 v55, s6
; GFX9-NEXT: .LBB57_6: ; %end
; GFX9-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; GFX9-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; GFX9-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX9-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX9-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v55, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v1, v54, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v2, v53, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v3, v52, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v6, v49, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v7, v48, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v8, v39, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v9, v38, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v10, v37, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v11, v36, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v12, v35, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v13, v34, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v14, v33, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v15, v32, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v16, v31, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v17, v30, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v18, v29, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v19, v28, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v20, v27, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v21, v26, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v22, v25, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48i16_to_v48f16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v5
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v6
; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s28, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s26, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s25, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s24, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s23, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s22, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s21, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s20, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s19, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s18, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s17, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s16, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s3, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s2, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s0, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s72, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s63, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s73, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s62, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s56, s61, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s60, 16
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s74, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s74, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB57_2
; GFX11-TRUE16-NEXT: ; %bb.1:
; GFX11-TRUE16-NEXT: s_mov_b32 s74, -1
; GFX11-TRUE16-NEXT: .LBB57_2: ; %Flow
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB57_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s57, s72, s57
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s47, s63, s47
; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, s57, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s57, s73, s59
; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, s47, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s47, s62, s58
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s56, s61, s56
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s46, s60, s46
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s29, s29, s45
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s28, s28, s44
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s27, s27, s43
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s26, s26, s42
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s25, s25, s41
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s24, s24, s40
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s23, s15
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s22, s14
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s21, s13
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s20, s12
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s19, s11
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s18, s10
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s17, s9
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s16, s7
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s6
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s8
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s47, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, s56, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, s46, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s29, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s28, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s15, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s14, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s13, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s12, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s11, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s10, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s9, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s7, 3 op_sel_hi:[1,0]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-TRUE16-NEXT: s_branch .LBB57_5
; GFX11-TRUE16-NEXT: .LBB57_4:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, s72 :: v_dual_mov_b32 v22, s63
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, s73 :: v_dual_mov_b32 v20, s62
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, s61 :: v_dual_mov_b32 v18, s60
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, s29 :: v_dual_mov_b32 v16, s28
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, s27 :: v_dual_mov_b32 v14, s26
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, s25 :: v_dual_mov_b32 v12, s24
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, s23 :: v_dual_mov_b32 v10, s22
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, s21 :: v_dual_mov_b32 v8, s20
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, s19 :: v_dual_mov_b32 v6, s18
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, s17 :: v_dual_mov_b32 v4, s16
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, s57 :: v_dual_mov_b32 v25, s47
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, s59 :: v_dual_mov_b32 v27, s58
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, s56 :: v_dual_mov_b32 v29, s46
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v31, s44
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, s43 :: v_dual_mov_b32 v33, s42
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, s41 :: v_dual_mov_b32 v35, s40
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v36, s15 :: v_dual_mov_b32 v37, s14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v38, s13 :: v_dual_mov_b32 v39, s12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v48, s11 :: v_dual_mov_b32 v49, s10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, s9 :: v_dual_mov_b32 v51, s7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, s8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s4 :: v_dual_mov_b32 v55, s5
; GFX11-TRUE16-NEXT: .LBB57_5: ; %end
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48i16_to_v48f16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v0
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v6
; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s29, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s44, s28, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s42, s26, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s41, s25, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s40, s24, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s15, s23, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s14, s22, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s21, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s12, s20, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s19, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s18, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s17, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s16, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s3, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s2, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s0, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s72, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s63, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s73, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s62, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s61, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s60, 16
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s74, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s74, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB57_2
; GFX11-FAKE16-NEXT: ; %bb.1:
; GFX11-FAKE16-NEXT: s_mov_b32 s74, -1
; GFX11-FAKE16-NEXT: .LBB57_2: ; %Flow
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-FAKE16-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB57_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s57, s72, s57
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s47, s63, s47
; GFX11-FAKE16-NEXT: v_pk_add_u16 v19, s57, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s57, s73, s59
; GFX11-FAKE16-NEXT: v_pk_add_u16 v20, s47, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s47, s62, s58
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s56, s61, s56
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s46, s60, s46
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s29, s29, s45
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s28, s28, s44
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s27, s27, s43
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s26, s26, s42
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s25, s25, s41
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s24, s24, s40
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s15, s23, s15
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s14, s22, s14
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s13, s21, s13
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s12, s20, s12
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s11, s19, s11
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s10, s18, s10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s9, s17, s9
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s7, s16, s7
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s3, s3, s6
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s2, s2, s8
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX11-FAKE16-NEXT: v_pk_add_u16 v21, s57, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v22, s47, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v23, s56, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v14, s46, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, s29, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, s28, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v17, s27, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v18, s26, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v10, s24, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v11, s15, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v12, s14, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v4, s12, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v5, s11, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v6, s10, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v7, s9, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v3, s0, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, s1, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, s2, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v0, s3, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_pk_add_u16 v8, s7, 3 op_sel_hi:[1,0]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
; GFX11-FAKE16-NEXT: s_branch .LBB57_5
; GFX11-FAKE16-NEXT: .LBB57_4:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v19, s72 :: v_dual_mov_b32 v20, s63
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, s73 :: v_dual_mov_b32 v22, s62
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, s61 :: v_dual_mov_b32 v14, s60
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v15, s29 :: v_dual_mov_b32 v16, s28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, s27 :: v_dual_mov_b32 v18, s26
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v9, s25 :: v_dual_mov_b32 v10, s24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, s23 :: v_dual_mov_b32 v12, s22
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, s21 :: v_dual_mov_b32 v4, s20
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, s19 :: v_dual_mov_b32 v6, s18
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, s17 :: v_dual_mov_b32 v8, s16
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, s57 :: v_dual_mov_b32 v25, s47
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, s59 :: v_dual_mov_b32 v27, s58
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v28, s56 :: v_dual_mov_b32 v29, s46
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v31, s44
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s43 :: v_dual_mov_b32 v33, s42
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s41 :: v_dual_mov_b32 v35, s40
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s15 :: v_dual_mov_b32 v37, s14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, s13 :: v_dual_mov_b32 v39, s12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, s11 :: v_dual_mov_b32 v49, s10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s9 :: v_dual_mov_b32 v51, s7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, s8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s4 :: v_dual_mov_b32 v55, s5
; GFX11-FAKE16-NEXT: .LBB57_5: ; %end
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v53, 16, v64
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v52, 16, v65
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v51, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v48, 16, v52
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v39, 16, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v39, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v38, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v35, 16, v39
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v34, 16, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v30, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v29, 16, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v25, 16, v29
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v24, 16, v30
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = add <48 x i16> %a, splat (i16 3)
%a2 = bitcast <48 x i16> %a1 to <48 x half>
br label %end
cmp.false:
%a3 = bitcast <48 x i16> %a to <48 x half>
br label %end
end:
%phi = phi <48 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x half> %phi
}
define <48 x i16> @bitcast_v48f16_to_v48i16(<48 x half> %a, i32 %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v48i16:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v22
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v20
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v19
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v18
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v17
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v16
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v15
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v14
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v13
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v12
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v11
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v10
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v9
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v8
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v7
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v6
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v5
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v4
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v3
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v2
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; SI-NEXT: s_cbranch_execz .LBB58_2
; SI-NEXT: ; %bb.1: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
; SI-NEXT: v_cvt_f32_f16_e32 v26, v26
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
; SI-NEXT: v_cvt_f32_f16_e32 v27, v27
; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
; SI-NEXT: v_cvt_f32_f16_e32 v29, v29
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
; SI-NEXT: v_cvt_f32_f16_e32 v17, v17
; SI-NEXT: v_cvt_f32_f16_e32 v30, v30
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v26
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
; SI-NEXT: v_cvt_f32_f16_e32 v32, v32
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
; SI-NEXT: v_cvt_f32_f16_e32 v33, v33
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
; SI-NEXT: v_add_f32_e32 v29, 0x38000000, v29
; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
; SI-NEXT: v_cvt_f32_f16_e32 v35, v35
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
; SI-NEXT: v_cvt_f32_f16_e32 v36, v36
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v25
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
; SI-NEXT: v_add_f32_e32 v32, 0x38000000, v32
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
; SI-NEXT: v_cvt_f32_f16_e32 v38, v38
; SI-NEXT: v_or_b32_e32 v23, v23, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v26
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
; SI-NEXT: v_cvt_f16_f32_e32 v32, v32
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
; SI-NEXT: v_add_f32_e32 v33, 0x38000000, v33
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
; SI-NEXT: v_cvt_f32_f16_e32 v24, v24
; SI-NEXT: v_or_b32_e32 v21, v21, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v27
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
; SI-NEXT: v_cvt_f16_f32_e32 v33, v33
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
; SI-NEXT: v_add_f32_e32 v35, 0x38000000, v35
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v49, v49
; SI-NEXT: v_or_b32_e32 v19, v19, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v29
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
; SI-NEXT: v_cvt_f16_f32_e32 v35, v35
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
; SI-NEXT: v_add_f32_e32 v36, 0x38000000, v36
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v55, v55
; SI-NEXT: v_cvt_f32_f16_e32 v54, v54
; SI-NEXT: v_cvt_f32_f16_e32 v53, v53
; SI-NEXT: v_cvt_f32_f16_e32 v52, v52
; SI-NEXT: v_cvt_f32_f16_e32 v51, v51
; SI-NEXT: v_cvt_f32_f16_e32 v50, v50
; SI-NEXT: v_cvt_f32_f16_e32 v48, v48
; SI-NEXT: v_cvt_f32_f16_e32 v39, v39
; SI-NEXT: v_cvt_f32_f16_e32 v37, v37
; SI-NEXT: v_cvt_f32_f16_e32 v34, v34
; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
; SI-NEXT: v_cvt_f32_f16_e32 v28, v28
; SI-NEXT: v_or_b32_e32 v17, v17, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v30
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
; SI-NEXT: v_cvt_f16_f32_e32 v36, v36
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
; SI-NEXT: v_add_f32_e32 v38, 0x38000000, v38
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
; SI-NEXT: v_cvt_f32_f16_e32 v20, v20
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v15, v15, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v32
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
; SI-NEXT: v_cvt_f16_f32_e32 v38, v38
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
; SI-NEXT: v_or_b32_e32 v13, v13, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v33
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_add_f32_e32 v49, 0x38000000, v49
; SI-NEXT: v_or_b32_e32 v11, v11, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v35
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f16_f32_e32 v49, v49
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_add_f32_e32 v55, 0x38000000, v55
; SI-NEXT: v_add_f32_e32 v54, 0x38000000, v54
; SI-NEXT: v_add_f32_e32 v53, 0x38000000, v53
; SI-NEXT: v_add_f32_e32 v52, 0x38000000, v52
; SI-NEXT: v_add_f32_e32 v51, 0x38000000, v51
; SI-NEXT: v_add_f32_e32 v50, 0x38000000, v50
; SI-NEXT: v_add_f32_e32 v48, 0x38000000, v48
; SI-NEXT: v_add_f32_e32 v39, 0x38000000, v39
; SI-NEXT: v_add_f32_e32 v37, 0x38000000, v37
; SI-NEXT: v_add_f32_e32 v34, 0x38000000, v34
; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
; SI-NEXT: v_or_b32_e32 v9, v9, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v36
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v55, v55
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v54, v54
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v53, v53
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
; SI-NEXT: v_cvt_f16_f32_e32 v52, v52
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
; SI-NEXT: v_cvt_f16_f32_e32 v51, v51
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
; SI-NEXT: v_cvt_f16_f32_e32 v50, v50
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
; SI-NEXT: v_cvt_f16_f32_e32 v48, v48
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
; SI-NEXT: v_cvt_f16_f32_e32 v39, v39
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
; SI-NEXT: v_cvt_f16_f32_e32 v37, v37
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
; SI-NEXT: v_cvt_f16_f32_e32 v34, v34
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
; SI-NEXT: v_or_b32_e32 v7, v7, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v38
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
; SI-NEXT: v_or_b32_e32 v5, v5, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v24
; SI-NEXT: v_or_b32_e32 v3, v3, v40
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v49
; SI-NEXT: v_or_b32_e32 v1, v1, v40
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_or_b32_e32 v0, v0, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v54
; SI-NEXT: v_or_b32_e32 v4, v4, v53
; SI-NEXT: v_or_b32_e32 v6, v6, v52
; SI-NEXT: v_or_b32_e32 v8, v8, v51
; SI-NEXT: v_or_b32_e32 v10, v10, v50
; SI-NEXT: v_or_b32_e32 v12, v12, v48
; SI-NEXT: v_or_b32_e32 v14, v14, v39
; SI-NEXT: v_or_b32_e32 v16, v16, v37
; SI-NEXT: v_or_b32_e32 v18, v18, v34
; SI-NEXT: v_or_b32_e32 v20, v20, v31
; SI-NEXT: v_or_b32_e32 v22, v22, v28
; SI-NEXT: v_alignbit_b32 v55, v1, v55, 16
; SI-NEXT: v_alignbit_b32 v54, v3, v54, 16
; SI-NEXT: v_alignbit_b32 v53, v5, v53, 16
; SI-NEXT: v_alignbit_b32 v52, v7, v52, 16
; SI-NEXT: v_alignbit_b32 v51, v9, v51, 16
; SI-NEXT: v_alignbit_b32 v50, v11, v50, 16
; SI-NEXT: v_alignbit_b32 v48, v13, v48, 16
; SI-NEXT: v_alignbit_b32 v39, v15, v39, 16
; SI-NEXT: v_alignbit_b32 v37, v17, v37, 16
; SI-NEXT: v_alignbit_b32 v34, v19, v34, 16
; SI-NEXT: v_alignbit_b32 v31, v21, v31, 16
; SI-NEXT: v_alignbit_b32 v28, v23, v28, 16
; SI-NEXT: .LBB58_2: ; %end
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v3, v3, v24
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v53
; SI-NEXT: v_or_b32_e32 v4, v4, v24
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v38
; SI-NEXT: v_or_b32_e32 v5, v5, v24
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v52
; SI-NEXT: v_or_b32_e32 v6, v6, v24
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
; SI-NEXT: v_or_b32_e32 v7, v7, v24
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v51
; SI-NEXT: v_or_b32_e32 v8, v8, v24
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v35
; SI-NEXT: v_or_b32_e32 v9, v9, v24
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v50
; SI-NEXT: v_or_b32_e32 v10, v10, v24
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v33
; SI-NEXT: v_or_b32_e32 v11, v11, v24
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v48
; SI-NEXT: v_or_b32_e32 v12, v12, v24
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; SI-NEXT: v_or_b32_e32 v13, v13, v24
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v39
; SI-NEXT: v_or_b32_e32 v14, v14, v24
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
; SI-NEXT: v_or_b32_e32 v15, v15, v24
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v37
; SI-NEXT: v_or_b32_e32 v16, v16, v24
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v29
; SI-NEXT: v_or_b32_e32 v17, v17, v24
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v34
; SI-NEXT: v_or_b32_e32 v18, v18, v24
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v27
; SI-NEXT: v_or_b32_e32 v19, v19, v24
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v31
; SI-NEXT: v_or_b32_e32 v20, v20, v24
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v26
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; SI-NEXT: v_or_b32_e32 v21, v21, v24
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v28
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; SI-NEXT: v_or_b32_e32 v1, v1, v49
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v54
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v25
; SI-NEXT: v_or_b32_e32 v0, v0, v55
; SI-NEXT: v_or_b32_e32 v2, v2, v49
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v48i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v23
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v22
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v21
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v20
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v19
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v18
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v16
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v13
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v9
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v6
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v5
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v4
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; VI-NEXT: s_cbranch_execz .LBB58_2
; VI-NEXT: ; %bb.1: ; %cmp.true
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_add_f16_e32 v55, 0x200, v55
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_e32 v54, 0x200, v54
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_add_f16_e32 v53, 0x200, v53
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_add_f16_e32 v52, 0x200, v52
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_e32 v24, 0x200, v24
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_add_f16_e32 v51, 0x200, v51
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_add_f16_e32 v50, 0x200, v50
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_add_f16_e32 v49, 0x200, v49
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
; VI-NEXT: v_add_f16_e32 v48, 0x200, v48
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
; VI-NEXT: v_add_f16_e32 v39, 0x200, v39
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
; VI-NEXT: v_add_f16_e32 v38, 0x200, v38
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
; VI-NEXT: v_add_f16_e32 v37, 0x200, v37
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
; VI-NEXT: v_add_f16_e32 v36, 0x200, v36
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
; VI-NEXT: v_add_f16_e32 v35, 0x200, v35
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
; VI-NEXT: v_add_f16_e32 v34, 0x200, v34
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
; VI-NEXT: v_add_f16_e32 v33, 0x200, v33
; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
; VI-NEXT: v_add_f16_e32 v32, 0x200, v32
; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
; VI-NEXT: v_add_f16_e32 v31, 0x200, v31
; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
; VI-NEXT: v_add_f16_e32 v19, 0x200, v19
; VI-NEXT: v_add_f16_e32 v29, 0x200, v29
; VI-NEXT: v_add_f16_e32 v20, 0x200, v20
; VI-NEXT: v_add_f16_e32 v28, 0x200, v28
; VI-NEXT: v_add_f16_e32 v21, 0x200, v21
; VI-NEXT: v_add_f16_e32 v27, 0x200, v27
; VI-NEXT: v_add_f16_e32 v22, 0x200, v22
; VI-NEXT: v_add_f16_e32 v26, 0x200, v26
; VI-NEXT: v_add_f16_e32 v23, 0x200, v23
; VI-NEXT: v_add_f16_e32 v25, 0x200, v25
; VI-NEXT: .LBB58_2: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v4, v4, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v51
; VI-NEXT: v_or_b32_sdwa v5, v5, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v50
; VI-NEXT: v_or_b32_sdwa v6, v6, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v49
; VI-NEXT: v_or_b32_sdwa v7, v7, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v48
; VI-NEXT: v_or_b32_sdwa v8, v8, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v39
; VI-NEXT: v_or_b32_sdwa v9, v9, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v38
; VI-NEXT: v_or_b32_sdwa v10, v10, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v37
; VI-NEXT: v_or_b32_sdwa v11, v11, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v36
; VI-NEXT: v_or_b32_sdwa v12, v12, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v35
; VI-NEXT: v_or_b32_sdwa v13, v13, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v34
; VI-NEXT: v_or_b32_sdwa v14, v14, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v33
; VI-NEXT: v_or_b32_sdwa v15, v15, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v32
; VI-NEXT: v_or_b32_sdwa v16, v16, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v31
; VI-NEXT: v_or_b32_sdwa v17, v17, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
; VI-NEXT: v_or_b32_sdwa v18, v18, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v29
; VI-NEXT: v_or_b32_sdwa v19, v19, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v28
; VI-NEXT: v_or_b32_sdwa v20, v20, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v27
; VI-NEXT: v_or_b32_sdwa v21, v21, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_or_b32_sdwa v22, v22, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v25
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v48i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v5
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v24
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_cbranch_execz .LBB58_2
; GFX9-NEXT: ; %bb.1: ; %cmp.true
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
; GFX9-NEXT: v_perm_b32 v23, v55, v23, s6
; GFX9-NEXT: v_perm_b32 v22, v54, v22, s6
; GFX9-NEXT: v_perm_b32 v21, v53, v21, s6
; GFX9-NEXT: v_perm_b32 v20, v52, v20, s6
; GFX9-NEXT: v_perm_b32 v19, v51, v19, s6
; GFX9-NEXT: v_perm_b32 v18, v50, v18, s6
; GFX9-NEXT: v_perm_b32 v17, v49, v17, s6
; GFX9-NEXT: v_perm_b32 v16, v48, v16, s6
; GFX9-NEXT: v_perm_b32 v15, v39, v15, s6
; GFX9-NEXT: v_perm_b32 v14, v38, v14, s6
; GFX9-NEXT: v_perm_b32 v13, v37, v13, s6
; GFX9-NEXT: s_movk_i32 s7, 0x200
; GFX9-NEXT: v_perm_b32 v12, v36, v12, s6
; GFX9-NEXT: v_perm_b32 v11, v35, v11, s6
; GFX9-NEXT: v_perm_b32 v10, v34, v10, s6
; GFX9-NEXT: v_perm_b32 v9, v33, v9, s6
; GFX9-NEXT: v_perm_b32 v8, v32, v8, s6
; GFX9-NEXT: v_perm_b32 v7, v31, v7, s6
; GFX9-NEXT: v_perm_b32 v6, v30, v6, s6
; GFX9-NEXT: v_perm_b32 v5, v28, v5, s6
; GFX9-NEXT: v_perm_b32 v4, v29, v4, s6
; GFX9-NEXT: v_perm_b32 v3, v27, v3, s6
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s6
; GFX9-NEXT: v_perm_b32 v1, v25, v1, s6
; GFX9-NEXT: v_perm_b32 v0, v24, v0, s6
; GFX9-NEXT: v_pk_add_f16 v23, v23, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v22, v22, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v21, v21, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v20, v20, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v19, v19, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v18, v18, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v17, v17, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v16, v16, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v15, v15, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, v14, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, v13, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, v12, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v5, v5, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v4, v4, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v3, v3, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, v2, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, v1, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v0, v0, s7 op_sel_hi:[1,0]
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v23
; GFX9-NEXT: .LBB58_2: ; %end
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: v_perm_b32 v0, v24, v0, s4
; GFX9-NEXT: v_perm_b32 v1, v25, v1, s4
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s4
; GFX9-NEXT: v_perm_b32 v3, v27, v3, s4
; GFX9-NEXT: v_perm_b32 v4, v29, v4, s4
; GFX9-NEXT: v_perm_b32 v5, v28, v5, s4
; GFX9-NEXT: v_perm_b32 v6, v30, v6, s4
; GFX9-NEXT: v_perm_b32 v7, v31, v7, s4
; GFX9-NEXT: v_perm_b32 v8, v32, v8, s4
; GFX9-NEXT: v_perm_b32 v9, v33, v9, s4
; GFX9-NEXT: v_perm_b32 v10, v34, v10, s4
; GFX9-NEXT: v_perm_b32 v11, v35, v11, s4
; GFX9-NEXT: v_perm_b32 v12, v36, v12, s4
; GFX9-NEXT: v_perm_b32 v13, v37, v13, s4
; GFX9-NEXT: v_perm_b32 v14, v38, v14, s4
; GFX9-NEXT: v_perm_b32 v15, v39, v15, s4
; GFX9-NEXT: v_perm_b32 v16, v48, v16, s4
; GFX9-NEXT: v_perm_b32 v17, v49, v17, s4
; GFX9-NEXT: v_perm_b32 v18, v50, v18, s4
; GFX9-NEXT: v_perm_b32 v19, v51, v19, s4
; GFX9-NEXT: v_perm_b32 v20, v52, v20, s4
; GFX9-NEXT: v_perm_b32 v21, v53, v21, s4
; GFX9-NEXT: v_perm_b32 v22, v54, v22, s4
; GFX9-NEXT: v_perm_b32 v23, v55, v23, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v48i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: .LBB58_2: ; %end
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v48i16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v24
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB58_2
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v64, v23, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v54, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v53, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v51, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v50, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v49, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v39, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v38, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v37, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v34, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v31, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v30, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v25, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v26, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v27, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v28, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v29, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v19
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v23
; GFX11-FAKE16-NEXT: .LBB58_2: ; %end
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v25, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v26, v1, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v27, v2, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v28, v3, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v29, v4, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v30, v5, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v31, v6, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v7, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v8, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v34, v9, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v35, v10, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v36, v11, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v37, v12, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v38, v13, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v39, v14, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v15, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v49, v16, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v50, v17, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v51, v18, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v19, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v53, v20, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v54, v21, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v22, 0x5040100
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v64, v23, 0x5040100
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
define inreg <48 x i16> @bitcast_v48f16_to_v48i16_scalar(<48 x half> inreg %a, i32 inreg %b) #0 {
; SI-LABEL: bitcast_v48f16_to_v48i16_scalar:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 ; 4-byte Folded Spill
; SI-NEXT: v_readfirstlane_b32 s11, v9
; SI-NEXT: v_readfirstlane_b32 s6, v8
; SI-NEXT: v_readfirstlane_b32 s12, v7
; SI-NEXT: v_readfirstlane_b32 s7, v6
; SI-NEXT: v_readfirstlane_b32 s46, v5
; SI-NEXT: v_readfirstlane_b32 s8, v4
; SI-NEXT: v_readfirstlane_b32 s45, v3
; SI-NEXT: v_readfirstlane_b32 s9, v2
; SI-NEXT: v_readfirstlane_b32 s44, v1
; SI-NEXT: v_readfirstlane_b32 s10, v0
; SI-NEXT: s_lshr_b32 s43, s29, 16
; SI-NEXT: s_lshr_b32 s62, s28, 16
; SI-NEXT: s_lshr_b32 s42, s27, 16
; SI-NEXT: s_lshr_b32 s73, s26, 16
; SI-NEXT: s_lshr_b32 s41, s25, 16
; SI-NEXT: s_lshr_b32 s75, s24, 16
; SI-NEXT: s_lshr_b32 s40, s23, 16
; SI-NEXT: s_lshr_b32 s76, s22, 16
; SI-NEXT: s_lshr_b32 s15, s21, 16
; SI-NEXT: s_lshr_b32 s77, s20, 16
; SI-NEXT: s_lshr_b32 s14, s19, 16
; SI-NEXT: s_lshr_b32 s78, s18, 16
; SI-NEXT: s_lshr_b32 s13, s17, 16
; SI-NEXT: s_lshr_b32 s79, s16, 16
; SI-NEXT: s_lshr_b32 s72, s11, 16
; SI-NEXT: s_lshr_b32 s47, s6, 16
; SI-NEXT: s_lshr_b32 s58, s12, 16
; SI-NEXT: s_lshr_b32 s57, s7, 16
; SI-NEXT: s_lshr_b32 s60, s46, 16
; SI-NEXT: s_lshr_b32 s61, s8, 16
; SI-NEXT: s_lshr_b32 s59, s45, 16
; SI-NEXT: s_lshr_b32 s63, s9, 16
; SI-NEXT: s_lshr_b32 s56, s44, 16
; SI-NEXT: s_lshr_b32 s74, s10, 16
; SI-NEXT: v_readfirstlane_b32 s4, v10
; SI-NEXT: s_cmp_lg_u32 s4, 0
; SI-NEXT: s_cbranch_scc0 .LBB59_2
; SI-NEXT: ; %bb.1: ; %cmp.false
; SI-NEXT: s_mov_b64 s[4:5], 0
; SI-NEXT: s_branch .LBB59_3
; SI-NEXT: .LBB59_2:
; SI-NEXT: s_mov_b64 s[4:5], -1
; SI-NEXT: .LBB59_3: ; %Flow
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s4, 1, 0
; SI-NEXT: s_cmp_lg_u32 s4, 1
; SI-NEXT: s_cbranch_scc1 .LBB59_5
; SI-NEXT: ; %bb.4: ; %cmp.true
; SI-NEXT: v_cvt_f32_f16_e32 v1, s78
; SI-NEXT: v_cvt_f32_f16_e32 v2, s77
; SI-NEXT: v_cvt_f32_f16_e32 v5, s76
; SI-NEXT: v_cvt_f32_f16_e32 v7, s62
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f16_f32_e32 v3, v2
; SI-NEXT: v_cvt_f32_f16_e32 v23, s19
; SI-NEXT: v_cvt_f32_f16_e32 v33, s17
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s75
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v5, s73
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s74
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v7
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v3
; SI-NEXT: v_cvt_f32_f16_e32 v3, s63
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v5, s61
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s57
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v3
; SI-NEXT: v_cvt_f32_f16_e32 v3, s47
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v20, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s72
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v22, v3
; SI-NEXT: v_cvt_f32_f16_e32 v3, s60
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v5
; SI-NEXT: v_cvt_f32_f16_e32 v5, s46
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v40, v1
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v24, v1
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v3, s59
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v24
; SI-NEXT: v_cvt_f32_f16_e32 v7, s29
; SI-NEXT: v_or_b32_e32 v19, v1, v5
; SI-NEXT: v_cvt_f32_f16_e32 v1, s45
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f32_f16_e32 v5, s56
; SI-NEXT: v_cvt_f16_f32_e32 v25, v3
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v26, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
; SI-NEXT: v_cvt_f32_f16_e32 v5, s44
; SI-NEXT: v_or_b32_e32 v17, v1, v3
; SI-NEXT: v_cvt_f32_f16_e32 v3, s43
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v27, v3
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_or_b32_e32 v15, v5, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s42
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v27
; SI-NEXT: v_or_b32_e32 v13, v3, v5
; SI-NEXT: v_cvt_f32_f16_e32 v3, s27
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f32_f16_e32 v5, s41
; SI-NEXT: v_cvt_f16_f32_e32 v28, v1
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v29, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28
; SI-NEXT: v_cvt_f32_f16_e32 v5, s25
; SI-NEXT: v_or_b32_e32 v11, v1, v3
; SI-NEXT: v_cvt_f32_f16_e32 v3, s40
; SI-NEXT: v_cvt_f32_f16_e32 v7, s23
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v30, v3
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v7
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v29
; SI-NEXT: v_or_b32_e32 v9, v5, v1
; SI-NEXT: v_cvt_f32_f16_e32 v1, s15
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v30
; SI-NEXT: v_or_b32_e32 v7, v3, v5
; SI-NEXT: v_cvt_f32_f16_e32 v3, s21
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
; SI-NEXT: v_cvt_f32_f16_e32 v5, s14
; SI-NEXT: v_cvt_f16_f32_e32 v31, v1
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v5
; SI-NEXT: v_cvt_f16_f32_e32 v32, v3
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31
; SI-NEXT: v_or_b32_e32 v5, v1, v3
; SI-NEXT: v_cvt_f32_f16_e32 v3, s13
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_cvt_f32_f16_e32 v21, s58
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
; SI-NEXT: v_cvt_f16_f32_e32 v34, v3
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33
; SI-NEXT: v_cvt_f16_f32_e32 v33, v3
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
; SI-NEXT: v_or_b32_e32 v3, v23, v1
; SI-NEXT: v_cvt_f32_f16_e32 v23, s12
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
; SI-NEXT: v_or_b32_e32 v1, v33, v1
; SI-NEXT: v_cvt_f32_f16_e32 v33, s11
; SI-NEXT: v_cvt_f32_f16_e32 v48, s28
; SI-NEXT: v_cvt_f32_f16_e32 v49, s10
; SI-NEXT: v_cvt_f32_f16_e32 v38, s24
; SI-NEXT: v_cvt_f32_f16_e32 v39, s26
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
; SI-NEXT: v_cvt_f16_f32_e32 v41, v21
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v23
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v33
; SI-NEXT: v_add_f32_e32 v48, 0x38000000, v48
; SI-NEXT: v_add_f32_e32 v49, 0x38000000, v49
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
; SI-NEXT: v_add_f32_e32 v38, 0x38000000, v38
; SI-NEXT: v_add_f32_e32 v39, 0x38000000, v39
; SI-NEXT: v_cvt_f16_f32_e32 v48, v48
; SI-NEXT: v_cvt_f16_f32_e32 v49, v49
; SI-NEXT: v_cvt_f16_f32_e32 v38, v38
; SI-NEXT: v_cvt_f16_f32_e32 v39, v39
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v41
; SI-NEXT: v_cvt_f32_f16_e32 v0, s79
; SI-NEXT: v_or_b32_e32 v21, v21, v33
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v40
; SI-NEXT: v_cvt_f32_f16_e32 v35, s16
; SI-NEXT: v_or_b32_e32 v23, v23, v33
; SI-NEXT: v_cvt_f32_f16_e32 v33, s18
; SI-NEXT: v_cvt_f32_f16_e32 v36, s20
; SI-NEXT: v_cvt_f32_f16_e32 v37, s22
; SI-NEXT: s_waitcnt expcnt(5)
; SI-NEXT: v_or_b32_e32 v44, v48, v12
; SI-NEXT: s_waitcnt expcnt(4)
; SI-NEXT: v_or_b32_e32 v45, v49, v14
; SI-NEXT: v_cvt_f32_f16_e32 v48, s7
; SI-NEXT: v_cvt_f32_f16_e32 v49, s6
; SI-NEXT: v_or_b32_e32 v42, v38, v8
; SI-NEXT: v_or_b32_e32 v43, v39, v10
; SI-NEXT: v_cvt_f32_f16_e32 v38, s9
; SI-NEXT: v_cvt_f32_f16_e32 v39, s8
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: v_add_f32_e32 v35, 0x38000000, v35
; SI-NEXT: v_add_f32_e32 v33, 0x38000000, v33
; SI-NEXT: v_add_f32_e32 v36, 0x38000000, v36
; SI-NEXT: v_add_f32_e32 v37, 0x38000000, v37
; SI-NEXT: v_add_f32_e32 v48, 0x38000000, v48
; SI-NEXT: v_add_f32_e32 v49, 0x38000000, v49
; SI-NEXT: v_cvt_f16_f32_e32 v35, v35
; SI-NEXT: v_cvt_f16_f32_e32 v33, v33
; SI-NEXT: v_cvt_f16_f32_e32 v36, v36
; SI-NEXT: v_cvt_f16_f32_e32 v37, v37
; SI-NEXT: v_add_f32_e32 v38, 0x38000000, v38
; SI-NEXT: v_add_f32_e32 v39, 0x38000000, v39
; SI-NEXT: v_cvt_f16_f32_e32 v48, v48
; SI-NEXT: v_cvt_f16_f32_e32 v49, v49
; SI-NEXT: v_cvt_f16_f32_e32 v38, v38
; SI-NEXT: v_cvt_f16_f32_e32 v39, v39
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v35, v35, v0
; SI-NEXT: v_or_b32_e32 v33, v33, v2
; SI-NEXT: v_or_b32_e32 v36, v36, v4
; SI-NEXT: v_or_b32_e32 v37, v37, v6
; SI-NEXT: s_waitcnt expcnt(1)
; SI-NEXT: v_or_b32_e32 v56, v48, v20
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_or_b32_e32 v57, v49, v22
; SI-NEXT: v_lshr_b64 v[52:53], v[2:3], 16
; SI-NEXT: v_lshr_b64 v[50:51], v[4:5], 16
; SI-NEXT: v_lshr_b64 v[48:49], v[6:7], 16
; SI-NEXT: v_or_b32_e32 v46, v38, v16
; SI-NEXT: v_or_b32_e32 v47, v39, v18
; SI-NEXT: v_lshr_b64 v[54:55], v[0:1], 16
; SI-NEXT: v_mov_b32_e32 v0, v35
; SI-NEXT: v_mov_b32_e32 v53, v33
; SI-NEXT: v_mov_b32_e32 v2, v34
; SI-NEXT: v_mov_b32_e32 v51, v36
; SI-NEXT: v_mov_b32_e32 v4, v32
; SI-NEXT: v_mov_b32_e32 v49, v37
; SI-NEXT: v_mov_b32_e32 v6, v31
; SI-NEXT: v_lshr_b64 v[38:39], v[8:9], 16
; SI-NEXT: v_mov_b32_e32 v8, v30
; SI-NEXT: v_lshr_b64 v[36:37], v[10:11], 16
; SI-NEXT: v_mov_b32_e32 v10, v29
; SI-NEXT: v_lshr_b64 v[34:35], v[12:13], 16
; SI-NEXT: v_mov_b32_e32 v12, v28
; SI-NEXT: v_lshr_b64 v[32:33], v[14:15], 16
; SI-NEXT: v_mov_b32_e32 v14, v27
; SI-NEXT: v_lshr_b64 v[30:31], v[16:17], 16
; SI-NEXT: v_mov_b32_e32 v16, v26
; SI-NEXT: v_lshr_b64 v[28:29], v[18:19], 16
; SI-NEXT: v_mov_b32_e32 v18, v25
; SI-NEXT: v_lshr_b64 v[26:27], v[20:21], 16
; SI-NEXT: v_mov_b32_e32 v20, v24
; SI-NEXT: v_lshr_b64 v[24:25], v[22:23], 16
; SI-NEXT: v_mov_b32_e32 v39, v42
; SI-NEXT: v_mov_b32_e32 v37, v43
; SI-NEXT: v_mov_b32_e32 v35, v44
; SI-NEXT: v_mov_b32_e32 v33, v45
; SI-NEXT: v_mov_b32_e32 v31, v46
; SI-NEXT: v_mov_b32_e32 v29, v47
; SI-NEXT: v_mov_b32_e32 v27, v56
; SI-NEXT: v_mov_b32_e32 v25, v57
; SI-NEXT: v_mov_b32_e32 v22, v41
; SI-NEXT: s_branch .LBB59_6
; SI-NEXT: .LBB59_5:
; SI-NEXT: v_mov_b32_e32 v40, s72
; SI-NEXT: v_mov_b32_e32 v22, s58
; SI-NEXT: v_mov_b32_e32 v20, s60
; SI-NEXT: v_mov_b32_e32 v18, s59
; SI-NEXT: v_mov_b32_e32 v16, s56
; SI-NEXT: v_mov_b32_e32 v14, s43
; SI-NEXT: v_mov_b32_e32 v12, s42
; SI-NEXT: v_mov_b32_e32 v10, s41
; SI-NEXT: v_mov_b32_e32 v8, s40
; SI-NEXT: v_mov_b32_e32 v6, s15
; SI-NEXT: v_mov_b32_e32 v4, s14
; SI-NEXT: v_mov_b32_e32 v2, s13
; SI-NEXT: v_mov_b32_e32 v25, s6
; SI-NEXT: v_mov_b32_e32 v27, s7
; SI-NEXT: v_mov_b32_e32 v29, s8
; SI-NEXT: v_mov_b32_e32 v31, s9
; SI-NEXT: v_mov_b32_e32 v33, s10
; SI-NEXT: v_mov_b32_e32 v35, s28
; SI-NEXT: v_mov_b32_e32 v37, s26
; SI-NEXT: v_mov_b32_e32 v39, s24
; SI-NEXT: v_mov_b32_e32 v49, s22
; SI-NEXT: v_mov_b32_e32 v51, s20
; SI-NEXT: v_mov_b32_e32 v53, s18
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_mov_b32_e32 v3, s19
; SI-NEXT: v_mov_b32_e32 v5, s21
; SI-NEXT: v_mov_b32_e32 v7, s23
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_mov_b32_e32 v11, s27
; SI-NEXT: v_mov_b32_e32 v13, s29
; SI-NEXT: v_mov_b32_e32 v15, s44
; SI-NEXT: v_mov_b32_e32 v17, s45
; SI-NEXT: v_mov_b32_e32 v19, s46
; SI-NEXT: v_mov_b32_e32 v21, s12
; SI-NEXT: v_mov_b32_e32 v23, s11
; SI-NEXT: v_mov_b32_e32 v54, s79
; SI-NEXT: v_mov_b32_e32 v52, s78
; SI-NEXT: v_mov_b32_e32 v50, s77
; SI-NEXT: v_mov_b32_e32 v48, s76
; SI-NEXT: v_mov_b32_e32 v38, s75
; SI-NEXT: v_mov_b32_e32 v36, s73
; SI-NEXT: v_mov_b32_e32 v34, s62
; SI-NEXT: v_mov_b32_e32 v32, s74
; SI-NEXT: v_mov_b32_e32 v30, s63
; SI-NEXT: v_mov_b32_e32 v28, s61
; SI-NEXT: v_mov_b32_e32 v26, s57
; SI-NEXT: v_mov_b32_e32 v24, s47
; SI-NEXT: .LBB59_6: ; %end
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; SI-NEXT: v_or_b32_e32 v21, v21, v22
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v25
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; SI-NEXT: v_or_b32_e32 v22, v22, v24
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v40
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: v_or_b32_e32 v1, v1, v2
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v52
; SI-NEXT: v_and_b32_e32 v52, 0xffff, v53
; SI-NEXT: v_or_b32_e32 v3, v3, v4
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v50
; SI-NEXT: v_and_b32_e32 v50, 0xffff, v51
; SI-NEXT: v_or_b32_e32 v5, v5, v6
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v49
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; SI-NEXT: v_or_b32_e32 v7, v7, v8
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v39
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; SI-NEXT: v_or_b32_e32 v9, v9, v10
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v37
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; SI-NEXT: v_or_b32_e32 v11, v11, v12
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v35
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; SI-NEXT: v_or_b32_e32 v13, v13, v14
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v33
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; SI-NEXT: v_or_b32_e32 v15, v15, v16
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v31
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; SI-NEXT: v_or_b32_e32 v17, v17, v18
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v29
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; SI-NEXT: v_or_b32_e32 v19, v19, v20
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v27
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
; SI-NEXT: v_or_b32_e32 v0, v0, v54
; SI-NEXT: v_or_b32_e32 v2, v52, v2
; SI-NEXT: v_or_b32_e32 v4, v50, v4
; SI-NEXT: v_or_b32_e32 v6, v6, v48
; SI-NEXT: v_or_b32_e32 v8, v8, v38
; SI-NEXT: v_or_b32_e32 v10, v10, v36
; SI-NEXT: v_or_b32_e32 v12, v12, v34
; SI-NEXT: v_or_b32_e32 v14, v14, v32
; SI-NEXT: v_or_b32_e32 v16, v16, v30
; SI-NEXT: v_or_b32_e32 v18, v18, v28
; SI-NEXT: v_or_b32_e32 v20, v20, v26
; SI-NEXT: v_or_b32_e32 v23, v23, v24
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: bitcast_v48f16_to_v48i16_scalar:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_readfirstlane_b32 s44, v9
; VI-NEXT: v_readfirstlane_b32 s46, v8
; VI-NEXT: v_readfirstlane_b32 s56, v7
; VI-NEXT: v_readfirstlane_b32 s58, v6
; VI-NEXT: v_readfirstlane_b32 s60, v5
; VI-NEXT: v_readfirstlane_b32 s62, v4
; VI-NEXT: v_readfirstlane_b32 s72, v3
; VI-NEXT: v_readfirstlane_b32 s74, v2
; VI-NEXT: v_readfirstlane_b32 s76, v1
; VI-NEXT: v_readfirstlane_b32 s78, v0
; VI-NEXT: s_lshr_b32 s6, s29, 16
; VI-NEXT: s_lshr_b32 s7, s28, 16
; VI-NEXT: s_lshr_b32 s8, s27, 16
; VI-NEXT: s_lshr_b32 s9, s26, 16
; VI-NEXT: s_lshr_b32 s10, s25, 16
; VI-NEXT: s_lshr_b32 s11, s24, 16
; VI-NEXT: s_lshr_b32 s12, s23, 16
; VI-NEXT: s_lshr_b32 s13, s22, 16
; VI-NEXT: s_lshr_b32 s14, s21, 16
; VI-NEXT: s_lshr_b32 s15, s20, 16
; VI-NEXT: s_lshr_b32 s40, s19, 16
; VI-NEXT: s_lshr_b32 s41, s18, 16
; VI-NEXT: s_lshr_b32 s42, s17, 16
; VI-NEXT: s_lshr_b32 s43, s16, 16
; VI-NEXT: s_lshr_b32 s45, s44, 16
; VI-NEXT: s_lshr_b32 s47, s46, 16
; VI-NEXT: s_lshr_b32 s57, s56, 16
; VI-NEXT: s_lshr_b32 s59, s58, 16
; VI-NEXT: s_lshr_b32 s61, s60, 16
; VI-NEXT: s_lshr_b32 s63, s62, 16
; VI-NEXT: s_lshr_b32 s73, s72, 16
; VI-NEXT: s_lshr_b32 s75, s74, 16
; VI-NEXT: s_lshr_b32 s77, s76, 16
; VI-NEXT: s_lshr_b32 s79, s78, 16
; VI-NEXT: v_readfirstlane_b32 s4, v10
; VI-NEXT: s_cmp_lg_u32 s4, 0
; VI-NEXT: s_cbranch_scc0 .LBB59_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB59_3
; VI-NEXT: .LBB59_2:
; VI-NEXT: s_mov_b64 s[4:5], -1
; VI-NEXT: .LBB59_3: ; %Flow
; VI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; VI-NEXT: s_cselect_b32 s4, 1, 0
; VI-NEXT: s_cmp_lg_u32 s4, 1
; VI-NEXT: s_cbranch_scc1 .LBB59_5
; VI-NEXT: ; %bb.4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v24, 0x200
; VI-NEXT: v_add_f16_e32 v0, s16, v24
; VI-NEXT: v_add_f16_e32 v55, s43, v24
; VI-NEXT: v_add_f16_e32 v1, s17, v24
; VI-NEXT: v_add_f16_e32 v54, s42, v24
; VI-NEXT: v_add_f16_e32 v2, s18, v24
; VI-NEXT: v_add_f16_e32 v53, s41, v24
; VI-NEXT: v_add_f16_e32 v3, s19, v24
; VI-NEXT: v_add_f16_e32 v52, s40, v24
; VI-NEXT: v_add_f16_e32 v4, s20, v24
; VI-NEXT: v_add_f16_e32 v51, s15, v24
; VI-NEXT: v_add_f16_e32 v5, s21, v24
; VI-NEXT: v_add_f16_e32 v50, s14, v24
; VI-NEXT: v_add_f16_e32 v6, s22, v24
; VI-NEXT: v_add_f16_e32 v49, s13, v24
; VI-NEXT: v_add_f16_e32 v7, s23, v24
; VI-NEXT: v_add_f16_e32 v48, s12, v24
; VI-NEXT: v_add_f16_e32 v8, s24, v24
; VI-NEXT: v_add_f16_e32 v39, s11, v24
; VI-NEXT: v_add_f16_e32 v9, s25, v24
; VI-NEXT: v_add_f16_e32 v38, s10, v24
; VI-NEXT: v_add_f16_e32 v10, s26, v24
; VI-NEXT: v_add_f16_e32 v37, s9, v24
; VI-NEXT: v_add_f16_e32 v11, s27, v24
; VI-NEXT: v_add_f16_e32 v36, s8, v24
; VI-NEXT: v_add_f16_e32 v12, s28, v24
; VI-NEXT: v_add_f16_e32 v35, s7, v24
; VI-NEXT: v_add_f16_e32 v13, s29, v24
; VI-NEXT: v_add_f16_e32 v34, s6, v24
; VI-NEXT: v_add_f16_e32 v14, s78, v24
; VI-NEXT: v_add_f16_e32 v33, s79, v24
; VI-NEXT: v_add_f16_e32 v15, s76, v24
; VI-NEXT: v_add_f16_e32 v32, s77, v24
; VI-NEXT: v_add_f16_e32 v16, s74, v24
; VI-NEXT: v_add_f16_e32 v31, s75, v24
; VI-NEXT: v_add_f16_e32 v17, s72, v24
; VI-NEXT: v_add_f16_e32 v30, s73, v24
; VI-NEXT: v_add_f16_e32 v18, s62, v24
; VI-NEXT: v_add_f16_e32 v29, s63, v24
; VI-NEXT: v_add_f16_e32 v19, s60, v24
; VI-NEXT: v_add_f16_e32 v28, s61, v24
; VI-NEXT: v_add_f16_e32 v20, s58, v24
; VI-NEXT: v_add_f16_e32 v27, s59, v24
; VI-NEXT: v_add_f16_e32 v21, s56, v24
; VI-NEXT: v_add_f16_e32 v26, s57, v24
; VI-NEXT: v_add_f16_e32 v22, s46, v24
; VI-NEXT: v_add_f16_e32 v25, s47, v24
; VI-NEXT: v_add_f16_e32 v23, s44, v24
; VI-NEXT: v_add_f16_e32 v24, s45, v24
; VI-NEXT: s_branch .LBB59_6
; VI-NEXT: .LBB59_5:
; VI-NEXT: v_mov_b32_e32 v24, s45
; VI-NEXT: v_mov_b32_e32 v23, s44
; VI-NEXT: v_mov_b32_e32 v25, s47
; VI-NEXT: v_mov_b32_e32 v22, s46
; VI-NEXT: v_mov_b32_e32 v26, s57
; VI-NEXT: v_mov_b32_e32 v21, s56
; VI-NEXT: v_mov_b32_e32 v27, s59
; VI-NEXT: v_mov_b32_e32 v20, s58
; VI-NEXT: v_mov_b32_e32 v28, s61
; VI-NEXT: v_mov_b32_e32 v19, s60
; VI-NEXT: v_mov_b32_e32 v29, s63
; VI-NEXT: v_mov_b32_e32 v18, s62
; VI-NEXT: v_mov_b32_e32 v30, s73
; VI-NEXT: v_mov_b32_e32 v17, s72
; VI-NEXT: v_mov_b32_e32 v31, s75
; VI-NEXT: v_mov_b32_e32 v16, s74
; VI-NEXT: v_mov_b32_e32 v32, s77
; VI-NEXT: v_mov_b32_e32 v15, s76
; VI-NEXT: v_mov_b32_e32 v33, s79
; VI-NEXT: v_mov_b32_e32 v14, s78
; VI-NEXT: v_mov_b32_e32 v34, s6
; VI-NEXT: v_mov_b32_e32 v13, s29
; VI-NEXT: v_mov_b32_e32 v35, s7
; VI-NEXT: v_mov_b32_e32 v12, s28
; VI-NEXT: v_mov_b32_e32 v36, s8
; VI-NEXT: v_mov_b32_e32 v11, s27
; VI-NEXT: v_mov_b32_e32 v37, s9
; VI-NEXT: v_mov_b32_e32 v10, s26
; VI-NEXT: v_mov_b32_e32 v38, s10
; VI-NEXT: v_mov_b32_e32 v9, s25
; VI-NEXT: v_mov_b32_e32 v39, s11
; VI-NEXT: v_mov_b32_e32 v8, s24
; VI-NEXT: v_mov_b32_e32 v48, s12
; VI-NEXT: v_mov_b32_e32 v7, s23
; VI-NEXT: v_mov_b32_e32 v49, s13
; VI-NEXT: v_mov_b32_e32 v6, s22
; VI-NEXT: v_mov_b32_e32 v50, s14
; VI-NEXT: v_mov_b32_e32 v5, s21
; VI-NEXT: v_mov_b32_e32 v51, s15
; VI-NEXT: v_mov_b32_e32 v4, s20
; VI-NEXT: v_mov_b32_e32 v52, s40
; VI-NEXT: v_mov_b32_e32 v3, s19
; VI-NEXT: v_mov_b32_e32 v53, s41
; VI-NEXT: v_mov_b32_e32 v2, s18
; VI-NEXT: v_mov_b32_e32 v54, s42
; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_mov_b32_e32 v55, s43
; VI-NEXT: v_mov_b32_e32 v0, s16
; VI-NEXT: .LBB59_6: ; %end
; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: v_or_b32_sdwa v0, v0, v55 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v54 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v2, v2, v53 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v3, v3, v52 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v4, v4, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v5, v5, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v6, v6, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v7, v7, v48 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v8, v8, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v9, v9, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v10, v10, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v11, v11, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v12, v12, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v13, v13, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v14, v14, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v15, v15, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v16, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v17, v17, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v19, v19, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v20, v20, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v21, v21, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v22, v22, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: bitcast_v48f16_to_v48i16_scalar:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s79, v9
; GFX9-NEXT: v_readfirstlane_b32 s78, v8
; GFX9-NEXT: v_readfirstlane_b32 s77, v7
; GFX9-NEXT: v_readfirstlane_b32 s76, v6
; GFX9-NEXT: v_readfirstlane_b32 s75, v5
; GFX9-NEXT: v_readfirstlane_b32 s74, v4
; GFX9-NEXT: v_readfirstlane_b32 s73, v3
; GFX9-NEXT: v_readfirstlane_b32 s72, v2
; GFX9-NEXT: v_readfirstlane_b32 s63, v1
; GFX9-NEXT: v_readfirstlane_b32 s62, v0
; GFX9-NEXT: s_lshr_b32 s43, s29, 16
; GFX9-NEXT: s_lshr_b32 s42, s28, 16
; GFX9-NEXT: s_lshr_b32 s41, s27, 16
; GFX9-NEXT: s_lshr_b32 s40, s26, 16
; GFX9-NEXT: s_lshr_b32 s15, s25, 16
; GFX9-NEXT: s_lshr_b32 s14, s24, 16
; GFX9-NEXT: s_lshr_b32 s13, s23, 16
; GFX9-NEXT: s_lshr_b32 s12, s22, 16
; GFX9-NEXT: s_lshr_b32 s11, s21, 16
; GFX9-NEXT: s_lshr_b32 s10, s20, 16
; GFX9-NEXT: s_lshr_b32 s9, s19, 16
; GFX9-NEXT: s_lshr_b32 s8, s18, 16
; GFX9-NEXT: s_lshr_b32 s7, s17, 16
; GFX9-NEXT: s_lshr_b32 s6, s16, 16
; GFX9-NEXT: s_lshr_b32 s61, s79, 16
; GFX9-NEXT: s_lshr_b32 s60, s78, 16
; GFX9-NEXT: s_lshr_b32 s59, s77, 16
; GFX9-NEXT: s_lshr_b32 s58, s76, 16
; GFX9-NEXT: s_lshr_b32 s57, s75, 16
; GFX9-NEXT: s_lshr_b32 s56, s74, 16
; GFX9-NEXT: s_lshr_b32 s47, s73, 16
; GFX9-NEXT: s_lshr_b32 s46, s72, 16
; GFX9-NEXT: s_lshr_b32 s45, s63, 16
; GFX9-NEXT: s_lshr_b32 s44, s62, 16
; GFX9-NEXT: v_readfirstlane_b32 s4, v10
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB59_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB59_3
; GFX9-NEXT: .LBB59_2:
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: .LBB59_3: ; %Flow
; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: s_cmp_lg_u32 s4, 1
; GFX9-NEXT: s_cbranch_scc1 .LBB59_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s79, s61
; GFX9-NEXT: v_mov_b32_e32 v0, 0x200
; GFX9-NEXT: v_pk_add_f16 v23, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s78, s60
; GFX9-NEXT: v_pk_add_f16 v22, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s77, s59
; GFX9-NEXT: v_pk_add_f16 v21, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s76, s58
; GFX9-NEXT: v_pk_add_f16 v20, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s75, s57
; GFX9-NEXT: v_pk_add_f16 v19, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s74, s56
; GFX9-NEXT: v_pk_add_f16 v18, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s73, s47
; GFX9-NEXT: v_pk_add_f16 v17, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s72, s46
; GFX9-NEXT: v_pk_add_f16 v16, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s63, s45
; GFX9-NEXT: v_pk_add_f16 v15, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s62, s44
; GFX9-NEXT: v_pk_add_f16 v14, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s29, s43
; GFX9-NEXT: v_pk_add_f16 v13, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s28, s42
; GFX9-NEXT: v_pk_add_f16 v12, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s27, s41
; GFX9-NEXT: v_pk_add_f16 v11, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s26, s40
; GFX9-NEXT: v_pk_add_f16 v10, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s25, s15
; GFX9-NEXT: v_pk_add_f16 v9, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s24, s14
; GFX9-NEXT: v_pk_add_f16 v8, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s23, s13
; GFX9-NEXT: v_pk_add_f16 v7, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s22, s12
; GFX9-NEXT: v_pk_add_f16 v6, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s21, s11
; GFX9-NEXT: v_pk_add_f16 v5, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s20, s10
; GFX9-NEXT: v_pk_add_f16 v4, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s19, s9
; GFX9-NEXT: v_pk_add_f16 v3, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s18, s8
; GFX9-NEXT: v_pk_add_f16 v2, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s17, s7
; GFX9-NEXT: v_pk_add_f16 v1, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s6
; GFX9-NEXT: v_pk_add_f16 v0, s4, v0 op_sel_hi:[1,0]
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX9-NEXT: s_branch .LBB59_6
; GFX9-NEXT: .LBB59_5:
; GFX9-NEXT: v_mov_b32_e32 v23, s79
; GFX9-NEXT: v_mov_b32_e32 v22, s78
; GFX9-NEXT: v_mov_b32_e32 v21, s77
; GFX9-NEXT: v_mov_b32_e32 v20, s76
; GFX9-NEXT: v_mov_b32_e32 v19, s75
; GFX9-NEXT: v_mov_b32_e32 v18, s74
; GFX9-NEXT: v_mov_b32_e32 v17, s73
; GFX9-NEXT: v_mov_b32_e32 v16, s72
; GFX9-NEXT: v_mov_b32_e32 v15, s63
; GFX9-NEXT: v_mov_b32_e32 v14, s62
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v24, s61
; GFX9-NEXT: v_mov_b32_e32 v25, s60
; GFX9-NEXT: v_mov_b32_e32 v26, s59
; GFX9-NEXT: v_mov_b32_e32 v27, s58
; GFX9-NEXT: v_mov_b32_e32 v28, s57
; GFX9-NEXT: v_mov_b32_e32 v29, s56
; GFX9-NEXT: v_mov_b32_e32 v30, s47
; GFX9-NEXT: v_mov_b32_e32 v31, s46
; GFX9-NEXT: v_mov_b32_e32 v32, s45
; GFX9-NEXT: v_mov_b32_e32 v33, s44
; GFX9-NEXT: v_mov_b32_e32 v34, s43
; GFX9-NEXT: v_mov_b32_e32 v35, s42
; GFX9-NEXT: v_mov_b32_e32 v36, s41
; GFX9-NEXT: v_mov_b32_e32 v37, s40
; GFX9-NEXT: v_mov_b32_e32 v38, s15
; GFX9-NEXT: v_mov_b32_e32 v39, s14
; GFX9-NEXT: v_mov_b32_e32 v48, s13
; GFX9-NEXT: v_mov_b32_e32 v49, s12
; GFX9-NEXT: v_mov_b32_e32 v50, s11
; GFX9-NEXT: v_mov_b32_e32 v51, s10
; GFX9-NEXT: v_mov_b32_e32 v52, s9
; GFX9-NEXT: v_mov_b32_e32 v53, s8
; GFX9-NEXT: v_mov_b32_e32 v54, s7
; GFX9-NEXT: v_mov_b32_e32 v55, s6
; GFX9-NEXT: .LBB59_6: ; %end
; GFX9-NEXT: v_lshlrev_b32_e32 v55, 16, v55
; GFX9-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; GFX9-NEXT: v_lshlrev_b32_e32 v53, 16, v53
; GFX9-NEXT: v_lshlrev_b32_e32 v52, 16, v52
; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v51
; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v50
; GFX9-NEXT: v_lshlrev_b32_e32 v49, 16, v49
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v38
; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX9-NEXT: v_lshlrev_b32_e32 v36, 16, v36
; GFX9-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX9-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v33
; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: v_or_b32_sdwa v0, v55, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v1, v54, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v2, v53, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v3, v52, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v4, v51, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v6, v49, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v7, v48, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v8, v39, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v9, v38, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v10, v37, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v11, v36, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v12, v35, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v13, v34, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v14, v33, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v15, v32, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v16, v31, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v17, v30, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v18, v29, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v19, v28, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v20, v27, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v21, v26, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v22, v25, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: bitcast_v48f16_to_v48i16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v5
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v3
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v6
; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s29, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s28, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s26, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s25, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s24, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s23, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s22, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s21, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s20, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s19, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s18, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s17, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s16, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s3, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s2, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s0, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s72, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s63, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s73, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s62, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s56, s61, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s60, 16
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s74, 0
; GFX11-TRUE16-NEXT: s_mov_b32 s74, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB59_2
; GFX11-TRUE16-NEXT: ; %bb.1:
; GFX11-TRUE16-NEXT: s_mov_b32 s74, -1
; GFX11-TRUE16-NEXT: .LBB59_2: ; %Flow
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB59_4
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s57, s72, s57
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s47, s63, s47
; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, s57 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s57, s73, s59
; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, s47 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s47, s62, s58
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s56, s61, s56
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s46, s60, s46
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s29, s29, s45
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s28, s28, s44
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s27, s27, s43
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s26, s26, s42
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s25, s25, s41
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s24, s24, s40
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s23, s15
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s22, s14
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s21, s13
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s20, s12
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s19, s11
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s18, s10
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s17, s9
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s16, s7
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s6
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s8
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, s57 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s47 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, s56 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, s46 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s29 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s28 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s15 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s14 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s13 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s12 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s11 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s10 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s9 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s7 op_sel_hi:[0,1]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v18
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v19
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v23
; GFX11-TRUE16-NEXT: s_branch .LBB59_5
; GFX11-TRUE16-NEXT: .LBB59_4:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, s72 :: v_dual_mov_b32 v22, s63
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, s73 :: v_dual_mov_b32 v20, s62
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, s61 :: v_dual_mov_b32 v18, s60
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, s29 :: v_dual_mov_b32 v16, s28
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, s27 :: v_dual_mov_b32 v14, s26
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, s25 :: v_dual_mov_b32 v12, s24
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, s23 :: v_dual_mov_b32 v10, s22
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, s21 :: v_dual_mov_b32 v8, s20
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, s19 :: v_dual_mov_b32 v6, s18
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, s17 :: v_dual_mov_b32 v4, s16
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s2
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, s57 :: v_dual_mov_b32 v25, s47
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, s59 :: v_dual_mov_b32 v27, s58
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, s56 :: v_dual_mov_b32 v29, s46
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v31, s44
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, s43 :: v_dual_mov_b32 v33, s42
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, s41 :: v_dual_mov_b32 v35, s40
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v36, s15 :: v_dual_mov_b32 v37, s14
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v38, s13 :: v_dual_mov_b32 v39, s12
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v48, s11 :: v_dual_mov_b32 v49, s10
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, s9 :: v_dual_mov_b32 v51, s7
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, s8
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s4 :: v_dual_mov_b32 v55, s5
; GFX11-TRUE16-NEXT: .LBB59_5: ; %end
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v55.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v54.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v53.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v52.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v51.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v50.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v49.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v48.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v39.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v38.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v37.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v36.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v35.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v34.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v33.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v32.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v31.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v29.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v26.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v25.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v24.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: bitcast_v48f16_to_v48i16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v5
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v4
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v3
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v2
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v1
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v0
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v6
; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s29, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s44, s28, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s27, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s42, s26, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s41, s25, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s40, s24, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s15, s23, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s14, s22, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s21, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s12, s20, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s19, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s18, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s17, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s16, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s3, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s2, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s0, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s72, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s63, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s73, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s62, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s61, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s60, 16
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s74, 0
; GFX11-FAKE16-NEXT: s_mov_b32 s74, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB59_2
; GFX11-FAKE16-NEXT: ; %bb.1:
; GFX11-FAKE16-NEXT: s_mov_b32 s74, -1
; GFX11-FAKE16-NEXT: .LBB59_2: ; %Flow
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s74, s74, exec_lo
; GFX11-FAKE16-NEXT: s_cselect_b32 s74, 1, 0
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s74, 1
; GFX11-FAKE16-NEXT: s_cbranch_scc1 .LBB59_4
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s57, s72, s57
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s47, s63, s47
; GFX11-FAKE16-NEXT: v_pk_add_f16 v19, 0x200, s57 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s57, s73, s59
; GFX11-FAKE16-NEXT: v_pk_add_f16 v20, 0x200, s47 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s47, s62, s58
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s56, s61, s56
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s46, s60, s46
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s29, s29, s45
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s28, s28, s44
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s27, s27, s43
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s26, s26, s42
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s25, s25, s41
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s24, s24, s40
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s15, s23, s15
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s14, s22, s14
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s13, s21, s13
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s12, s20, s12
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s11, s19, s11
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s10, s18, s10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s9, s17, s9
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s7, s16, s7
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s3, s3, s6
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s2, s2, s8
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s0, s0, s5
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX11-FAKE16-NEXT: v_pk_add_f16 v21, 0x200, s57 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v22, 0x200, s47 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v23, 0x200, s56 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v14, 0x200, s46 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, s29 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, s28 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v17, 0x200, s27 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v18, 0x200, s26 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v9, 0x200, s25 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v10, 0x200, s24 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v11, 0x200, s15 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v12, 0x200, s14 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, 0x200, s12 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v5, 0x200, s11 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v6, 0x200, s10 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v7, 0x200, s9 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v3, 0x200, s0 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, s1 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, s2 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v0, 0x200, s3 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_pk_add_f16 v8, 0x200, s7 op_sel_hi:[0,1]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v5
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v13
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v15
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v14
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v20
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v19
; GFX11-FAKE16-NEXT: s_branch .LBB59_5
; GFX11-FAKE16-NEXT: .LBB59_4:
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v19, s72 :: v_dual_mov_b32 v20, s63
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, s73 :: v_dual_mov_b32 v22, s62
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, s61 :: v_dual_mov_b32 v14, s60
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v15, s29 :: v_dual_mov_b32 v16, s28
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v17, s27 :: v_dual_mov_b32 v18, s26
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v9, s25 :: v_dual_mov_b32 v10, s24
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, s23 :: v_dual_mov_b32 v12, s22
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, s21 :: v_dual_mov_b32 v4, s20
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, s19 :: v_dual_mov_b32 v6, s18
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, s17 :: v_dual_mov_b32 v8, s16
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s0
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, s57 :: v_dual_mov_b32 v25, s47
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, s59 :: v_dual_mov_b32 v27, s58
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v28, s56 :: v_dual_mov_b32 v29, s46
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v31, s44
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s43 :: v_dual_mov_b32 v33, s42
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s41 :: v_dual_mov_b32 v35, s40
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s15 :: v_dual_mov_b32 v37, s14
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, s13 :: v_dual_mov_b32 v39, s12
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, s11 :: v_dual_mov_b32 v49, s10
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s9 :: v_dual_mov_b32 v51, s7
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s6 :: v_dual_mov_b32 v53, s8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s4 :: v_dual_mov_b32 v55, s5
; GFX11-FAKE16-NEXT: .LBB59_5: ; %end
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v64, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v55, 16, v3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v54, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v53, 16, v64
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v52, 16, v65
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v52, 0xffff, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v51, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v50, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v48, 16, v52
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v39, 16, v53
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v39, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v38, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v37, 16, v12
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v35, 16, v39
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v34, 16, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v33, 16, v18
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v32, 16, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v30, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v29, 16, v35
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v20
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v49, 16, v6
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v36, 16, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v31, 16, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v28, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v27, 16, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v26, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v25, 16, v29
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v24, 16, v30
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
br i1 %cmp, label %cmp.true, label %cmp.false
cmp.true:
%a1 = fadd <48 x half> %a, splat (half 0xH0200)
%a2 = bitcast <48 x half> %a1 to <48 x i16>
br label %end
cmp.false:
%a3 = bitcast <48 x half> %a to <48 x i16>
br label %end
end:
%phi = phi <48 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
ret <48 x i16> %phi
}
attributes #0 = { nounwind }