llvm/test/CodeGen/AArch64/sve-frintz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mattr=+sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

; Check that fp -> int -> fp conversions can be
; lowered to the SVE FRINTZ instructions for
; scalable vectors.

define <vscale x 4 x float> @frintz_f32_i32_f32(<vscale x 4 x float> %in) {
; CHECK-LABEL: frintz_f32_i32_f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i32>
  %res2 = sitofp <vscale x 4 x i32> %res to <vscale x 4 x float>
  ret <vscale x 4 x float> %res2
}

define <vscale x 4 x float> @frintz_f32_i32_f32_nsz(<vscale x 4 x float> %in) {
; CHECK-LABEL: frintz_f32_i32_f32_nsz:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    frintz z0.s, p0/m, z0.s
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i32>
  %res2 = sitofp nsz <vscale x 4 x i32> %res to <vscale x 4 x float>
  ret <vscale x 4 x float> %res2
}

define <vscale x 2 x double> @frintz_f64_i32_f64(<vscale x 2 x double> %in) {
; CHECK-LABEL: frintz_f64_i32_f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    scvtf z0.d, p0/m, z0.d
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i32>
  %res2 = sitofp <vscale x 2 x i32> %res to <vscale x 2 x double>
  ret <vscale x 2 x double> %res2
}

define <vscale x 2 x double> @frintz_f64_i32_f64_nsz(<vscale x 2 x double> %in) {
; CHECK-LABEL: frintz_f64_i32_f64_nsz:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintz z0.d, p0/m, z0.d
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i32>
  %res2 = sitofp nsz <vscale x 2 x i32> %res to <vscale x 2 x double>
  ret <vscale x 2 x double> %res2
}

define <vscale x 8 x float> @frintz_f32_i32_f32_nxv8i32(<vscale x 8 x float> %in) {
; CHECK-LABEL: frintz_f32_i32_f32_nxv8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    fcvtzs z1.s, p0/m, z1.s
; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
; CHECK-NEXT:    scvtf z0.s, p0/m, z0.s
; CHECK-NEXT:    scvtf z1.s, p0/m, z1.s
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 8 x float> %in to <vscale x 8 x i32>
  %res2 = sitofp <vscale x 8 x i32> %res to <vscale x 8 x float>
  ret <vscale x 8 x float> %res2
}

define <vscale x 8 x float> @frintz_f32_i32_f32_nxv8i32_nsz(<vscale x 8 x float> %in) {
; CHECK-LABEL: frintz_f32_i32_f32_nxv8i32_nsz:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    frintz z0.s, p0/m, z0.s
; CHECK-NEXT:    frintz z1.s, p0/m, z1.s
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 8 x float> %in to <vscale x 8 x i32>
  %res2 = sitofp nsz <vscale x 8 x i32> %res to <vscale x 8 x float>
  ret <vscale x 8 x float> %res2
}

define <vscale x 2 x double> @frintz_f64_i64_f64(<vscale x 2 x double> %in) {
; CHECK-LABEL: frintz_f64_i64_f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    scvtf z0.d, p0/m, z0.d
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i64>
  %res2 = sitofp <vscale x 2 x i64> %res to <vscale x 2 x double>
  ret <vscale x 2 x double> %res2
}

define <vscale x 2 x double> @frintz_f64_i64_f64_nsz(<vscale x 2 x double> %in) {
; CHECK-LABEL: frintz_f64_i64_f64_nsz:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintz z0.d, p0/m, z0.d
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 2 x double> %in to <vscale x 2 x i64>
  %res2 = sitofp nsz <vscale x 2 x i64> %res to <vscale x 2 x double>
  ret <vscale x 2 x double> %res2
}

define <vscale x 4 x float> @frintz_f32_i64_f32(<vscale x 4 x float> %in) {
; CHECK-LABEL: frintz_f32_i64_f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpklo z1.d, z0.s
; CHECK-NEXT:    uunpkhi z0.d, z0.s
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    scvtf z0.s, p0/m, z0.d
; CHECK-NEXT:    scvtf z1.s, p0/m, z1.d
; CHECK-NEXT:    uzp1 z0.s, z1.s, z0.s
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i64>
  %res2 = sitofp <vscale x 4 x i64> %res to <vscale x 4 x float>
  ret <vscale x 4 x float> %res2
}

define <vscale x 4 x float> @frintz_f32_i64_f32_nsz(<vscale x 4 x float> %in) {
; CHECK-LABEL: frintz_f32_i64_f32_nsz:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    frintz z0.s, p0/m, z0.s
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 4 x float> %in to <vscale x 4 x i64>
  %res2 = sitofp nsz <vscale x 4 x i64> %res to <vscale x 4 x float>
  ret <vscale x 4 x float> %res2
}

define <vscale x 4 x double> @frintz_f64_i64_f64_nxv4i64(<vscale x 4 x double> %in) {
; CHECK-LABEL: frintz_f64_i64_f64_nxv4i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    scvtf z0.d, p0/m, z0.d
; CHECK-NEXT:    scvtf z1.d, p0/m, z1.d
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 4 x double> %in to <vscale x 4 x i64>
  %res2 = sitofp <vscale x 4 x i64> %res to <vscale x 4 x double>
  ret <vscale x 4 x double> %res2
}

define <vscale x 4 x double> @frintz_f64_i64_f64_nxv4i64_nsz(<vscale x 4 x double> %in) {
; CHECK-LABEL: frintz_f64_i64_f64_nxv4i64_nsz:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintz z0.d, p0/m, z0.d
; CHECK-NEXT:    frintz z1.d, p0/m, z1.d
; CHECK-NEXT:    ret
  %res = fptosi <vscale x 4 x double> %in to <vscale x 4 x i64>
  %res2 = sitofp nsz <vscale x 4 x i64> %res to <vscale x 4 x double>
  ret <vscale x 4 x double> %res2
}