llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s

; Not from issue 76416, but separate testcase reported on the same
; regressing commit.
define void @other_regression(i1 %cmp.not.i.i.i) {
; CHECK-LABEL: other_regression:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushq %rax
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    movl 0, %eax
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    sarl %cl, %eax
; CHECK-NEXT:    movl $1, %edx
; CHECK-NEXT:    xorl %ecx, %ecx
; CHECK-NEXT:    shrl %cl, %edx
; CHECK-NEXT:    imull %eax, %edx
; CHECK-NEXT:    movslq %edx, %rsi
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    xorl %edi, %edi
; CHECK-NEXT:    xorl %edx, %edx
; CHECK-NEXT:    callq *%rax
entry:
  br label %for.cond10.preheader

trap:                                             ; preds = %for.body13
  unreachable

for.cond10.preheader:                             ; preds = %while.cond.i.i.i, %entry
  %indvars.iv = phi i64 [ 0, %entry ], [ 1, %while.cond.i.i.i ]
  %i = trunc i64 %indvars.iv to i32
  br label %for.body13

for.body13:                                       ; preds = %for.cond10.preheader
  %i1 = load i32, ptr null, align 4
  %shr = ashr i32 %i1, %i
  %shr15 = ashr i32 1, %i
  %mul16 = mul i32 %shr15, %shr
  %conv = sext i32 %mul16 to i64
  call void null(ptr null, i64 %conv, ptr null)
  br i1 false, label %while.cond.i.i.i, label %trap

while.cond.i.i.i:                                 ; preds = %while.cond.i.i.i, %for.body13
  br i1 %cmp.not.i.i.i, label %for.cond10.preheader, label %while.cond.i.i.i
}