| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 |
| // RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck %s |
| |
| // CHECK-LABEL: define spir_func void @_Z1fv( |
| // CHECK-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[X:%.*]] = alloca half, align 2 |
| // CHECK-NEXT: [[Y:%.*]] = alloca half, align 2 |
| // CHECK-NEXT: [[Z:%.*]] = alloca half, align 2 |
| // CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[X]], align 2 |
| // CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[Y]], align 2 |
| // CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]] |
| // CHECK-NEXT: store half [[ADD]], ptr [[Z]], align 2 |
| // CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[X]], align 2 |
| // CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[Y]], align 2 |
| // CHECK-NEXT: [[SUB:%.*]] = fsub half [[TMP2]], [[TMP3]] |
| // CHECK-NEXT: store half [[SUB]], ptr [[Z]], align 2 |
| // CHECK-NEXT: [[TMP4:%.*]] = load half, ptr [[X]], align 2 |
| // CHECK-NEXT: [[TMP5:%.*]] = load half, ptr [[Y]], align 2 |
| // CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP4]], [[TMP5]] |
| // CHECK-NEXT: store half [[MUL]], ptr [[Z]], align 2 |
| // CHECK-NEXT: [[TMP6:%.*]] = load half, ptr [[X]], align 2 |
| // CHECK-NEXT: [[TMP7:%.*]] = load half, ptr [[Y]], align 2 |
| // CHECK-NEXT: [[DIV:%.*]] = fdiv half [[TMP6]], [[TMP7]] |
| // CHECK-NEXT: store half [[DIV]], ptr [[Z]], align 2 |
| // CHECK-NEXT: ret void |
| // |
| void f() { |
| _Float16 x, y, z; |
| |
| z = x + y; |
| |
| z = x - y; |
| |
| z = x * y; |
| |
| z = x / y; |
| } |
