llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs < %s \
; RUN:   -target-abi=ilp32 -mattr=+zhinx | FileCheck %s
define dso_local void @zdinx_asm(ptr nocapture noundef writeonly %a, double noundef %b, double noundef %c) nounwind {
; CHECK-LABEL: zdinx_asm:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    mv a5, a4
; CHECK-NEXT:    mv a7, a2
; CHECK-NEXT:    mv a4, a3
; CHECK-NEXT:    mv a6, a1
; CHECK-NEXT:    #APP
; CHECK-NEXT:    fsgnjx.d a2, a6, a4
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    sw a2, 8(a0)
; CHECK-NEXT:    sw a3, 12(a0)
; CHECK-NEXT:    ret
entry:
  %arrayidx = getelementptr inbounds double, ptr %a, i32 1
  %0 = tail call double asm "fsgnjx.d $0, $1, $2", "=r,r,r"(double %b, double %c)
  store double %0, ptr %arrayidx, align 8
  ret void
}

define dso_local void @zfinx_asm(ptr nocapture noundef writeonly %a, float noundef %b, float noundef %c) nounwind {
; CHECK-LABEL: zfinx_asm:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    #APP
; CHECK-NEXT:    fsgnjx.s a1, a1, a2
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    sw a1, 4(a0)
; CHECK-NEXT:    ret
entry:
  %arrayidx = getelementptr inbounds float, ptr %a, i32 1
  %0 = tail call float asm "fsgnjx.s $0, $1, $2", "=r,r,r"(float %b, float %c)
  store float %0, ptr %arrayidx, align 8
  ret void
}

define dso_local void @zhinx_asm(ptr nocapture noundef writeonly %a, half noundef %b, half noundef %c) nounwind {
; CHECK-LABEL: zhinx_asm:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    #APP
; CHECK-NEXT:    fsgnjx.h a1, a1, a2
; CHECK-NEXT:    #NO_APP
; CHECK-NEXT:    sh a1, 2(a0)
; CHECK-NEXT:    ret
entry:
  %arrayidx = getelementptr inbounds half, ptr %a, i32 1
  %0 = tail call half asm "fsgnjx.h $0, $1, $2", "=r,r,r"(half %b, half %c)
  store half %0, ptr %arrayidx, align 8
  ret void
}