llvm/test/CodeGen/NVPTX/f16-ex2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mcpu=sm_75 -mattr=+ptx70 | FileCheck --check-prefixes=CHECK-FP16 %s
; RUN: %if ptxas-11.0 %{ llc < %s -mcpu=sm_75 -mattr=+ptx70 | %ptxas-verify -arch=sm_75 %}
target triple = "nvptx64-nvidia-cuda"

declare half @llvm.nvvm.ex2.approx.f16(half)
declare <2 x half> @llvm.nvvm.ex2.approx.f16x2(<2 x half>)

; CHECK-LABEL: ex2_half
define half @ex2_half(half %0) {
; CHECK-FP16-LABEL: ex2_half(
; CHECK-FP16:       {
; CHECK-FP16-NEXT:    .reg .b16 %rs<3>;
; CHECK-FP16-EMPTY:
; CHECK-FP16-NEXT:  // %bb.0:
; CHECK-FP16-NEXT:    ld.param.b16 %rs1, [ex2_half_param_0];
; CHECK-FP16-NEXT:    ex2.approx.f16 %rs2, %rs1;
; CHECK-FP16-NEXT:    st.param.b16 [func_retval0], %rs2;
; CHECK-FP16-NEXT:    ret;
  %res = call half @llvm.nvvm.ex2.approx.f16(half %0)
  ret half %res
}

; CHECK-LABEL: ex2_2xhalf
define <2 x half> @ex2_2xhalf(<2 x half> %0) {
; CHECK-FP16-LABEL: ex2_2xhalf(
; CHECK-FP16:       {
; CHECK-FP16-NEXT:    .reg .b32 %r<3>;
; CHECK-FP16-EMPTY:
; CHECK-FP16-NEXT:  // %bb.0:
; CHECK-FP16-NEXT:    ld.param.b32 %r1, [ex2_2xhalf_param_0];
; CHECK-FP16-NEXT:    ex2.approx.f16x2 %r2, %r1;
; CHECK-FP16-NEXT:    st.param.b32 [func_retval0], %r2;
; CHECK-FP16-NEXT:    ret;
  %res = call <2 x half> @llvm.nvvm.ex2.approx.f16x2(<2 x half> %0)
  ret <2 x half> %res
}