llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=hexagon < %s | FileCheck %s

target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"

define dso_local fastcc <64 x float> @f0(<64 x float> %a0, <64 x float> %a1) unnamed_addr #0 {
; CHECK-LABEL: f0:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v4 = vxor(v4,v4)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     q0 = vcmp.gt(v4.sf,v0.sf)
; CHECK-NEXT:     q1 = vcmp.gt(v4.sf,v1.sf)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     v0 = vmux(q0,v2,v0)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:     v1 = vmux(q1,v3,v1)
; CHECK-NEXT:    }
b0:
  %v1 = fcmp ogt <64 x float> zeroinitializer, %a0
  %v2 = select <64 x i1> %v1, <64 x float> %a1, <64 x float> %a0
  ret <64 x float> %v2
}

define dso_local fastcc <128 x half> @f1(<128 x half> %a0, <128 x half> %a1) unnamed_addr #0 {
; CHECK-LABEL: f1:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v4 = vxor(v4,v4)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     q0 = vcmp.gt(v4.hf,v0.hf)
; CHECK-NEXT:     q1 = vcmp.gt(v4.hf,v1.hf)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     v0 = vmux(q0,v2,v0)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:     v1 = vmux(q1,v3,v1)
; CHECK-NEXT:    }
b0:
  %v1 = fcmp ogt <128 x half> zeroinitializer, %a0
  %v2 = select <128 x i1> %v1, <128 x half> %a1, <128 x half> %a0
  ret <128 x half> %v2
}

attributes #0 = { "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat,-hvx-ieee-fp" }