llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=hexagon < %s | FileCheck %s

define <64 x i16> @f0(<64 x half> %a0) #0 {
; CHECK-LABEL: f0:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v0.h = vcvt(v0.hf)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = fptosi <64 x half> %a0 to <64 x i16>
  ret <64 x i16> %v0
}

define <64 x i16> @f1(<64 x half> %a0) #0 {
; CHECK-LABEL: f1:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v0.uh = vcvt(v0.hf)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = fptoui <64 x half> %a0 to <64 x i16>
  ret <64 x i16> %v0
}

define <128 x i8> @f2(<128 x half> %a0) #0 {
; CHECK-LABEL: f2:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v0.b = vcvt(v1.hf,v0.hf)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = fptosi <128 x half> %a0 to <128 x i8>
  ret <128 x i8> %v0
}

define <128 x i8> @f3(<128 x half> %a0) #0 {
; CHECK-LABEL: f3:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v0.ub = vcvt(v1.hf,v0.hf)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = fptoui <128 x half> %a0 to <128 x i8>
  ret <128 x i8> %v0
}

define <64 x half> @f4(<64 x i16> %a0) #0 {
; CHECK-LABEL: f4:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v0.hf = vcvt(v0.h)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = sitofp <64 x i16> %a0 to <64 x half>
  ret <64 x half> %v0
}

define <64 x half> @f5(<64 x i16> %a0) #0 {
; CHECK-LABEL: f5:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v0.hf = vcvt(v0.uh)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = uitofp <64 x i16> %a0 to <64 x half>
  ret <64 x half> %v0
}

define <128 x half> @f6(<128 x i8> %a0) #0 {
; CHECK-LABEL: f6:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v1:0.hf = vcvt(v0.b)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = sitofp <128 x i8> %a0 to <128 x half>
  ret <128 x half> %v0
}

define <128 x half> @f7(<128 x i8> %a0) #0 {
; CHECK-LABEL: f7:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     v1:0.hf = vcvt(v0.ub)
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:    }
b0:
  %v0 = uitofp <128 x i8> %a0 to <128 x half>
  ret <128 x half> %v0
}

attributes #0 = { nounwind "target-features"="+hvxv69,+hvx-length128b,+hvx-ieee-fp,-hvx-qfloat" }