llvm/test/CodeGen/AArch64/mlicm-csr-mask.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64-unknown-linux-gnu -run-pass=greedy,machinelicm -verify-machineinstrs -o - %s | FileCheck %s

# FIXME: Running RA is needed otherwise it runs pre-RA LICM.
---
name: test
tracksRegLiveness: true
body: |
  ; CHECK-LABEL: name: test
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $x0, $w1, $x2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   B %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $x0, $w1, $x2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   renamable $q11 = MOVIv4i32 2, 8
  ; CHECK-NEXT:   BL &memset, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2, implicit-def $sp, implicit-def $x0
  ; CHECK-NEXT:   renamable $q10 = MVNIv4i32 4, 0
  ; CHECK-NEXT:   $xzr = SUBSXri $x0, 1, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 11, %bb.1, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   liveins: $q10, $q11
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $q0 = COPY $q10
  ; CHECK-NEXT:   $q1 = COPY $q11
  bb.0:
    liveins: $x0, $w1, $x2
    B %bb.1

  bb.1:
    liveins: $x0, $w1, $x2
    renamable $q11 = MOVIv4i32 2, 8
    BL &memset, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2, implicit-def $sp, implicit-def $x0
    renamable $q10 = MVNIv4i32 4, 0
    $xzr = SUBSXri $x0, 1, 0, implicit-def $nzcv
    Bcc 11, %bb.1, implicit $nzcv
    B %bb.2

  bb.2:
    liveins: $q10, $q11
    $q0 = COPY $q10
    $q1 = COPY $q11
...