llvm/test/CodeGen/AArch64/GlobalISel/combine-addv.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -mtriple aarch64-unknown-unknown -mattr=+dotprod %s -o - | FileCheck %s

---
name:            vecreduce_intrinsic
body:             |
  bb.0:
    liveins: $q0, $q1, $q2, $q3, $q4
    ; CHECK-LABEL: name: vecreduce_intrinsic
    ; CHECK: liveins: $q0, $q1, $q2, $q3, $q4
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(<4 x s32>) = COPY $q4
    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY1]](<4 x s32>), [[COPY2]](<4 x s32>), [[COPY3]](<4 x s32>), [[COPY4]](<4 x s32>)
    ; CHECK-NEXT: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.experimental.vector.partial.reduce.add), [[COPY]](<4 x s32>), [[CONCAT_VECTORS]](<16 x s32>)
    ; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[INT]](<4 x s32>)
    ; CHECK-NEXT: $w0 = COPY [[VECREDUCE_ADD]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:_(<4 x s32>) = COPY $q0
    %2:_(<4 x s32>) = COPY $q1
    %3:_(<4 x s32>) = COPY $q2
    %4:_(<4 x s32>) = COPY $q3
    %5:_(<4 x s32>) = COPY $q4
    %1:_(<16 x s32>) = G_CONCAT_VECTORS %2:_(<4 x s32>), %3:_(<4 x s32>), %4:_(<4 x s32>), %5:_(<4 x s32>)
    %6:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.experimental.vector.partial.reduce.add), %0:_(<4 x s32>), %1:_(<16 x s32>)
    %7:_(s32) = G_VECREDUCE_ADD %6:_(<4 x s32>)
    $w0 = COPY %7:_(s32)
    RET_ReallyLR implicit $w0

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