| commit | fe4f6c1a58ab4f00a88a97af01000b6783b573ee | [log] [tgz] |
|---|---|---|
| author | Luke Lau <luke@igalia.com> | Mon Jul 28 22:59:49 2025 +0800 |
| committer | GitHub <noreply@github.com> | Mon Jul 28 22:59:49 2025 +0800 |
| tree | d791a6647c08648b7bb038dbf215592fbab58ea7 | |
| parent | 4b1d5b8d4f4d09e9988c0f5ca4a35957bf99235e [diff] |
[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmin/zvfbfmin (#150882) When vectorizing with predication some loops that were previously vectorized without zvfhmin/zvfbfmin will no longer be vectorized because the masked load/store or gather/scatter cost returns illegal. This is due to a discrepancy where for these costs we check isLegalElementTypeForRVV but for regular memory accesses we don't. But for bf16 and f16 vectors we don't actually need the extension support for loads and stores, so this adds a new function which takes this into account. For regular memory accesses we should probably also e.g. return an invalid cost for i64 elements on zve32x, but it doesn't look like we have tests for this yet. We also should probably not be vectorizing these bf16/f16 loops to begin with if we don't have zvfhmin/zvfbfmin and zfhmin/zfbfmin. I think this is due to the scalar costs being too cheap. I've added tests for this in a100f6367205c6a909d68027af6a8675a8091bd9 to fix in another patch.
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