)]}'
{
  "commit": "fe4f6c1a58ab4f00a88a97af01000b6783b573ee",
  "tree": "d791a6647c08648b7bb038dbf215592fbab58ea7",
  "parents": [
    "4b1d5b8d4f4d09e9988c0f5ca4a35957bf99235e"
  ],
  "author": {
    "name": "Luke Lau",
    "email": "luke@igalia.com",
    "time": "Mon Jul 28 22:59:49 2025 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jul 28 22:59:49 2025 +0800"
  },
  "message": "[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmin/zvfbfmin (#150882)\n\nWhen vectorizing with predication some loops that were previously\nvectorized without zvfhmin/zvfbfmin will no longer be vectorized because\nthe masked load/store or gather/scatter cost returns illegal.\n\nThis is due to a discrepancy where for these costs we check\nisLegalElementTypeForRVV but for regular memory accesses we don\u0027t.\n\nBut for bf16 and f16 vectors we don\u0027t actually need the extension\nsupport for loads and stores, so this adds a new function which takes\nthis into account.\n\nFor regular memory accesses we should probably also e.g. return an\ninvalid cost for i64 elements on zve32x, but it doesn\u0027t look like we\nhave tests for this yet.\n\nWe also should probably not be vectorizing these bf16/f16 loops to begin\nwith if we don\u0027t have zvfhmin/zvfbfmin and zfhmin/zfbfmin. I think this\nis due to the scalar costs being too cheap. I\u0027ve added tests for this in\na100f6367205c6a909d68027af6a8675a8091bd9 to fix in another patch.",
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