| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=amdgpu9.08-amd-amdhsa < %s | FileCheck %s |
| |
| define amdgpu_kernel void @cannot_create_empty_or_backwards_segment(i1 %arg, i1 %arg1, i1 %arg2, i1 %arg3, i1 %arg4, i1 %arg5) { |
| ; CHECK-LABEL: cannot_create_empty_or_backwards_segment: |
| ; CHECK: ; %bb.0: ; %bb |
| ; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3] |
| ; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1] |
| ; CHECK-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CHECK-NEXT: s_add_u32 s20, s20, s17 |
| ; CHECK-NEXT: s_addc_u32 s21, s21, 0 |
| ; CHECK-NEXT: v_mov_b32_e32 v0, 0 |
| ; CHECK-NEXT: s_waitcnt lgkmcnt(0) |
| ; CHECK-NEXT: s_bitcmp1_b32 s0, 0 |
| ; CHECK-NEXT: s_cselect_b64 s[8:9], -1, 0 |
| ; CHECK-NEXT: s_bitcmp1_b32 s0, 8 |
| ; CHECK-NEXT: s_cselect_b64 s[4:5], -1, 0 |
| ; CHECK-NEXT: s_bitcmp1_b32 s0, 16 |
| ; CHECK-NEXT: s_cselect_b64 s[10:11], -1, 0 |
| ; CHECK-NEXT: s_bitcmp1_b32 s0, 24 |
| ; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0 |
| ; CHECK-NEXT: s_bitcmp1_b32 s1, 0 |
| ; CHECK-NEXT: s_cselect_b64 s[6:7], -1, 0 |
| ; CHECK-NEXT: s_bitcmp1_b32 s1, 8 |
| ; CHECK-NEXT: s_cselect_b64 s[12:13], -1, 0 |
| ; CHECK-NEXT: s_and_b64 s[0:1], exec, s[2:3] |
| ; CHECK-NEXT: s_and_b64 s[2:3], exec, s[12:13] |
| ; CHECK-NEXT: s_and_b64 s[4:5], exec, s[4:5] |
| ; CHECK-NEXT: s_and_b64 s[6:7], exec, s[6:7] |
| ; CHECK-NEXT: .LBB0_1: ; %bb6 |
| ; CHECK-NEXT: ; =>This Loop Header: Depth=1 |
| ; CHECK-NEXT: ; Child Loop BB0_2 Depth 2 |
| ; CHECK-NEXT: s_mov_b64 s[12:13], -1 |
| ; CHECK-NEXT: .LBB0_2: ; %bb7 |
| ; CHECK-NEXT: ; Parent Loop BB0_1 Depth=1 |
| ; CHECK-NEXT: ; => This Inner Loop Header: Depth=2 |
| ; CHECK-NEXT: s_and_b64 s[14:15], s[10:11], exec |
| ; CHECK-NEXT: s_cbranch_scc0 .LBB0_9 |
| ; CHECK-NEXT: ; %bb.3: ; %bb8 |
| ; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=2 |
| ; CHECK-NEXT: s_mov_b64 vcc, s[0:1] |
| ; CHECK-NEXT: s_cbranch_vccz .LBB0_5 |
| ; CHECK-NEXT: ; %bb.4: ; %bb10 |
| ; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=2 |
| ; CHECK-NEXT: s_mov_b64 vcc, s[2:3] |
| ; CHECK-NEXT: s_cbranch_vccnz .LBB0_6 |
| ; CHECK-NEXT: s_branch .LBB0_10 |
| ; CHECK-NEXT: .LBB0_5: ; %bb9 |
| ; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=2 |
| ; CHECK-NEXT: s_mov_b64 vcc, s[4:5] |
| ; CHECK-NEXT: s_cbranch_vccz .LBB0_10 |
| ; CHECK-NEXT: .LBB0_6: ; %bb13 |
| ; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=2 |
| ; CHECK-NEXT: s_mov_b64 vcc, s[4:5] |
| ; CHECK-NEXT: s_cbranch_vccz .LBB0_11 |
| ; CHECK-NEXT: ; %bb.7: ; %bb16 |
| ; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=2 |
| ; CHECK-NEXT: s_mov_b64 vcc, s[6:7] |
| ; CHECK-NEXT: s_cbranch_vccz .LBB0_2 |
| ; CHECK-NEXT: ; %bb.8: ; in Loop: Header=BB0_1 Depth=1 |
| ; CHECK-NEXT: s_mov_b64 s[14:15], 0 |
| ; CHECK-NEXT: s_mov_b64 s[16:17], 0 |
| ; CHECK-NEXT: s_and_b64 vcc, exec, s[12:13] |
| ; CHECK-NEXT: s_cbranch_vccz .LBB0_12 |
| ; CHECK-NEXT: s_branch .LBB0_14 |
| ; CHECK-NEXT: .LBB0_9: ; in Loop: Header=BB0_1 Depth=1 |
| ; CHECK-NEXT: s_mov_b64 s[14:15], 0 |
| ; CHECK-NEXT: s_mov_b64 s[16:17], -1 |
| ; CHECK-NEXT: s_and_b64 vcc, exec, s[12:13] |
| ; CHECK-NEXT: s_cbranch_vccz .LBB0_12 |
| ; CHECK-NEXT: s_branch .LBB0_14 |
| ; CHECK-NEXT: .LBB0_10: ; in Loop: Header=BB0_1 Depth=1 |
| ; CHECK-NEXT: s_mov_b64 s[16:17], 0 |
| ; CHECK-NEXT: s_mov_b64 s[14:15], -1 |
| ; CHECK-NEXT: s_cbranch_execz .LBB0_12 |
| ; CHECK-NEXT: s_branch .LBB0_14 |
| ; CHECK-NEXT: .LBB0_11: ; in Loop: Header=BB0_1 Depth=1 |
| ; CHECK-NEXT: ; implicit-def: $sgpr14_sgpr15 |
| ; CHECK-NEXT: ; implicit-def: $sgpr16_sgpr17 |
| ; CHECK-NEXT: .LBB0_12: ; %bb14 |
| ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1 |
| ; CHECK-NEXT: s_and_b64 s[12:13], s[8:9], exec |
| ; CHECK-NEXT: s_cbranch_scc0 .LBB0_1 |
| ; CHECK-NEXT: ; %bb.13: ; %bb15 |
| ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1 |
| ; CHECK-NEXT: buffer_store_dword v0, off, s[20:23], 0 offset:4 |
| ; CHECK-NEXT: buffer_store_dword v0, off, s[20:23], 0 |
| ; CHECK-NEXT: s_branch .LBB0_1 |
| ; CHECK-NEXT: .LBB0_14: ; %loop.exit.guard |
| ; CHECK-NEXT: s_and_b64 vcc, exec, s[16:17] |
| ; CHECK-NEXT: s_cbranch_vccnz .LBB0_19 |
| ; CHECK-NEXT: ; %bb.15: ; %loop.exit.guard5 |
| ; CHECK-NEXT: s_and_b64 vcc, exec, s[14:15] |
| ; CHECK-NEXT: s_cbranch_vccnz .LBB0_20 |
| ; CHECK-NEXT: ; %bb.16: ; %bb17 |
| ; CHECK-NEXT: s_mov_b64 vcc, s[0:1] |
| ; CHECK-NEXT: s_cbranch_vccz .LBB0_18 |
| ; CHECK-NEXT: ; %bb.17: ; %bb19 |
| ; CHECK-NEXT: s_and_b64 s[0:1], s[8:9], exec |
| ; CHECK-NEXT: s_cbranch_scc1 .LBB0_19 |
| ; CHECK-NEXT: .LBB0_18: ; %bb18 |
| ; CHECK-NEXT: s_endpgm |
| ; CHECK-NEXT: .LBB0_19: ; %bb20 |
| ; CHECK-NEXT: .LBB0_20: ; %bb12 |
| bb: |
| br label %bb6 |
| |
| bb6: ; preds = %bb15, %bb14, %bb |
| br label %bb7 |
| |
| bb7: ; preds = %bb16, %bb6 |
| br i1 %arg2, label %bb8, label %bb20 |
| |
| bb8: ; preds = %bb7 |
| br i1 %arg3, label %bb10, label %bb9 |
| |
| bb9: ; preds = %bb8 |
| br i1 %arg1, label %bb13, label %bb12 |
| |
| bb10: ; preds = %bb8 |
| br i1 %arg5, label %bb11, label %bb12 |
| |
| bb11: ; preds = %bb10 |
| br label %bb13 |
| |
| bb12: ; preds = %bb10, %bb9 |
| unreachable |
| |
| bb13: ; preds = %bb11, %bb9 |
| br i1 %arg1, label %bb16, label %bb14 |
| |
| bb14: ; preds = %bb13 |
| br i1 %arg, label %bb15, label %bb6 |
| |
| bb15: ; preds = %bb14 |
| store double 0.000000e+00, ptr addrspace(5) zeroinitializer, align 2147483648 |
| br label %bb6 |
| |
| bb16: ; preds = %bb13 |
| br i1 %arg4, label %bb17, label %bb7 |
| |
| bb17: ; preds = %bb16 |
| br i1 %arg3, label %bb19, label %bb18 |
| |
| bb18: ; preds = %bb17 |
| ret void |
| |
| bb19: ; preds = %bb17 |
| br i1 %arg, label %bb20, label %bb21 |
| |
| bb20: ; preds = %bb19, %bb7 |
| unreachable |
| |
| bb21: ; preds = %bb19 |
| ret void |
| } |
