llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-1x.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple aarch64 -O0 -global-isel -o - %s | FileCheck %s

define <1 x i1> @shuffle_extract_4(<8 x i1> %a, <8 x i1> %b) {
; CHECK-LABEL: shuffle_extract_4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
; CHECK-NEXT:    umov w8, v0.h[4]
; CHECK-NEXT:    and w0, w8, #0x1
; CHECK-NEXT:    ret
  %extractvec60 = shufflevector <8 x i1> %a, <8 x i1> %b, <1 x i32> <i32 4>
  ret <1 x i1> %extractvec60
}

define <1 x i1> @shuffle_extract_12(<8 x i1> %a, <8 x i1> %b) {
; CHECK-LABEL: shuffle_extract_12:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ushll v0.8h, v1.8b, #0
; CHECK-NEXT:    umov w8, v0.h[4]
; CHECK-NEXT:    and w0, w8, #0x1
; CHECK-NEXT:    ret
  %extractvec60 = shufflevector <8 x i1> %a, <8 x i1> %b, <1 x i32> <i32 12>
  ret <1 x i1> %extractvec60
}

define <1 x i1> @shuffle_extract_p(<8 x i1> %a, <8 x i1> %b) {
; CHECK-LABEL: shuffle_extract_p:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // implicit-def: $w8
; CHECK-NEXT:    and w0, w8, #0x1
; CHECK-NEXT:    ret
  %extractvec60 = shufflevector <8 x i1> %a, <8 x i1> %b, <1 x i32> <i32 poison>
  ret <1 x i1> %extractvec60
}

define <1 x i32> @shufflevector_v1i32(<1 x i32> %a, <1 x i32> %b) {
; CHECK-LABEL: shufflevector_v1i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, d1
; CHECK-NEXT:    ret
    %c = shufflevector <1 x i32> %a, <1 x i32> %b, <1 x i32> <i32 1>
    ret <1 x i32> %c
}