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llvm/llvm-project/f42b930af976e73fcf52e28d77ac6d94883bf950/./llvm/test/Transforms/LoopVectorize/RISCV
tree: f42cade701ebdb68f59f81f9e58420116290253d
  1. defaults.ll
  2. divrem.ll
  3. force-vect-msg.ll
  4. illegal-type.ll
  5. inloop-reduction.ll
  6. interleaved-accesses-zve32x.ll
  7. interleaved-accesses.ll
  8. interleaved-cost.ll
  9. lit.local.cfg
  10. lmul.ll
  11. low-trip-count.ll
  12. mask-index-type.ll
  13. masked_gather_scatter.ll
  14. ordered-reduction.ll
  15. reg-usage.ll
  16. riscv-interleaved.ll
  17. riscv-unroll.ll
  18. riscv-vector-reverse.ll
  19. safe-dep-distance.ll
  20. scalable-basics.ll
  21. scalable-reductions.ll
  22. scalable-tailfold.ll
  23. scalable-vf-hint.ll
  24. select-cmp-reduction.ll
  25. short-trip-count.ll
  26. strided-accesses.ll
  27. uniform-load-store.ll
  28. unroll-in-loop-vectorizer.ll
  29. zvl32b.ll