llvm/test/Transforms/SandboxVectorizer/Passes/Common/alignment.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=sandbox-vectorizer -sbvec-passes="seed-collection(stores)<bundle-vec(bottom-up)>" -sbvec-vec-reg-bits=1024 %s -S | FileCheck %s --check-prefix=BNDL
; RUN: opt -passes=sandbox-vectorizer -sbvec-passes="seed-collection(stores)<load-store-vec>" -sbvec-vec-reg-bits=1024 %s -S | FileCheck %s --check-prefix=LSV


; Check that the vector loads and stores have the expected alignment.


; %ld0 loads 2 bytes. If %ld0 and %ld1 load consecutive mem addresses
; we could deduce that %ld0 actually has an alignment of 2, same for
; the vector load.
define void @alignment_f16(ptr %ptr0) {
; BNDL-LABEL: define void @alignment_f16(
; BNDL-SAME: ptr [[PTR0:%.*]]) {
; BNDL-NEXT:    [[VECL:%.*]] = load <2 x half>, ptr [[PTR0]], align 1, !sandboxvec [[META0:![0-9]+]]
; BNDL-NEXT:    store <2 x half> [[VECL]], ptr [[PTR0]], align 4, !sandboxvec [[META0]]
; BNDL-NEXT:    ret void
;
; LSV-LABEL: define void @alignment_f16(
; LSV-SAME: ptr [[PTR0:%.*]]) {
; LSV-NEXT:    [[VECIINITL:%.*]] = load <2 x half>, ptr [[PTR0]], align 1, !sandboxvec [[META0:![0-9]+]]
; LSV-NEXT:    store <2 x half> [[VECIINITL]], ptr [[PTR0]], align 4, !sandboxvec [[META0]]
; LSV-NEXT:    ret void
;
  %ptr1 = getelementptr inbounds i8, ptr %ptr0, i64 2

  %ld0 = load half, ptr %ptr0, align 1
  %ld1 = load half, ptr %ptr1, align 4

  store half %ld0, ptr %ptr0, align 4
  store half %ld1, ptr %ptr1, align 1
  ret void
}

; %ld0 loads 4 bytes. If %ld0 and %ld1 load consecutive mem addresses
; we could deduce that %ld0 actually has an alignment of 4, same for
; the vector load.
define void @alignment_f32(ptr %ptr0) {
; BNDL-LABEL: define void @alignment_f32(
; BNDL-SAME: ptr [[PTR0:%.*]]) {
; BNDL-NEXT:    [[VECL:%.*]] = load <2 x float>, ptr [[PTR0]], align 1, !sandboxvec [[META1:![0-9]+]]
; BNDL-NEXT:    store <2 x float> [[VECL]], ptr [[PTR0]], align 4, !sandboxvec [[META1]]
; BNDL-NEXT:    ret void
;
; LSV-LABEL: define void @alignment_f32(
; LSV-SAME: ptr [[PTR0:%.*]]) {
; LSV-NEXT:    [[VECIINITL:%.*]] = load <2 x float>, ptr [[PTR0]], align 1, !sandboxvec [[META1:![0-9]+]]
; LSV-NEXT:    store <2 x float> [[VECIINITL]], ptr [[PTR0]], align 4, !sandboxvec [[META1]]
; LSV-NEXT:    ret void
;
  %ptr1 = getelementptr inbounds i8, ptr %ptr0, i64 4

  %ld0 = load float, ptr %ptr0, align 1
  %ld1 = load float, ptr %ptr1, align 4

  store float %ld0, ptr %ptr0, align 4
  store float %ld1, ptr %ptr1, align 1
  ret void
}

; %ld0 loads 8 bytes. If %ld0 and %ld1 load consecutive mem addresses
; we could deduce that %ld0 actually has an alignment of 4, same for
; the vector load.
define void @alignment_f64(ptr %ptr0) {
; BNDL-LABEL: define void @alignment_f64(
; BNDL-SAME: ptr [[PTR0:%.*]]) {
; BNDL-NEXT:    [[VECL:%.*]] = load <2 x double>, ptr [[PTR0]], align 1, !sandboxvec [[META2:![0-9]+]]
; BNDL-NEXT:    store <2 x double> [[VECL]], ptr [[PTR0]], align 4, !sandboxvec [[META2]]
; BNDL-NEXT:    ret void
;
; LSV-LABEL: define void @alignment_f64(
; LSV-SAME: ptr [[PTR0:%.*]]) {
; LSV-NEXT:    [[VECIINITL:%.*]] = load <2 x double>, ptr [[PTR0]], align 1, !sandboxvec [[META2:![0-9]+]]
; LSV-NEXT:    store <2 x double> [[VECIINITL]], ptr [[PTR0]], align 4, !sandboxvec [[META2]]
; LSV-NEXT:    ret void
;
  %ptr1 = getelementptr inbounds i8, ptr %ptr0, i64 8

  %ld0 = load double, ptr %ptr0, align 1
  %ld1 = load double, ptr %ptr1, align 4

  store double %ld0, ptr %ptr0, align 4
  store double %ld1, ptr %ptr1, align 1
  ret void
}
;.
; BNDL: [[META0]] = distinct !{!"sandboxregion"}
; BNDL: [[META1]] = distinct !{!"sandboxregion"}
; BNDL: [[META2]] = distinct !{!"sandboxregion"}
;.
; LSV: [[META0]] = distinct !{!"sandboxregion"}
; LSV: [[META1]] = distinct !{!"sandboxregion"}
; LSV: [[META2]] = distinct !{!"sandboxregion"}
;.