| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 | |
| ; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s --check-prefixes=CHECK,CHECK-VF4UF1 | |
| ; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=4 -S %s | FileCheck %s --check-prefixes=CHECK,CHECK-VF4UF4 | |
| ; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=4 -S %s | FileCheck %s --check-prefixes=CHECK,CHECK-VF1UF4 | |
| define i64 @smax_idx(ptr nocapture readonly %a, i64 %mm, i64 %ii, ptr nocapture writeonly %res_max, i64 %n) { | |
| ; CHECK-VF4UF1-LABEL: define i64 @smax_idx( | |
| ; CHECK-VF4UF1-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4UF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4UF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP2]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP3:%.*]] = icmp slt <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI1]] | |
| ; CHECK-VF4UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | |
| ; CHECK-VF4UF1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP2]]) | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i64> poison, i64 [[TMP6]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT2]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT3]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP4]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF1-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP6]], [[MM]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[II]], i64 [[TMP9]] | |
| ; CHECK-VF4UF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF1: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX4:%.*]] = phi i64 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF1: [[LOOP]]: | |
| ; CHECK-VF4UF1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP13:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX4]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP12]]) | |
| ; CHECK-VF4UF1-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP12]] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF1-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] | |
| ; CHECK-VF4UF1: [[EXIT]]: | |
| ; CHECK-VF4UF1-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP13]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF1-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF4UF4-LABEL: define i64 @smax_idx( | |
| ; CHECK-VF4UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i64> [[STEP_ADD]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i64> [[STEP_ADD_2]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP2]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i64>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i64>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP5]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP6]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP7]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI2]], <4 x i64> [[WIDE_LOAD9]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP8]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI3]], <4 x i64> [[WIDE_LOAD10]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP9:%.*]] = icmp slt <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP10:%.*]] = icmp slt <4 x i64> [[VEC_PHI1]], [[WIDE_LOAD8]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP11:%.*]] = icmp slt <4 x i64> [[VEC_PHI2]], [[WIDE_LOAD9]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP12:%.*]] = icmp slt <4 x i64> [[VEC_PHI3]], [[WIDE_LOAD10]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI4]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI5]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI6]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI7]] | |
| ; CHECK-VF4UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[STEP_ADD_3]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | |
| ; CHECK-VF4UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP5]], <4 x i64> [[TMP6]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP7]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX11]], <4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX12]]) | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT13:%.*]] = insertelement <4 x i64> poison, i64 [[TMP18]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT14:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT13]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: [[TMP19:%.*]] = icmp eq <4 x i64> [[TMP5]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP20:%.*]] = icmp eq <4 x i64> [[TMP6]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP21:%.*]] = icmp eq <4 x i64> [[TMP7]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP22:%.*]] = icmp eq <4 x i64> [[TMP8]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP23:%.*]] = select <4 x i1> [[TMP19]], <4 x i64> [[TMP13]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP20]], <4 x i64> [[TMP14]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP21]], <4 x i64> [[TMP15]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP26:%.*]] = select <4 x i1> [[TMP22]], <4 x i64> [[TMP16]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX15:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[TMP23]], <4 x i64> [[TMP24]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX16:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[RDX_MINMAX15]], <4 x i64> [[TMP25]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX17:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[RDX_MINMAX16]], <4 x i64> [[TMP26]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP27:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[RDX_MINMAX17]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP18]], [[MM]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[II]], i64 [[TMP27]] | |
| ; CHECK-VF4UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP18]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX18:%.*]] = phi i64 [ [[TMP29]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF4: [[LOOP]]: | |
| ; CHECK-VF4UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP31:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX18]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP30:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP31]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP30]]) | |
| ; CHECK-VF4UF4-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP30]] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] | |
| ; CHECK-VF4UF4: [[EXIT]]: | |
| ; CHECK-VF4UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP31]], %[[LOOP]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP29]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF1UF4-LABEL: define i64 @smax_idx( | |
| ; CHECK-VF1UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF1UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI4:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI5:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI6:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI7:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1UF4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP12]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI]], i64 [[TMP8]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI1]], i64 [[TMP9]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP14]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI2]], i64 [[TMP10]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP15]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI3]], i64 [[TMP11]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP16:%.*]] = icmp slt i64 [[VEC_PHI]], [[TMP8]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP17:%.*]] = icmp slt i64 [[VEC_PHI1]], [[TMP9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP18:%.*]] = icmp slt i64 [[VEC_PHI2]], [[TMP10]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP19:%.*]] = icmp slt i64 [[VEC_PHI3]], [[TMP11]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP20]] = select i1 [[TMP16]], i64 [[INDEX]], i64 [[VEC_PHI4]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP21]] = select i1 [[TMP17]], i64 [[TMP1]], i64 [[VEC_PHI5]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP22]] = select i1 [[TMP18]], i64 [[TMP2]], i64 [[VEC_PHI6]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP23]] = select i1 [[TMP19]], i64 [[TMP3]], i64 [[VEC_PHI7]] | |
| ; CHECK-VF1UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | |
| ; CHECK-VF1UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP12]], i64 [[TMP13]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX8:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP14]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX9:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX8]], i64 [[TMP15]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[TMP12]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP13]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP27:%.*]] = icmp eq i64 [[TMP14]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP15]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i64 [[TMP20]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP30:%.*]] = select i1 [[TMP26]], i64 [[TMP21]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP31:%.*]] = select i1 [[TMP27]], i64 [[TMP22]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP32:%.*]] = select i1 [[TMP28]], i64 [[TMP23]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP29]], i64 [[TMP30]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX11:%.*]] = call i64 @llvm.umin.i64(i64 [[RDX_MINMAX10]], i64 [[TMP31]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX12:%.*]] = call i64 @llvm.umin.i64(i64 [[RDX_MINMAX11]], i64 [[TMP32]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP33:%.*]] = icmp eq i64 [[RDX_MINMAX9]], [[MM]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i64 [[II]], i64 [[RDX_MINMAX12]] | |
| ; CHECK-VF1UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX13:%.*]] = phi i64 [ [[TMP34]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1UF4: [[LOOP]]: | |
| ; CHECK-VF1UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP36:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX13]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP35:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP36]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP35]]) | |
| ; CHECK-VF1UF4-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP35]] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF1UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] | |
| ; CHECK-VF1UF4: [[EXIT]]: | |
| ; CHECK-VF1UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP36]], %[[LOOP]] ], [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP34]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF1UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %1, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %1 = tail call i64 @llvm.smax.i64(i64 %max, i64 %0) | |
| %cmp1 = icmp slt i64 %max, %0 | |
| %spec.select7 = select i1 %cmp1, i64 %iv, i64 %max.idx | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| store i64 %1, ptr %res_max | |
| ret i64 %spec.select7 | |
| } | |
| ; | |
| ; Check the different order of reduction phis. | |
| ; | |
| define i64 @smax_idx_inverted_phi(ptr nocapture readonly %a, i64 %mm, i64 %ii, ptr nocapture writeonly %res_max, i64 %n) { | |
| ; CHECK-VF4UF1-LABEL: define i64 @smax_idx_inverted_phi( | |
| ; CHECK-VF4UF1-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4UF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4UF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP2]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP3:%.*]] = icmp slt <4 x i64> [[VEC_PHI1]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] | |
| ; CHECK-VF4UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] | |
| ; CHECK-VF4UF1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP2]]) | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i64> poison, i64 [[TMP6]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT2]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT3]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP4]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF1-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP6]], [[MM]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[II]], i64 [[TMP9]] | |
| ; CHECK-VF4UF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF1: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX4:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF1: [[LOOP]]: | |
| ; CHECK-VF4UF1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX4]], %[[SCALAR_PH]] ], [ [[TMP13:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP12]]) | |
| ; CHECK-VF4UF1-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP12]] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF1-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] | |
| ; CHECK-VF4UF1: [[EXIT]]: | |
| ; CHECK-VF4UF1-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP13]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF1-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF4UF4-LABEL: define i64 @smax_idx_inverted_phi( | |
| ; CHECK-VF4UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i64> [[STEP_ADD]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i64> [[STEP_ADD_2]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP2]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i64>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i64>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP5]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI4]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP6]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI5]], <4 x i64> [[WIDE_LOAD8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP7]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI6]], <4 x i64> [[WIDE_LOAD9]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP8]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI7]], <4 x i64> [[WIDE_LOAD10]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP9:%.*]] = icmp slt <4 x i64> [[VEC_PHI4]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP10:%.*]] = icmp slt <4 x i64> [[VEC_PHI5]], [[WIDE_LOAD8]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP11:%.*]] = icmp slt <4 x i64> [[VEC_PHI6]], [[WIDE_LOAD9]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP12:%.*]] = icmp slt <4 x i64> [[VEC_PHI7]], [[WIDE_LOAD10]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI1]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI2]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI3]] | |
| ; CHECK-VF4UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[STEP_ADD_3]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] | |
| ; CHECK-VF4UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP5]], <4 x i64> [[TMP6]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP7]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX11]], <4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX12]]) | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT13:%.*]] = insertelement <4 x i64> poison, i64 [[TMP18]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT14:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT13]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: [[TMP19:%.*]] = icmp eq <4 x i64> [[TMP5]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP20:%.*]] = icmp eq <4 x i64> [[TMP6]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP21:%.*]] = icmp eq <4 x i64> [[TMP7]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP22:%.*]] = icmp eq <4 x i64> [[TMP8]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP23:%.*]] = select <4 x i1> [[TMP19]], <4 x i64> [[TMP13]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP20]], <4 x i64> [[TMP14]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP21]], <4 x i64> [[TMP15]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP26:%.*]] = select <4 x i1> [[TMP22]], <4 x i64> [[TMP16]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX15:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[TMP23]], <4 x i64> [[TMP24]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX16:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[RDX_MINMAX15]], <4 x i64> [[TMP25]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX17:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[RDX_MINMAX16]], <4 x i64> [[TMP26]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP27:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[RDX_MINMAX17]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP18]], [[MM]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[II]], i64 [[TMP27]] | |
| ; CHECK-VF4UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP29]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX18:%.*]] = phi i64 [ [[TMP18]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF4: [[LOOP]]: | |
| ; CHECK-VF4UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX18]], %[[SCALAR_PH]] ], [ [[TMP31:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP30:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP31]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP30]]) | |
| ; CHECK-VF4UF4-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP30]] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] | |
| ; CHECK-VF4UF4: [[EXIT]]: | |
| ; CHECK-VF4UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP31]], %[[LOOP]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP29]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF1UF4-LABEL: define i64 @smax_idx_inverted_phi( | |
| ; CHECK-VF1UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF1UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI4:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI5:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI6:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI7:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1UF4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP12]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI4]], i64 [[TMP8]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI5]], i64 [[TMP9]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP14]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI6]], i64 [[TMP10]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP15]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI7]], i64 [[TMP11]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP16:%.*]] = icmp slt i64 [[VEC_PHI4]], [[TMP8]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP17:%.*]] = icmp slt i64 [[VEC_PHI5]], [[TMP9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP18:%.*]] = icmp slt i64 [[VEC_PHI6]], [[TMP10]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP19:%.*]] = icmp slt i64 [[VEC_PHI7]], [[TMP11]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP20]] = select i1 [[TMP16]], i64 [[INDEX]], i64 [[VEC_PHI]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP21]] = select i1 [[TMP17]], i64 [[TMP1]], i64 [[VEC_PHI1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP22]] = select i1 [[TMP18]], i64 [[TMP2]], i64 [[VEC_PHI2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP23]] = select i1 [[TMP19]], i64 [[TMP3]], i64 [[VEC_PHI3]] | |
| ; CHECK-VF1UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] | |
| ; CHECK-VF1UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP12]], i64 [[TMP13]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX8:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP14]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX9:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX8]], i64 [[TMP15]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[TMP12]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP13]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP27:%.*]] = icmp eq i64 [[TMP14]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP15]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i64 [[TMP20]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP30:%.*]] = select i1 [[TMP26]], i64 [[TMP21]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP31:%.*]] = select i1 [[TMP27]], i64 [[TMP22]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP32:%.*]] = select i1 [[TMP28]], i64 [[TMP23]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP29]], i64 [[TMP30]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX11:%.*]] = call i64 @llvm.umin.i64(i64 [[RDX_MINMAX10]], i64 [[TMP31]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX12:%.*]] = call i64 @llvm.umin.i64(i64 [[RDX_MINMAX11]], i64 [[TMP32]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP33:%.*]] = icmp eq i64 [[RDX_MINMAX9]], [[MM]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i64 [[II]], i64 [[RDX_MINMAX12]] | |
| ; CHECK-VF1UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP34]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX13:%.*]] = phi i64 [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1UF4: [[LOOP]]: | |
| ; CHECK-VF1UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX13]], %[[SCALAR_PH]] ], [ [[TMP36:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP35:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP36]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP35]]) | |
| ; CHECK-VF1UF4-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP35]] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF1UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] | |
| ; CHECK-VF1UF4: [[EXIT]]: | |
| ; CHECK-VF1UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP36]], %[[LOOP]] ], [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP34]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF1UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %1, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %1 = tail call i64 @llvm.smax.i64(i64 %max, i64 %0) | |
| %cmp1 = icmp slt i64 %max, %0 | |
| %spec.select7 = select i1 %cmp1, i64 %iv, i64 %max.idx | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| store i64 %1, ptr %res_max | |
| ret i64 %spec.select7 | |
| } | |
| ; Check if it is a min/max with index (MMI) pattern when the | |
| ; min/max value is not used outside the loop. | |
| ; | |
| ; Currently, the vectorizer checks if smax value is used outside | |
| ; the loop. However, even if only the index part has external users, | |
| ; and smax itself does not have external users, it can still form a | |
| ; MMI pattern. | |
| ; | |
| define i64 @smax_idx_max_no_exit_user(ptr nocapture readonly %a, i64 %mm, i64 %ii, i64 %n) { | |
| ; CHECK-VF4UF1-LABEL: define i64 @smax_idx_max_no_exit_user( | |
| ; CHECK-VF4UF1-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4UF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4UF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP2]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP3:%.*]] = icmp slt <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI1]] | |
| ; CHECK-VF4UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] | |
| ; CHECK-VF4UF1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP2]]) | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i64> poison, i64 [[TMP6]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT2]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT3]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP4]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF1-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP6]], [[MM]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[II]], i64 [[TMP9]] | |
| ; CHECK-VF4UF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF1: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX4:%.*]] = phi i64 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF1: [[LOOP]]: | |
| ; CHECK-VF4UF1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP13:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX4]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP12]]) | |
| ; CHECK-VF4UF1-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP12]] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF1-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] | |
| ; CHECK-VF4UF1: [[EXIT]]: | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF4UF4-LABEL: define i64 @smax_idx_max_no_exit_user( | |
| ; CHECK-VF4UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i64> [ poison, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i64> [[STEP_ADD]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i64> [[STEP_ADD_2]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP2]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i64>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i64>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP5]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP6]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP7]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI2]], <4 x i64> [[WIDE_LOAD9]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP8]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI3]], <4 x i64> [[WIDE_LOAD10]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP9:%.*]] = icmp slt <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP10:%.*]] = icmp slt <4 x i64> [[VEC_PHI1]], [[WIDE_LOAD8]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP11:%.*]] = icmp slt <4 x i64> [[VEC_PHI2]], [[WIDE_LOAD9]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP12:%.*]] = icmp slt <4 x i64> [[VEC_PHI3]], [[WIDE_LOAD10]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI4]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI5]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI6]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI7]] | |
| ; CHECK-VF4UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[STEP_ADD_3]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] | |
| ; CHECK-VF4UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP5]], <4 x i64> [[TMP6]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP7]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX11]], <4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX12]]) | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT13:%.*]] = insertelement <4 x i64> poison, i64 [[TMP18]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT14:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT13]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: [[TMP19:%.*]] = icmp eq <4 x i64> [[TMP5]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP20:%.*]] = icmp eq <4 x i64> [[TMP6]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP21:%.*]] = icmp eq <4 x i64> [[TMP7]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP22:%.*]] = icmp eq <4 x i64> [[TMP8]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP23:%.*]] = select <4 x i1> [[TMP19]], <4 x i64> [[TMP13]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP20]], <4 x i64> [[TMP14]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP21]], <4 x i64> [[TMP15]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[TMP26:%.*]] = select <4 x i1> [[TMP22]], <4 x i64> [[TMP16]], <4 x i64> splat (i64 -1) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX15:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[TMP23]], <4 x i64> [[TMP24]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX16:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[RDX_MINMAX15]], <4 x i64> [[TMP25]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX17:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[RDX_MINMAX16]], <4 x i64> [[TMP26]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP27:%.*]] = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> [[RDX_MINMAX17]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP18]], [[MM]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[II]], i64 [[TMP27]] | |
| ; CHECK-VF4UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP18]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX18:%.*]] = phi i64 [ [[TMP29]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF4: [[LOOP]]: | |
| ; CHECK-VF4UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP31:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX18]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP30:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP31]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP30]]) | |
| ; CHECK-VF4UF4-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP30]] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] | |
| ; CHECK-VF4UF4: [[EXIT]]: | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP29]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF1UF4-LABEL: define i64 @smax_idx_max_no_exit_user( | |
| ; CHECK-VF1UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF1UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI4:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI5:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI6:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI7:%.*]] = phi i64 [ poison, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1UF4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP12]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI]], i64 [[TMP8]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI1]], i64 [[TMP9]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP14]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI2]], i64 [[TMP10]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP15]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI3]], i64 [[TMP11]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP16:%.*]] = icmp slt i64 [[VEC_PHI]], [[TMP8]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP17:%.*]] = icmp slt i64 [[VEC_PHI1]], [[TMP9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP18:%.*]] = icmp slt i64 [[VEC_PHI2]], [[TMP10]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP19:%.*]] = icmp slt i64 [[VEC_PHI3]], [[TMP11]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP20]] = select i1 [[TMP16]], i64 [[INDEX]], i64 [[VEC_PHI4]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP21]] = select i1 [[TMP17]], i64 [[TMP1]], i64 [[VEC_PHI5]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP22]] = select i1 [[TMP18]], i64 [[TMP2]], i64 [[VEC_PHI6]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP23]] = select i1 [[TMP19]], i64 [[TMP3]], i64 [[VEC_PHI7]] | |
| ; CHECK-VF1UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] | |
| ; CHECK-VF1UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP12]], i64 [[TMP13]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX8:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP14]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX9:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX8]], i64 [[TMP15]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[TMP12]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP13]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP27:%.*]] = icmp eq i64 [[TMP14]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP15]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i64 [[TMP20]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP30:%.*]] = select i1 [[TMP26]], i64 [[TMP21]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP31:%.*]] = select i1 [[TMP27]], i64 [[TMP22]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP32:%.*]] = select i1 [[TMP28]], i64 [[TMP23]], i64 -1 | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP29]], i64 [[TMP30]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX11:%.*]] = call i64 @llvm.umin.i64(i64 [[RDX_MINMAX10]], i64 [[TMP31]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX12:%.*]] = call i64 @llvm.umin.i64(i64 [[RDX_MINMAX11]], i64 [[TMP32]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP33:%.*]] = icmp eq i64 [[RDX_MINMAX9]], [[MM]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i64 [[II]], i64 [[RDX_MINMAX12]] | |
| ; CHECK-VF1UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX13:%.*]] = phi i64 [ [[TMP34]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1UF4: [[LOOP]]: | |
| ; CHECK-VF1UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP36:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX13]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP35:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP36]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP35]]) | |
| ; CHECK-VF1UF4-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP35]] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF1UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] | |
| ; CHECK-VF1UF4: [[EXIT]]: | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP34]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %1, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %1 = tail call i64 @llvm.smax.i64(i64 %max, i64 %0) | |
| %cmp1 = icmp slt i64 %max, %0 | |
| %spec.select7 = select i1 %cmp1, i64 %iv, i64 %max.idx | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| ; %1 has no external users | |
| ret i64 %spec.select7 | |
| } | |
| ; Check smax implemented by select(cmp()). | |
| ; | |
| ; Currently, MMI pattern does not support icmp with multiple users. | |
| ; TODO: It may be possible to reuse some of the methods in instcombine pass to | |
| ; check whether icmp can be duplicated. | |
| ; | |
| define i64 @smax_idx_select_cmp(ptr nocapture readonly %a, i64 %mm, i64 %ii, ptr nocapture writeonly %res_max, i64 %n) { | |
| ; CHECK-LABEL: define i64 @smax_idx_select_cmp( | |
| ; CHECK-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK: [[LOOP]]: | |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[MAX:%.*]] = phi i64 [ [[MM]], %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[II]], %[[ENTRY]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP0]] | |
| ; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i64 [[TMP0]], i64 [[MAX]] | |
| ; CHECK-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ] | |
| ; CHECK-NEXT: store i64 [[SPEC_SELECT_LCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %spec.select, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %cmp1 = icmp slt i64 %max, %0 | |
| %spec.select = select i1 %cmp1, i64 %0, i64 %max | |
| %spec.select7 = select i1 %cmp1, i64 %iv, i64 %max.idx | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| store i64 %spec.select, ptr %res_max | |
| ret i64 %spec.select7 | |
| } | |
| ; | |
| ; Check sge case. | |
| ; | |
| define i64 @smax_idx_inverted_pred(ptr nocapture readonly %a, i64 %mm, i64 %ii, ptr nocapture writeonly %res_max, i64 %n) { | |
| ; CHECK-VF4UF1-LABEL: define i64 @smax_idx_inverted_pred( | |
| ; CHECK-VF4UF1-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4UF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4UF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP2]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP3:%.*]] = icmp sge <4 x i64> [[WIDE_LOAD]], [[VEC_PHI]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI1]] | |
| ; CHECK-VF4UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] | |
| ; CHECK-VF4UF1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP2]]) | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i64> poison, i64 [[TMP6]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT2]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT3]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP4]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF1-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP9]], -9223372036854775808 | |
| ; CHECK-VF4UF1-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 [[II]] | |
| ; CHECK-VF4UF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF1: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX4:%.*]] = phi i64 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF1: [[LOOP]]: | |
| ; CHECK-VF4UF1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP13:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX4]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP12]]) | |
| ; CHECK-VF4UF1-NEXT: [[CMP1:%.*]] = icmp sge i64 [[TMP12]], [[MAX]] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF1-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] | |
| ; CHECK-VF4UF1: [[EXIT]]: | |
| ; CHECK-VF4UF1-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP13]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF1-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF4UF4-LABEL: define i64 @smax_idx_inverted_pred( | |
| ; CHECK-VF4UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i64> [[STEP_ADD]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i64> [[STEP_ADD_2]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP2]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i64>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i64>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP5]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP6]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP7]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI2]], <4 x i64> [[WIDE_LOAD9]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP8]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI3]], <4 x i64> [[WIDE_LOAD10]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP9:%.*]] = icmp sge <4 x i64> [[WIDE_LOAD]], [[VEC_PHI]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP10:%.*]] = icmp sge <4 x i64> [[WIDE_LOAD8]], [[VEC_PHI1]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP11:%.*]] = icmp sge <4 x i64> [[WIDE_LOAD9]], [[VEC_PHI2]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP12:%.*]] = icmp sge <4 x i64> [[WIDE_LOAD10]], [[VEC_PHI3]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI4]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI5]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI6]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI7]] | |
| ; CHECK-VF4UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[STEP_ADD_3]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] | |
| ; CHECK-VF4UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP5]], <4 x i64> [[TMP6]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP7]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX11]], <4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX12]]) | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT13:%.*]] = insertelement <4 x i64> poison, i64 [[TMP18]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT14:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT13]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: [[TMP19:%.*]] = icmp eq <4 x i64> [[TMP5]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP20:%.*]] = icmp eq <4 x i64> [[TMP6]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP21:%.*]] = icmp eq <4 x i64> [[TMP7]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP22:%.*]] = icmp eq <4 x i64> [[TMP8]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP23:%.*]] = select <4 x i1> [[TMP19]], <4 x i64> [[TMP13]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP20]], <4 x i64> [[TMP14]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP21]], <4 x i64> [[TMP15]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[TMP26:%.*]] = select <4 x i1> [[TMP22]], <4 x i64> [[TMP16]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX15:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP23]], <4 x i64> [[TMP24]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX16:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX15]], <4 x i64> [[TMP25]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX17:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX16]], <4 x i64> [[TMP26]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP27:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX17]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP27]], -9223372036854775808 | |
| ; CHECK-VF4UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP27]], i64 [[II]] | |
| ; CHECK-VF4UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP18]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX18:%.*]] = phi i64 [ [[TMP29]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF4: [[LOOP]]: | |
| ; CHECK-VF4UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP31:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX18]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP30:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP31]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP30]]) | |
| ; CHECK-VF4UF4-NEXT: [[CMP1:%.*]] = icmp sge i64 [[TMP30]], [[MAX]] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF4UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] | |
| ; CHECK-VF4UF4: [[EXIT]]: | |
| ; CHECK-VF4UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP31]], %[[LOOP]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP29]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF1UF4-LABEL: define i64 @smax_idx_inverted_pred( | |
| ; CHECK-VF1UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF1UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI4:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI5:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI6:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI7:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1UF4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP12]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI]], i64 [[TMP8]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI1]], i64 [[TMP9]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP14]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI2]], i64 [[TMP10]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP15]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI3]], i64 [[TMP11]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP16:%.*]] = icmp sge i64 [[TMP8]], [[VEC_PHI]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP17:%.*]] = icmp sge i64 [[TMP9]], [[VEC_PHI1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP18:%.*]] = icmp sge i64 [[TMP10]], [[VEC_PHI2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP19:%.*]] = icmp sge i64 [[TMP11]], [[VEC_PHI3]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP20]] = select i1 [[TMP16]], i64 [[INDEX]], i64 [[VEC_PHI4]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP21]] = select i1 [[TMP17]], i64 [[TMP1]], i64 [[VEC_PHI5]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP22]] = select i1 [[TMP18]], i64 [[TMP2]], i64 [[VEC_PHI6]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP23]] = select i1 [[TMP19]], i64 [[TMP3]], i64 [[VEC_PHI7]] | |
| ; CHECK-VF1UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] | |
| ; CHECK-VF1UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP12]], i64 [[TMP13]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX8:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP14]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX9:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX8]], i64 [[TMP15]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[TMP12]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP13]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP27:%.*]] = icmp eq i64 [[TMP14]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP15]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i64 [[TMP20]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP30:%.*]] = select i1 [[TMP26]], i64 [[TMP21]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP31:%.*]] = select i1 [[TMP27]], i64 [[TMP22]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP32:%.*]] = select i1 [[TMP28]], i64 [[TMP23]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX10:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP29]], i64 [[TMP30]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX11:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX10]], i64 [[TMP31]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX12:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX11]], i64 [[TMP32]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP33:%.*]] = icmp ne i64 [[RDX_MINMAX12]], -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i64 [[RDX_MINMAX12]], i64 [[II]] | |
| ; CHECK-VF1UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX13:%.*]] = phi i64 [ [[TMP34]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1UF4: [[LOOP]]: | |
| ; CHECK-VF1UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP36:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX13]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP35:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP36]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP35]]) | |
| ; CHECK-VF1UF4-NEXT: [[CMP1:%.*]] = icmp sge i64 [[TMP35]], [[MAX]] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-VF1UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] | |
| ; CHECK-VF1UF4: [[EXIT]]: | |
| ; CHECK-VF1UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP36]], %[[LOOP]] ], [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP34]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF1UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %1, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %1 = tail call i64 @llvm.smax.i64(i64 %max, i64 %0) | |
| %cmp1 = icmp sge i64 %0, %max | |
| %spec.select7 = select i1 %cmp1, i64 %iv, i64 %max.idx | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| store i64 %1, ptr %res_max | |
| ret i64 %spec.select7 | |
| } | |
| ; | |
| ; In such cases, the last index should be extracted. | |
| ; | |
| define i64 @smax_idx_extract_last(ptr nocapture readonly %a, i64 %mm, i64 %ii, ptr nocapture writeonly %res_max, i64 %n) { | |
| ; CHECK-VF4UF1-LABEL: define i64 @smax_idx_extract_last( | |
| ; CHECK-VF4UF1-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4UF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4UF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP2]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_PHI1]], <4 x i64> [[VEC_IND]] | |
| ; CHECK-VF4UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4UF1-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] | |
| ; CHECK-VF4UF1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP2]]) | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i64> poison, i64 [[TMP6]], i64 0 | |
| ; CHECK-VF4UF1-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT2]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF1-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[TMP2]], [[BROADCAST_SPLAT3]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP4]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF1-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF1-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP9]], -9223372036854775808 | |
| ; CHECK-VF4UF1-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 [[II]] | |
| ; CHECK-VF4UF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF1: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: [[BC_MERGE_RDX4:%.*]] = phi i64 [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF1: [[LOOP]]: | |
| ; CHECK-VF4UF1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP13:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX4]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF1-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP12]]) | |
| ; CHECK-VF4UF1-NEXT: [[CMP1_NOT:%.*]] = icmp sgt i64 [[MAX]], [[TMP12]] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1_NOT]], i64 [[MAX_IDX]], i64 [[IV]] | |
| ; CHECK-VF4UF1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF1-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF1-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] | |
| ; CHECK-VF4UF1: [[EXIT]]: | |
| ; CHECK-VF4UF1-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP13]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF1-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF1-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF4UF4-LABEL: define i64 @smax_idx_extract_last( | |
| ; CHECK-VF4UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[MM]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i64> [[STEP_ADD]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i64> [[STEP_ADD_2]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP2]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i64>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i64>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP5]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI]], <4 x i64> [[WIDE_LOAD]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP6]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI1]], <4 x i64> [[WIDE_LOAD8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP7]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI2]], <4 x i64> [[WIDE_LOAD9]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP8]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[VEC_PHI3]], <4 x i64> [[WIDE_LOAD10]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP9:%.*]] = icmp sgt <4 x i64> [[VEC_PHI]], [[WIDE_LOAD]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP10:%.*]] = icmp sgt <4 x i64> [[VEC_PHI1]], [[WIDE_LOAD8]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i64> [[VEC_PHI2]], [[WIDE_LOAD9]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP12:%.*]] = icmp sgt <4 x i64> [[VEC_PHI3]], [[WIDE_LOAD10]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[VEC_PHI4]], <4 x i64> [[VEC_IND]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i64> [[VEC_PHI5]], <4 x i64> [[STEP_ADD]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[VEC_PHI6]], <4 x i64> [[STEP_ADD_2]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[VEC_PHI7]], <4 x i64> [[STEP_ADD_3]] | |
| ; CHECK-VF4UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4UF4-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[STEP_ADD_3]], splat (i64 4) | |
| ; CHECK-VF4UF4-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] | |
| ; CHECK-VF4UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP5]], <4 x i64> [[TMP6]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP7]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX11]], <4 x i64> [[TMP8]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP18:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX12]]) | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLATINSERT13:%.*]] = insertelement <4 x i64> poison, i64 [[TMP18]], i64 0 | |
| ; CHECK-VF4UF4-NEXT: [[BROADCAST_SPLAT14:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT13]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4UF4-NEXT: [[TMP19:%.*]] = icmp eq <4 x i64> [[TMP5]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP20:%.*]] = icmp eq <4 x i64> [[TMP6]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP21:%.*]] = icmp eq <4 x i64> [[TMP7]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP22:%.*]] = icmp eq <4 x i64> [[TMP8]], [[BROADCAST_SPLAT14]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP23:%.*]] = select <4 x i1> [[TMP19]], <4 x i64> [[TMP13]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[TMP24:%.*]] = select <4 x i1> [[TMP20]], <4 x i64> [[TMP14]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP21]], <4 x i64> [[TMP15]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[TMP26:%.*]] = select <4 x i1> [[TMP22]], <4 x i64> [[TMP16]], <4 x i64> splat (i64 -9223372036854775808) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX15:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP23]], <4 x i64> [[TMP24]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX16:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX15]], <4 x i64> [[TMP25]]) | |
| ; CHECK-VF4UF4-NEXT: [[RDX_MINMAX17:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX16]], <4 x i64> [[TMP26]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP27:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX17]]) | |
| ; CHECK-VF4UF4-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP27]], -9223372036854775808 | |
| ; CHECK-VF4UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP27]], i64 [[II]] | |
| ; CHECK-VF4UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF4UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP18]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: [[BC_MERGE_RDX18:%.*]] = phi i64 [ [[TMP29]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF4UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4UF4: [[LOOP]]: | |
| ; CHECK-VF4UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP31:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX18]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4UF4-NEXT: [[TMP30:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4UF4-NEXT: [[TMP31]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP30]]) | |
| ; CHECK-VF4UF4-NEXT: [[CMP1_NOT:%.*]] = icmp sgt i64 [[MAX]], [[TMP30]] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1_NOT]], i64 [[MAX_IDX]], i64 [[IV]] | |
| ; CHECK-VF4UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] | |
| ; CHECK-VF4UF4: [[EXIT]]: | |
| ; CHECK-VF4UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP31]], %[[LOOP]] ], [ [[TMP18]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP29]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF4UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| ; CHECK-VF1UF4-LABEL: define i64 @smax_idx_extract_last( | |
| ; CHECK-VF1UF4-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1UF4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1UF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1UF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF1UF4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1UF4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1UF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ [[MM]], %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI4:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI5:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI6:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[VEC_PHI7:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1UF4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1UF4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP12]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI]], i64 [[TMP8]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP13]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI1]], i64 [[TMP9]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP14]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI2]], i64 [[TMP10]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP15]] = tail call i64 @llvm.smax.i64(i64 [[VEC_PHI3]], i64 [[TMP11]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP16:%.*]] = icmp sgt i64 [[VEC_PHI]], [[TMP8]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP17:%.*]] = icmp sgt i64 [[VEC_PHI1]], [[TMP9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[VEC_PHI2]], [[TMP10]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP19:%.*]] = icmp sgt i64 [[VEC_PHI3]], [[TMP11]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP20]] = select i1 [[TMP16]], i64 [[VEC_PHI4]], i64 [[INDEX]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP21]] = select i1 [[TMP17]], i64 [[VEC_PHI5]], i64 [[TMP1]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP22]] = select i1 [[TMP18]], i64 [[VEC_PHI6]], i64 [[TMP2]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP23]] = select i1 [[TMP19]], i64 [[VEC_PHI7]], i64 [[TMP3]] | |
| ; CHECK-VF1UF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[TMP24]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] | |
| ; CHECK-VF1UF4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP12]], i64 [[TMP13]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX8:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP14]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX9:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX8]], i64 [[TMP15]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[TMP12]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP13]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP27:%.*]] = icmp eq i64 [[TMP14]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[TMP15]], [[RDX_MINMAX9]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP29:%.*]] = select i1 [[TMP25]], i64 [[TMP20]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP30:%.*]] = select i1 [[TMP26]], i64 [[TMP21]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP31:%.*]] = select i1 [[TMP27]], i64 [[TMP22]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP32:%.*]] = select i1 [[TMP28]], i64 [[TMP23]], i64 -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX10:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP29]], i64 [[TMP30]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX11:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX10]], i64 [[TMP31]]) | |
| ; CHECK-VF1UF4-NEXT: [[RDX_MINMAX12:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX11]], i64 [[TMP32]]) | |
| ; CHECK-VF1UF4-NEXT: [[TMP33:%.*]] = icmp ne i64 [[RDX_MINMAX12]], -9223372036854775808 | |
| ; CHECK-VF1UF4-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i64 [[RDX_MINMAX12]], i64 [[II]] | |
| ; CHECK-VF1UF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1UF4: [[SCALAR_PH]]: | |
| ; CHECK-VF1UF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ], [ [[MM]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: [[BC_MERGE_RDX13:%.*]] = phi i64 [ [[TMP34]], %[[MIDDLE_BLOCK]] ], [ [[II]], %[[ENTRY]] ] | |
| ; CHECK-VF1UF4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1UF4: [[LOOP]]: | |
| ; CHECK-VF1UF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[TMP36:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[BC_MERGE_RDX13]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1UF4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1UF4-NEXT: [[TMP35:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF1UF4-NEXT: [[TMP36]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP35]]) | |
| ; CHECK-VF1UF4-NEXT: [[CMP1_NOT:%.*]] = icmp sgt i64 [[MAX]], [[TMP35]] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1_NOT]], i64 [[MAX_IDX]], i64 [[IV]] | |
| ; CHECK-VF1UF4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1UF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF1UF4-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] | |
| ; CHECK-VF1UF4: [[EXIT]]: | |
| ; CHECK-VF1UF4-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP36]], %[[LOOP]] ], [ [[RDX_MINMAX9]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ], [ [[TMP34]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1UF4-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-VF1UF4-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %1, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %1 = tail call i64 @llvm.smax.i64(i64 %max, i64 %0) | |
| %cmp1.not = icmp sgt i64 %max, %0 | |
| %spec.select7 = select i1 %cmp1.not, i64 %max.idx, i64 %iv | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| store i64 %1, ptr %res_max | |
| ret i64 %spec.select7 | |
| } | |
| ; | |
| ; The operands of smax intrinsic and icmp are not the same to be recognized as MMI. | |
| ; | |
| define i64 @smax_idx_not_vec_1(ptr nocapture readonly %a, ptr nocapture readonly %b, i64 %mm, i64 %ii, ptr nocapture writeonly %res_max, i64 %n) { | |
| ; CHECK-LABEL: define i64 @smax_idx_not_vec_1( | |
| ; CHECK-SAME: ptr readonly captures(none) [[A:%.*]], ptr readonly captures(none) [[B:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK: [[LOOP]]: | |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[MAX:%.*]] = phi i64 [ [[MM]], %[[ENTRY]] ], [ [[TMP2:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[II]], %[[ENTRY]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-NEXT: [[GEP_A_01:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-NEXT: [[TMP2]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP0]]) | |
| ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP1]] | |
| ; CHECK-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 [[IV]], i64 [[MAX_IDX]] | |
| ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP2]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ] | |
| ; CHECK-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %2, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %gep.a.01 = getelementptr inbounds i64, ptr %b, i64 %iv | |
| %1 = load i64, ptr %gep.a | |
| %2 = tail call i64 @llvm.smax.i64(i64 %max, i64 %0) | |
| %cmp1 = icmp slt i64 %max, %1 | |
| %spec.select7 = select i1 %cmp1, i64 %iv, i64 %max.idx | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| store i64 %2, ptr %res_max | |
| ret i64 %spec.select7 | |
| } | |
| ; | |
| ; It cannot be recognized as MMI when the operand of index select is not an induction variable. | |
| ; | |
| define i64 @smax_idx_not_vec_2(ptr nocapture readonly %a, i64 %mm, i64 %ii, ptr nocapture writeonly %res_max, i64 %n) { | |
| ; CHECK-LABEL: define i64 @smax_idx_not_vec_2( | |
| ; CHECK-SAME: ptr readonly captures(none) [[A:%.*]], i64 [[MM:%.*]], i64 [[II:%.*]], ptr writeonly captures(none) [[RES_MAX:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK: [[LOOP]]: | |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[MAX:%.*]] = phi i64 [ [[MM]], %[[ENTRY]] ], [ [[TMP1:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[MAX_IDX:%.*]] = phi i64 [ [[II]], %[[ENTRY]] ], [ [[SPEC_SELECT7:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[GEP_A]], align 4 | |
| ; CHECK-NEXT: [[TMP1]] = tail call i64 @llvm.smax.i64(i64 [[MAX]], i64 [[TMP0]]) | |
| ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i64 [[MAX]], [[TMP0]] | |
| ; CHECK-NEXT: [[SPEC_SELECT7]] = select i1 [[CMP1]], i64 123, i64 [[MAX_IDX]] | |
| ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi i64 [ [[TMP1]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[SPEC_SELECT7_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT7]], %[[LOOP]] ] | |
| ; CHECK-NEXT: store i64 [[DOTLCSSA]], ptr [[RES_MAX]], align 4 | |
| ; CHECK-NEXT: ret i64 [[SPEC_SELECT7_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %max = phi i64 [ %mm, %entry ], [ %1, %loop ] | |
| %max.idx = phi i64 [ %ii, %entry ], [ %spec.select7, %loop ] | |
| %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %gep.a | |
| %1 = tail call i64 @llvm.smax.i64(i64 %max, i64 %0) | |
| %cmp1 = icmp slt i64 %max, %0 | |
| %spec.select7 = select i1 %cmp1, i64 123, i64 %max.idx | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop | |
| exit: | |
| store i64 %1, ptr %res_max | |
| ret i64 %spec.select7 | |
| } | |