| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph:" --version 6 | |
| ; RUN: opt -p loop-vectorize -force-vector-width=2 -force-target-supports-masked-memory-ops -S %s | FileCheck %s | |
| ; %a is known dereferenceable via assume for the whole loop. | |
| define void @deref_assumption_in_preheader_non_constant_trip_count_access_i8(ptr noalias noundef %a, ptr noalias %b, ptr noalias %c, i64 %n) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_non_constant_trip_count_access_i8( | |
| ; CHECK-SAME: ptr noalias noundef [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 [[N]]) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i8> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i8>, ptr [[TMP1]], align 1 | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i8> [[WIDE_LOAD]], <2 x i8> [[WIDE_LOAD1]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i8> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 %n) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i8, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i8, ptr %b, i64 %iv | |
| %l.b = load i8, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i8 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i8, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i8 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i8, ptr %c, i64 %iv | |
| store i8 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| ; Adding an extra dereferenceable assume with constant size should not | |
| ; interfere. | |
| define void @deref_assumption_in_preheader_non_constant_trip_count_access_i8_extra_constant_assume(ptr noalias noundef %a, ptr noalias %b, ptr noalias %c, i64 %n) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_non_constant_trip_count_access_i8_extra_constant_assume( | |
| ; CHECK-SAME: ptr noalias noundef [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 100) ] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 [[N]]) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i8> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i8>, ptr [[TMP1]], align 1 | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i8> [[WIDE_LOAD]], <2 x i8> [[WIDE_LOAD1]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i8> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 100) ] | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 %n) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i8, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i8, ptr %b, i64 %iv | |
| %l.b = load i8, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i8 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i8, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i8 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i8, ptr %c, i64 %iv | |
| store i8 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| define void @deref_assumption_in_preheader_non_constant_trip_count_access_i8_extra_variable_assume(ptr noalias noundef %a, ptr noalias %b, ptr noalias %c, i64 %n, i64 %m) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_non_constant_trip_count_access_i8_extra_variable_assume( | |
| ; CHECK-SAME: ptr noalias noundef [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]], i64 [[M:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 [[M]]) ] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 [[N]]) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP2]], align 1 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i8> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i8>, ptr [[TMP1]], align 1 | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i8> [[WIDE_LOAD]], <2 x i8> [[WIDE_LOAD1]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i8> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 %m) ] | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 %n) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i8, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i8, ptr %b, i64 %iv | |
| %l.b = load i8, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i8 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i8, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i8 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i8, ptr %c, i64 %iv | |
| store i8 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| ; %a is known dereferenceable via assume for the whole loop. | |
| define void @deref_assumption_in_preheader_non_constant_trip_count_access_i32(ptr noalias noundef %a, ptr noalias %b, ptr noalias %c, i64 %n) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_non_constant_trip_count_access_i32( | |
| ; CHECK-SAME: ptr noalias noundef [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[N]], 4 | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 [[MUL]]) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP2]], align 1 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i32>, ptr [[TMP1]], align 1 | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[WIDE_LOAD]], <2 x i32> [[WIDE_LOAD1]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| %mul = mul nsw nuw i64 %n, 4 | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 %mul) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %l.b = load i32, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i32 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i32, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i32 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i32, ptr %c, i64 %iv | |
| store i32 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| ; %a is NOT known dereferenceable via assume for the whole loop. | |
| define void @deref_assumption_in_preheader_too_small_non_constant_trip_count_access_i32(ptr noalias noundef %a, ptr noalias %b, ptr noalias %c, i64 %n) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_too_small_non_constant_trip_count_access_i32( | |
| ; CHECK-SAME: ptr noalias noundef [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 [[N]]) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP2]], align 1 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 1 [[TMP1]], <2 x i1> [[TMP3]], <2 x i32> poison) | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[WIDE_MASKED_LOAD]], <2 x i32> [[WIDE_LOAD]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 %n) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %l.b = load i32, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i32 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i32, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i32 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i32, ptr %c, i64 %iv | |
| store i32 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| ; %a is NOT known dereferenceable via assume for the whole loop. | |
| define void @deref_assumption_in_preheader_too_small2_non_constant_trip_count_access_i32(ptr noalias noundef %a, ptr noalias %b, ptr noalias %c, i64 %n) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_too_small2_non_constant_trip_count_access_i32( | |
| ; CHECK-SAME: ptr noalias noundef [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 4), "dereferenceable"(ptr [[A]], i64 100) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP2]], align 1 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 1 [[TMP1]], <2 x i1> [[TMP3]], <2 x i32> poison) | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[WIDE_MASKED_LOAD]], <2 x i32> [[WIDE_LOAD]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| call void @llvm.assume(i1 true) [ "align"(ptr %a, i64 4), "dereferenceable"(ptr %a, i64 100) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %l.b = load i32, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i32 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i32, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i32 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i32, ptr %c, i64 %iv | |
| store i32 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| ; %a is known dereferenceable via assume for the whole loop, alignment is known via function attribute. | |
| define void @deref_assumption_in_preheader_non_constant_trip_count_access_i32_align_attribute(ptr noalias noundef align 4 %a, ptr noalias %b, ptr noalias %c, i64 %n) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_non_constant_trip_count_access_i32_align_attribute( | |
| ; CHECK-SAME: ptr noalias noundef align 4 [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[N]], 4 | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[A]], i64 [[MUL]]) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP2]], align 4 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp sge <2 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4 | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[WIDE_LOAD]], <2 x i32> [[WIDE_LOAD1]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| %mul = mul nsw nuw i64 %n, 4 | |
| call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %a, i64 %mul) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %l.b = load i32, ptr %gep.b, align 4 | |
| %c.1 = icmp sge i32 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i32, ptr %gep.a, align 4 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i32 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i32, ptr %c, i64 %iv | |
| store i32 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| ; Alignment via argument attribute is too small (1 but needs 4). | |
| define void @deref_assumption_in_preheader_non_constant_trip_count_access_i32_align_attribute_too_small(ptr noalias noundef align 1 %a, ptr noalias %b, ptr noalias %c, i64 %n) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_in_preheader_non_constant_trip_count_access_i32_align_attribute_too_small( | |
| ; CHECK-SAME: ptr noalias noundef align 1 [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[N]], 4 | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[A]], i64 [[MUL]]) ] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[N]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP2]], align 4 | |
| ; CHECK-NEXT: [[TMP3:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 4 [[TMP1]], <2 x i1> [[TMP3]], <2 x i32> poison) | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[WIDE_MASKED_LOAD]], <2 x i32> [[WIDE_LOAD]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]] | |
| ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP4]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| %mul = mul nsw nuw i64 %n, 4 | |
| call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %a, i64 %mul) ] | |
| br label %loop.header | |
| loop.header: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %l.b = load i32, ptr %gep.b, align 4 | |
| %c.1 = icmp sge i32 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i32, ptr %gep.a, align 4 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i32 [ %l.a, %loop.then ], [ %l.b, %loop.header ] | |
| %gep.c = getelementptr inbounds i32, ptr %c, i64 %iv | |
| store i32 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %ec = icmp eq i64 %iv.next, %n | |
| br i1 %ec, label %exit, label %loop.header | |
| exit: | |
| ret void | |
| } | |
| ; The start access is SCEV with non-constant offset because of variable `iv.start` | |
| ; for IV. | |
| define void @deref_assumption_loop_access_start_variable(i8 %v, ptr noundef %P, i64 range(i64 0, 2000) %N, ptr noalias %b, ptr noalias %c, i64 range(i64 0, 2000) %iv.start) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_loop_access_start_variable( | |
| ; CHECK-SAME: i8 [[V:%.*]], ptr noundef [[P:%.*]], i64 range(i64 0, 2000) [[N:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 range(i64 0, 2000) [[IV_START:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: [[A:%.*]] = getelementptr i8, ptr [[P]], i64 16 | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[IV_START]], [[N]] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[N]], 4 | |
| ; CHECK-NEXT: [[ADD:%.*]] = add i64 [[MUL]], 16 | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[P]], i64 [[ADD]]) ] | |
| ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[N]], [[IV_START]] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[IV_START]], [[N_VEC]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[IV_START]], [[INDEX]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP3]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP5]], align 1 | |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 1 [[TMP4]], <2 x i1> [[TMP6]], <2 x i32> poison) | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> [[WIDE_MASKED_LOAD]], <2 x i32> [[WIDE_LOAD]] | |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[TMP3]] | |
| ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP7]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| %a = getelementptr i8, ptr %P, i64 16 | |
| %cmp = icmp slt i64 %iv.start, %N | |
| call void @llvm.assume(i1 %cmp) | |
| %mul = mul i64 %N, 4 | |
| %add = add i64 %mul, 16 | |
| call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %P, i64 %add) ] | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ %iv.next, %loop.latch ], [ %iv.start, %entry ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %l.b = load i32, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i32 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i32, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i32 [ %l.a, %loop.then ], [ %l.b, %loop ] | |
| %gep.c = getelementptr inbounds i32, ptr %c, i64 %iv | |
| store i32 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %term.cond = icmp slt i64 %iv.next, %N | |
| br i1 %term.cond, label %loop, label %exit | |
| exit: | |
| ret void | |
| } | |
| ; Same as previous test, but `iv.start` is not known nonnegative. | |
| define void @deref_assumption_loop_access_start_variable_unknown_range(i8 %v, ptr noundef %P, i64 range(i64 0, 2000) %N, ptr noalias %b, ptr noalias %c, i64 %iv.start) nofree nosync { | |
| ; CHECK-LABEL: define void @deref_assumption_loop_access_start_variable_unknown_range( | |
| ; CHECK-SAME: i8 [[V:%.*]], ptr noundef [[P:%.*]], i64 range(i64 0, 2000) [[N:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[IV_START:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-NEXT: [[A:%.*]] = getelementptr i8, ptr [[P]], i64 16 | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[IV_START]], [[N]] | |
| ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) | |
| ; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[N]], 4 | |
| ; CHECK-NEXT: [[ADD:%.*]] = add i64 [[MUL]], 16 | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[P]], i64 [[ADD]]) ] | |
| ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[N]], [[IV_START]] | |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 | |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK: [[VECTOR_PH]]: | |
| ; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1 | |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]] | |
| ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[IV_START]], [[N_VEC]] | |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK: [[VECTOR_BODY]]: | |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-NEXT: [[TMP3:%.*]] = add nuw i64 [[IV_START]], [[INDEX]] | |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP3]] | |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP5]], align 1 | |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp slt <2 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 1 [[TMP4]], <2 x i1> [[TMP6]], <2 x i32> poison) | |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> [[WIDE_MASKED_LOAD]], <2 x i32> [[WIDE_LOAD]] | |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[TMP3]] | |
| ; CHECK-NEXT: store <2 x i32> [[PREDPHI]], ptr [[TMP7]], align 1 | |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 | |
| ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] | |
| ; CHECK: [[MIDDLE_BLOCK]]: | |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] | |
| ; CHECK-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] | |
| ; CHECK: [[SCALAR_PH]]: | |
| ; | |
| entry: | |
| %a = getelementptr i8, ptr %P, i64 16 | |
| %cmp = icmp slt i64 %iv.start, %N | |
| call void @llvm.assume(i1 %cmp) | |
| %mul = mul i64 %N, 4 | |
| %add = add i64 %mul, 16 | |
| call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %P, i64 %add) ] | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ %iv.next, %loop.latch ], [ %iv.start, %entry ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %gep.b = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %l.b = load i32, ptr %gep.b, align 1 | |
| %c.1 = icmp sge i32 %l.b, 0 | |
| br i1 %c.1, label %loop.latch, label %loop.then | |
| loop.then: | |
| %l.a = load i32, ptr %gep.a, align 1 | |
| br label %loop.latch | |
| loop.latch: | |
| %merge = phi i32 [ %l.a, %loop.then ], [ %l.b, %loop ] | |
| %gep.c = getelementptr inbounds i32, ptr %c, i64 %iv | |
| store i32 %merge, ptr %gep.c, align 1 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %term.cond = icmp slt i64 %iv.next, %N | |
| br i1 %term.cond, label %loop, label %exit | |
| exit: | |
| ret void | |
| } | |
| ; Test to check type mismatch while calling getUMaxExpr() | |
| define void @test_assumed_bounds_type_mismatch(ptr noalias %array, ptr readonly %pred, i32 %n) nosync nofree { | |
| ; CHECK-LABEL: define void @test_assumed_bounds_type_mismatch( | |
| ; CHECK-SAME: ptr noalias [[ARRAY:%.*]], ptr readonly [[PRED:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { | |
| ; CHECK-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-NEXT: [[N_BYTES:%.*]] = mul nuw nsw i32 [[N]], 2 | |
| ; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[PRED]], i32 [[N_BYTES]]) ] | |
| ; CHECK-NEXT: [[TC:%.*]] = sext i32 [[N]] to i64 | |
| ; CHECK-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK: [[FOR_BODY]]: | |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_INC:.*]] ] | |
| ; CHECK-NEXT: [[ST_ADDR:%.*]] = getelementptr inbounds i16, ptr [[ARRAY]], i64 [[IV]] | |
| ; CHECK-NEXT: [[DATA:%.*]] = load i16, ptr [[ST_ADDR]], align 2 | |
| ; CHECK-NEXT: [[INC:%.*]] = add nsw i16 [[DATA]], 1 | |
| ; CHECK-NEXT: store i16 [[INC]], ptr [[ST_ADDR]], align 2 | |
| ; CHECK-NEXT: [[EE_ADDR:%.*]] = getelementptr inbounds i16, ptr [[PRED]], i64 [[IV]] | |
| ; CHECK-NEXT: [[EE_VAL:%.*]] = load i16, ptr [[EE_ADDR]], align 2 | |
| ; CHECK-NEXT: [[EE_COND:%.*]] = icmp sgt i16 [[EE_VAL]], 500 | |
| ; CHECK-NEXT: br i1 [[EE_COND]], label %[[EXIT:.*]], label %[[FOR_INC]] | |
| ; CHECK: [[FOR_INC]]: | |
| ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-NEXT: [[COUNTED_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[TC]] | |
| ; CHECK-NEXT: br i1 [[COUNTED_COND]], label %[[EXIT]], label %[[FOR_BODY]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: ret void | |
| ; | |
| entry: | |
| %n_bytes = mul nuw nsw i32 %n, 2 | |
| call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %pred, i32 %n_bytes) ] | |
| %tc = sext i32 %n to i64 | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.inc ] | |
| %st.addr = getelementptr inbounds i16, ptr %array, i64 %iv | |
| %data = load i16, ptr %st.addr, align 2 | |
| %inc = add nsw i16 %data, 1 | |
| store i16 %inc, ptr %st.addr, align 2 | |
| %ee.addr = getelementptr inbounds i16, ptr %pred, i64 %iv | |
| %ee.val = load i16, ptr %ee.addr, align 2 | |
| %ee.cond = icmp sgt i16 %ee.val, 500 | |
| br i1 %ee.cond, label %exit, label %for.inc | |
| for.inc: | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %counted.cond = icmp eq i64 %iv.next, %tc | |
| br i1 %counted.cond, label %exit, label %for.body | |
| exit: | |
| ret void | |
| } |