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llvm/llvm-project/f3d4f2aa601703166e75ec00a67624b073a613f2/./llvm/test/Transforms/LoopVectorize/VPlan/vplan-iv-transforms.ll
blob: a47b56d9aa85a8ec2232ff856d775578bea913b0 [file]
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=8 -disable-output -vplan-print-after=printOptimizedVPlan %s 2>&1 | FileCheck %s
define void @iv_no_binary_op_in_descriptor(i1 %c, ptr %dst) {
; CHECK-LABEL: VPlan for loop in 'iv_no_binary_op_in_descriptor'
; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
; CHECK-NEXT: Live-in ir<1000> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
; CHECK-NEXT: Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT: <x1> vector loop: {
; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%dst>, vp<[[VP4]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds i64, ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN store vp<[[VP5]]>, ir<%iv>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<exit>:
; CHECK-NEXT: No successors
; CHECK-EMPTY:
; CHECK-NEXT: scalar.ph:
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
; CHECK-NEXT: Successor(s): ir-bb<loop.header>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop.header>:
; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next.p, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK-NEXT: IR %gep = getelementptr inbounds i64, ptr %dst, i64 %iv
; CHECK-NEXT: IR store i64 %iv, ptr %gep, align 8
; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %loop.header
loop.header:
%iv = phi i64 [ 0, %entry ], [ %iv.next.p, %loop.latch ]
%gep = getelementptr inbounds i64, ptr %dst, i64 %iv
store i64 %iv, ptr %gep, align 8
%iv.next = add i64 %iv, 1
br label %loop.latch
loop.latch:
%iv.next.p = phi i64 [ %iv.next, %loop.header ]
%exitcond.not = icmp eq i64 %iv.next.p, 1000
br i1 %exitcond.not, label %exit, label %loop.header
exit:
ret void
}
; Check that VPWidenIntOrFPInductionRecipe is expanded into smaller recipes in
; the final VPlan.
define void @iv_expand(ptr %p, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'iv_expand'
; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
; CHECK-NEXT: Live-in ir<%n> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
; CHECK-NEXT: Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT: <x1> vector loop: {
; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%q> = getelementptr ir<%p>, vp<[[VP4]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer i64, ir<%q>, ir<1>
; CHECK-NEXT: WIDEN ir<%x> = load vp<[[VP5]]>
; CHECK-NEXT: WIDEN ir<%y> = add ir<%x>, ir<%iv>
; CHECK-NEXT: WIDEN store vp<[[VP5]]>, ir<%y>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<exit>:
; CHECK-NEXT: No successors
; CHECK-EMPTY:
; CHECK-NEXT: scalar.ph:
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
; CHECK-NEXT: Successor(s): ir-bb<loop>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop>:
; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK-NEXT: IR %q = getelementptr i64, ptr %p, i64 %iv
; CHECK-NEXT: IR %x = load i64, ptr %q, align 4
; CHECK-NEXT: IR %y = add i64 %x, %iv
; CHECK-NEXT: IR store i64 %y, ptr %q, align 4
; CHECK-NEXT: IR %iv.next = add i64 %iv, 1
; CHECK-NEXT: IR %done = icmp eq i64 %iv.next, %n
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %loop
loop:
%iv = phi i64 [0, %entry], [%iv.next, %loop]
%q = getelementptr i64, ptr %p, i64 %iv
%x = load i64, ptr %q
%y = add i64 %x, %iv
store i64 %y, ptr %q
%iv.next = add i64 %iv, 1
%done = icmp eq i64 %iv.next, %n
br i1 %done, label %exit, label %loop
exit:
ret void
}
; FIXME: The nuw/nsw flags from the scalar IV are not valid for the truncated
; IV.
define void @iv_truncated_wrap_flags(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'iv_truncated_wrap_flags'
; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
; CHECK-NEXT: Live-in ir<%n> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
; CHECK-NEXT: Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT: <x1> vector loop: {
; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]> (truncated to i16)
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%ptr> = getelementptr inbounds ir<%dst>, vp<[[VP4]]>
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds i16, ir<%ptr>, ir<1>
; CHECK-NEXT: WIDEN store vp<[[VP5]]>, ir<%iv>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<exit>:
; CHECK-NEXT: No successors
; CHECK-EMPTY:
; CHECK-NEXT: scalar.ph:
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
; CHECK-NEXT: Successor(s): ir-bb<loop>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop>:
; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK-NEXT: IR %val = trunc i64 %iv to i16
; CHECK-NEXT: IR %ptr = getelementptr inbounds i16, ptr %dst, i64 %iv
; CHECK-NEXT: IR store i16 %val, ptr %ptr, align 2
; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1
; CHECK-NEXT: IR %exit.cond = icmp eq i64 %iv.next, %n
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%val = trunc i64 %iv to i16
%ptr = getelementptr inbounds i16, ptr %dst, i64 %iv
store i16 %val, ptr %ptr, align 2
%iv.next = add nuw nsw i64 %iv, 1
%exit.cond = icmp eq i64 %iv.next, %n
br i1 %exit.cond, label %exit, label %loop
exit:
ret void
}
define void @fp_iv_step_defined_outside_loop(ptr %a, float %x, float %y, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'fp_iv_step_defined_outside_loop'
; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
; CHECK-NEXT: Live-in ir<%n> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
; CHECK-NEXT: IR %step = fmul fast float %x, %y
; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = EXPAND SCEV %step
; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<0.000000e+00> + vp<[[VP2]]> * vp<[[VP3]]>
; CHECK-NEXT: Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT: <x1> vector loop: {
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = CANONICAL-IV
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%f> = WIDEN-INDUCTION fast ir<0.000000e+00>, vp<[[VP3]]>, vp<[[VP0]]>
; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = SCALAR-STEPS vp<[[VP5]]>, ir<1>, vp<[[VP0]]>
; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%a>, vp<[[VP6]]>
; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds float, ir<%gep>, ir<1>
; CHECK-NEXT: WIDEN store vp<[[VP7]]>, ir<%f>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<exit>:
; CHECK-NEXT: No successors
; CHECK-EMPTY:
; CHECK-NEXT: scalar.ph:
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val>.1 = phi [ vp<[[VP4]]>, middle.block ], [ ir<0.000000e+00>, ir-bb<entry> ]
; CHECK-NEXT: Successor(s): ir-bb<loop>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop>:
; CHECK-NEXT: IR %i = phi i64 [ 0, %entry ], [ %i.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK-NEXT: IR %f = phi float [ 0.000000e+00, %entry ], [ %f.next, %loop ] (extra operand: vp<%bc.resume.val>.1 from scalar.ph)
; CHECK-NEXT: IR %gep = getelementptr inbounds float, ptr %a, i64 %i
; CHECK-NEXT: IR store float %f, ptr %gep, align 4
; CHECK-NEXT: IR %f.next = fadd fast float %f, %step
; CHECK-NEXT: IR %i.next = add nuw nsw i64 %i, 1
; CHECK-NEXT: IR %ec = icmp eq i64 %i.next, %n
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
%step = fmul fast float %x, %y
br label %loop
loop:
%i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
%f = phi float [ 0.0, %entry ], [ %f.next, %loop ]
%gep = getelementptr inbounds float, ptr %a, i64 %i
store float %f, ptr %gep, align 4
%f.next = fadd fast float %f, %step
%i.next = add nuw nsw i64 %i, 1
%ec = icmp eq i64 %i.next, %n
br i1 %ec, label %exit, label %loop
exit:
ret void
}
; The latch value of the count-down induction %iv is a single-entry phi.
define i64 @early_exit_countdown_iv_via_latch_phi(i64 %n, i64 %mask) {
; CHECK-LABEL: VPlan for loop in 'early_exit_countdown_iv_via_latch_phi'
; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV ((-1 * (1 smin (-1 + %n)<nsw>)) + %n)
; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%n> + vp<[[VP2]]> * ir<-1>
; CHECK-NEXT: Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT: <x1> vector loop: {
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = CANONICAL-IV
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<%n>, ir<-1>, vp<[[VP0]]>
; CHECK-NEXT: WIDEN ir<%iv.next> = add nsw ir<%iv>, ir<-1>
; CHECK-NEXT: WIDEN ir<%hi> = shl nsw ir<-1>, ir<%iv.next>
; CHECK-NEXT: WIDEN ir<%or> = or ir<%hi>, ir<%mask>
; CHECK-NEXT: WIDEN ir<%c> = icmp eq ir<%or>, ir<-1>
; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = freeze ir<%c>
; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = any-of vp<[[VP6]]>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = icmp eq vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-two-conds vp<[[VP7]]>, vp<[[VP8]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-NEXT: Successor(s): vector.early.exit, middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.early.exit:
; CHECK-NEXT: EMIT vp<%first.active.lane> = first-active-lane vp<[[VP6]]>
; CHECK-NEXT: EMIT vp<%early.exit.value> = extract-lane vp<%first.active.lane>, ir<%iv.next>
; CHECK-NEXT: Successor(s): ir-bb<exit>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<exit>:
; CHECK-NEXT: IR %res = phi i64 [ %iv.next, %loop.header ], [ 0, %loop.latch ] (extra operands: ir<0> from middle.block, vp<%early.exit.value> from vector.early.exit)
; CHECK-NEXT: No successors
; CHECK-EMPTY:
; CHECK-NEXT: scalar.ph:
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%n>, ir-bb<entry> ]
; CHECK-NEXT: Successor(s): ir-bb<loop.header>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop.header>:
; CHECK-NEXT: IR %iv = phi i64 [ %n, %entry ], [ %iv.latch, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK-NEXT: IR %iv.next = add nsw i64 %iv, -1
; CHECK-NEXT: IR %hi = shl nsw i64 -1, %iv.next
; CHECK-NEXT: IR %or = or i64 %hi, %mask
; CHECK-NEXT: IR %c = icmp eq i64 %or, -1
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %loop.header
loop.header:
%iv = phi i64 [ %n, %entry ], [ %iv.latch, %loop.latch ]
%iv.next = add nsw i64 %iv, -1
%hi = shl nsw i64 -1, %iv.next
%or = or i64 %hi, %mask
%c = icmp eq i64 %or, -1
br i1 %c, label %exit, label %loop.latch
loop.latch:
%iv.latch = phi i64 [ %iv.next, %loop.header ]
%ec = icmp sgt i64 %iv.latch, 1
br i1 %ec, label %loop.header, label %exit
exit:
%res = phi i64 [ %iv.next, %loop.header ], [ 0, %loop.latch ]
ret i64 %res
}
; The latch values of both %cnt and %x are single-entry phis.
define i32 @early_exit_two_ivs_via_latch_phis(i32 %n, i32 %w, ptr %count.out) {
; CHECK-LABEL: VPlan for loop in 'early_exit_two_ivs_via_latch_phis'
; CHECK: VPlan 'Initial VPlan for VF={8},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
; CHECK-NEXT: Live-in ir<%n> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = DERIVED-IV ir<%n> + vp<[[VP2]]> * ir<-1>
; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP2]]> * ir<4>
; CHECK-NEXT: Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT: <x1> vector loop: {
; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = CANONICAL-IV
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: ir<%cnt> = WIDEN-INDUCTION nsw ir<%n>, ir<-1>, vp<[[VP0]]>
; CHECK-NEXT: ir<%x> = WIDEN-INDUCTION nsw ir<0>, ir<4>, vp<[[VP0]]>
; CHECK-NEXT: WIDEN ir<%x.next> = add nsw ir<%x>, ir<4>
; CHECK-NEXT: WIDEN ir<%c> = icmp sge ir<%x.next>, ir<%w>
; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = freeze ir<%c>
; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = any-of vp<[[VP6]]>
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]>
; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = icmp eq vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-two-conds vp<[[VP7]]>, vp<[[VP8]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-NEXT: Successor(s): vector.early.exit, middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.early.exit:
; CHECK-NEXT: WIDEN ir<%cnt.next> = add nsw ir<%cnt>, ir<-1>
; CHECK-NEXT: EMIT vp<%first.active.lane> = first-active-lane vp<[[VP6]]>
; CHECK-NEXT: EMIT vp<%early.exit.value> = extract-lane vp<%first.active.lane>, ir<%x.next>
; CHECK-NEXT: EMIT vp<%early.exit.value>.1 = extract-lane vp<%first.active.lane>, ir<%cnt.next>
; CHECK-NEXT: Successor(s): ir-bb<exit>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<exit>:
; CHECK-NEXT: IR %res.x = phi i32 [ %x.next, %loop.header ], [ %x.latch, %loop.latch ] (extra operands: vp<[[VP4]]> from middle.block, vp<%early.exit.value> from vector.early.exit)
; CHECK-NEXT: IR %res.cnt = phi i32 [ %cnt.next, %loop.header ], [ 0, %loop.latch ] (extra operands: ir<0> from middle.block, vp<%early.exit.value>.1 from vector.early.exit)
; CHECK-NEXT: IR store i32 %res.cnt, ptr %count.out, align 4
; CHECK-NEXT: No successors
; CHECK-EMPTY:
; CHECK-NEXT: scalar.ph:
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP3]]>, middle.block ], [ ir<%n>, ir-bb<entry> ]
; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val>.1 = phi [ vp<[[VP4]]>, middle.block ], [ ir<0>, ir-bb<entry> ]
; CHECK-NEXT: Successor(s): ir-bb<loop.header>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop.header>:
; CHECK-NEXT: IR %cnt = phi i32 [ %n, %entry ], [ %cnt.latch, %loop.latch ] (extra operand: vp<%bc.resume.val> from scalar.ph)
; CHECK-NEXT: IR %x = phi i32 [ 0, %entry ], [ %x.latch, %loop.latch ] (extra operand: vp<%bc.resume.val>.1 from scalar.ph)
; CHECK-NEXT: IR %x.next = add nsw i32 %x, 4
; CHECK-NEXT: IR %cnt.next = add nsw i32 %cnt, -1
; CHECK-NEXT: IR %c = icmp slt i32 %x.next, %w
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %loop.header
loop.header:
%cnt = phi i32 [ %n, %entry ], [ %cnt.latch, %loop.latch ]
%x = phi i32 [ 0, %entry ], [ %x.latch, %loop.latch ]
%x.next = add nsw i32 %x, 4
%cnt.next = add nsw i32 %cnt, -1
%c = icmp slt i32 %x.next, %w
br i1 %c, label %loop.latch, label %exit
loop.latch:
%x.latch = phi i32 [ %x.next, %loop.header ]
%cnt.latch = phi i32 [ %cnt.next, %loop.header ]
%ec = icmp eq i32 %cnt.latch, 0
br i1 %ec, label %exit, label %loop.header
exit:
%res.x = phi i32 [ %x.next, %loop.header ], [ %x.latch, %loop.latch ]
%res.cnt = phi i32 [ %cnt.next, %loop.header ], [ 0, %loop.latch ]
store i32 %res.cnt, ptr %count.out, align 4
ret i32 %res.x
}