llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -passes=loop-vectorize < %s -S -o - | FileCheck %s

target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"

define void @arm_abs_q7(ptr nocapture readonly %pSrc, ptr nocapture %pDst, i32 %blockSize) #0 {
; CHECK-LABEL: define void @arm_abs_q7(
; CHECK-SAME: ptr readonly captures(none) [[PSRC:%.*]], ptr captures(none) [[PDST:%.*]], i32 [[BLOCKSIZE:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[PSRC2:%.*]] = ptrtoaddr ptr [[PSRC]] to i32
; CHECK-NEXT:    [[PDST1:%.*]] = ptrtoaddr ptr [[PDST]] to i32
; CHECK-NEXT:    [[CMP_NOT19:%.*]] = icmp eq i32 [[BLOCKSIZE]], 0
; CHECK-NEXT:    br i1 [[CMP_NOT19]], label %[[WHILE_END:.*]], label %[[WHILE_BODY_PREHEADER:.*]]
; CHECK:       [[WHILE_BODY_PREHEADER]]:
; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 16
; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK:       [[VECTOR_MEMCHECK]]:
; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 [[PDST1]], [[PSRC2]]
; CHECK-NEXT:    [[TMP11:%.*]] = sub i32 [[TMP0]], 1
; CHECK-NEXT:    [[DIFF_CHECK:%.*]] = icmp ult i32 [[TMP11]], 15
; CHECK-NEXT:    br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[N_MOD_VF:%.*]] = and i32 [[BLOCKSIZE]], 15
; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[BLOCKSIZE]], [[N_MOD_VF]]
; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[N_VEC]]
; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 [[BLOCKSIZE]], [[N_VEC]]
; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[N_VEC]]
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[INDEX]]
; CHECK-NEXT:    [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[INDEX]]
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[NEXT_GEP]], align 1
; CHECK-NEXT:    [[TMP4:%.*]] = icmp sgt <16 x i8> [[WIDE_LOAD]], zeroinitializer
; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], splat (i8 -128)
; CHECK-NEXT:    [[TMP6:%.*]] = sub <16 x i8> zeroinitializer, [[WIDE_LOAD]]
; CHECK-NEXT:    [[TMP7:%.*]] = select <16 x i1> [[TMP5]], <16 x i8> splat (i8 127), <16 x i8> [[TMP6]]
; CHECK-NEXT:    [[TMP8:%.*]] = select <16 x i1> [[TMP4]], <16 x i8> [[WIDE_LOAD]], <16 x i8> [[TMP7]]
; CHECK-NEXT:    store <16 x i8> [[TMP8]], ptr [[NEXT_GEP3]], align 1
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
; CHECK-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[BLOCKSIZE]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[CMP_N]], label %[[WHILE_END_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; CHECK:       [[SCALAR_PH]]:
; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[PSRC]], %[[WHILE_BODY_PREHEADER]] ], [ [[PSRC]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[BLOCKSIZE]], %[[WHILE_BODY_PREHEADER]] ], [ [[BLOCKSIZE]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    [[BC_RESUME_VAL5:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[PDST]], %[[WHILE_BODY_PREHEADER]] ], [ [[PDST]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    br label %[[WHILE_BODY:.*]]
; CHECK:       [[WHILE_BODY]]:
; CHECK-NEXT:    [[PSRC_ADDR_022:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[BLKCNT_021:%.*]] = phi i32 [ [[DEC:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[PDST_ADDR_020:%.*]] = phi ptr [ [[INCDEC_PTR13:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL5]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[PSRC_ADDR_022]], i32 1
; CHECK-NEXT:    [[TMP10:%.*]] = load i8, ptr [[PSRC_ADDR_022]], align 1
; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i8 [[TMP10]], 0
; CHECK-NEXT:    [[CMP5:%.*]] = icmp eq i8 [[TMP10]], -128
; CHECK-NEXT:    [[SUB:%.*]] = sub i8 0, [[TMP10]]
; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP5]], i8 127, i8 [[SUB]]
; CHECK-NEXT:    [[COND11:%.*]] = select i1 [[CMP1]], i8 [[TMP10]], i8 [[COND]]
; CHECK-NEXT:    [[INCDEC_PTR13]] = getelementptr inbounds i8, ptr [[PDST_ADDR_020]], i32 1
; CHECK-NEXT:    store i8 [[COND11]], ptr [[PDST_ADDR_020]], align 1
; CHECK-NEXT:    [[DEC]] = add i32 [[BLKCNT_021]], -1
; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
; CHECK-NEXT:    br i1 [[CMP_NOT]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK:       [[WHILE_END_LOOPEXIT]]:
; CHECK-NEXT:    br label %[[WHILE_END]]
; CHECK:       [[WHILE_END]]:
; CHECK-NEXT:    ret void
;
entry:
  %cmp.not19 = icmp eq i32 %blockSize, 0
  br i1 %cmp.not19, label %while.end, label %while.body.preheader

while.body.preheader:
  br label %while.body

while.body:
  %pSrc.addr.022 = phi ptr [ %incdec.ptr, %while.body ], [ %pSrc, %while.body.preheader ]
  %blkCnt.021 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
  %pDst.addr.020 = phi ptr [ %incdec.ptr13, %while.body ], [ %pDst, %while.body.preheader ]
  %incdec.ptr = getelementptr inbounds i8, ptr %pSrc.addr.022, i32 1
  %0 = load i8, ptr %pSrc.addr.022, align 1
  %cmp1 = icmp sgt i8 %0, 0
  %cmp5 = icmp eq i8 %0, -128
  %sub = sub i8 0, %0
  %cond = select i1 %cmp5, i8 127, i8 %sub
  %cond11 = select i1 %cmp1, i8 %0, i8 %cond
  %incdec.ptr13 = getelementptr inbounds i8, ptr %pDst.addr.020, i32 1
  store i8 %cond11, ptr %pDst.addr.020, align 1
  %dec = add i32 %blkCnt.021, -1
  %cmp.not = icmp eq i32 %dec, 0
  br i1 %cmp.not, label %while.end.loopexit, label %while.body

while.end.loopexit:
  br label %while.end

while.end:
  ret void
}

define void @arm_abs_q15(ptr nocapture readonly %pSrc, ptr nocapture %pDst, i32 %blockSize) #0 {
; CHECK-LABEL: define void @arm_abs_q15(
; CHECK-SAME: ptr readonly captures(none) [[PSRC:%.*]], ptr captures(none) [[PDST:%.*]], i32 [[BLOCKSIZE:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[PSRC2:%.*]] = ptrtoaddr ptr [[PSRC]] to i32
; CHECK-NEXT:    [[PDST1:%.*]] = ptrtoaddr ptr [[PDST]] to i32
; CHECK-NEXT:    [[CMP_NOT20:%.*]] = icmp eq i32 [[BLOCKSIZE]], 0
; CHECK-NEXT:    br i1 [[CMP_NOT20]], label %[[WHILE_END:.*]], label %[[WHILE_BODY_PREHEADER:.*]]
; CHECK:       [[WHILE_BODY_PREHEADER]]:
; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 8
; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK:       [[VECTOR_MEMCHECK]]:
; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 [[PDST1]], [[PSRC2]]
; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 [[TMP0]], 1
; CHECK-NEXT:    [[DIFF_CHECK:%.*]] = icmp ult i32 [[TMP5]], 15
; CHECK-NEXT:    br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[N_MOD_VF:%.*]] = and i32 [[BLOCKSIZE]], 7
; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[BLOCKSIZE]], [[N_MOD_VF]]
; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[N_VEC]], 1
; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[TMP1]]
; CHECK-NEXT:    [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[N_VEC]]
; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[TMP1]]
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = shl i32 [[INDEX]], 1
; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[OFFSET_IDX]]
; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[OFFSET_IDX]]
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[NEXT_GEP]], align 2
; CHECK-NEXT:    [[TMP6:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD]], zeroinitializer
; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq <8 x i16> [[WIDE_LOAD]], splat (i16 -32768)
; CHECK-NEXT:    [[TMP8:%.*]] = sub <8 x i16> zeroinitializer, [[WIDE_LOAD]]
; CHECK-NEXT:    [[TMP9:%.*]] = select <8 x i1> [[TMP7]], <8 x i16> splat (i16 32767), <8 x i16> [[TMP8]]
; CHECK-NEXT:    [[TMP10:%.*]] = select <8 x i1> [[TMP6]], <8 x i16> [[WIDE_LOAD]], <8 x i16> [[TMP9]]
; CHECK-NEXT:    store <8 x i16> [[TMP10]], ptr [[NEXT_GEP4]], align 2
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[BLOCKSIZE]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[CMP_N]], label %[[WHILE_END_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; CHECK:       [[SCALAR_PH]]:
; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[PSRC]], %[[WHILE_BODY_PREHEADER]] ], [ [[PSRC]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[BLOCKSIZE]], %[[WHILE_BODY_PREHEADER]] ], [ [[BLOCKSIZE]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    [[BC_RESUME_VAL5:%.*]] = phi ptr [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[PDST]], %[[WHILE_BODY_PREHEADER]] ], [ [[PDST]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    br label %[[WHILE_BODY:.*]]
; CHECK:       [[WHILE_BODY]]:
; CHECK-NEXT:    [[PSRC_ADDR_023:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[BLKCNT_022:%.*]] = phi i32 [ [[DEC:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[PDST_ADDR_021:%.*]] = phi ptr [ [[INCDEC_PTR13:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL5]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[INCDEC_PTR]] = getelementptr inbounds i16, ptr [[PSRC_ADDR_023]], i32 1
; CHECK-NEXT:    [[TMP12:%.*]] = load i16, ptr [[PSRC_ADDR_023]], align 2
; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i16 [[TMP12]], 0
; CHECK-NEXT:    [[CMP5:%.*]] = icmp eq i16 [[TMP12]], -32768
; CHECK-NEXT:    [[SUB:%.*]] = sub i16 0, [[TMP12]]
; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP5]], i16 32767, i16 [[SUB]]
; CHECK-NEXT:    [[COND11:%.*]] = select i1 [[CMP1]], i16 [[TMP12]], i16 [[COND]]
; CHECK-NEXT:    [[INCDEC_PTR13]] = getelementptr inbounds i16, ptr [[PDST_ADDR_021]], i32 1
; CHECK-NEXT:    store i16 [[COND11]], ptr [[PDST_ADDR_021]], align 2
; CHECK-NEXT:    [[DEC]] = add i32 [[BLKCNT_022]], -1
; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
; CHECK-NEXT:    br i1 [[CMP_NOT]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK:       [[WHILE_END_LOOPEXIT]]:
; CHECK-NEXT:    br label %[[WHILE_END]]
; CHECK:       [[WHILE_END]]:
; CHECK-NEXT:    ret void
;
entry:
  %cmp.not20 = icmp eq i32 %blockSize, 0
  br i1 %cmp.not20, label %while.end, label %while.body.preheader

while.body.preheader:
  br label %while.body

while.body:
  %pSrc.addr.023 = phi ptr [ %incdec.ptr, %while.body ], [ %pSrc, %while.body.preheader ]
  %blkCnt.022 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
  %pDst.addr.021 = phi ptr [ %incdec.ptr13, %while.body ], [ %pDst, %while.body.preheader ]
  %incdec.ptr = getelementptr inbounds i16, ptr %pSrc.addr.023, i32 1
  %0 = load i16, ptr %pSrc.addr.023, align 2
  %cmp1 = icmp sgt i16 %0, 0
  %cmp5 = icmp eq i16 %0, -32768
  %sub = sub i16 0, %0
  %cond = select i1 %cmp5, i16 32767, i16 %sub
  %cond11 = select i1 %cmp1, i16 %0, i16 %cond
  %incdec.ptr13 = getelementptr inbounds i16, ptr %pDst.addr.021, i32 1
  store i16 %cond11, ptr %pDst.addr.021, align 2
  %dec = add i32 %blkCnt.022, -1
  %cmp.not = icmp eq i32 %dec, 0
  br i1 %cmp.not, label %while.end.loopexit, label %while.body

while.end.loopexit:
  br label %while.end

while.end:
  ret void
}

define void @arm_abs_q31(ptr nocapture readonly %pSrc, ptr nocapture %pDst, i32 %blockSize) #0 {
; CHECK-LABEL: define void @arm_abs_q31(
; CHECK-SAME: ptr readonly captures(none) [[PSRC:%.*]], ptr captures(none) [[PDST:%.*]], i32 [[BLOCKSIZE:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[PSRC2:%.*]] = ptrtoaddr ptr [[PSRC]] to i32
; CHECK-NEXT:    [[PDST1:%.*]] = ptrtoaddr ptr [[PDST]] to i32
; CHECK-NEXT:    [[CMP_NOT14:%.*]] = icmp eq i32 [[BLOCKSIZE]], 0
; CHECK-NEXT:    br i1 [[CMP_NOT14]], label %[[WHILE_END:.*]], label %[[WHILE_BODY_PREHEADER:.*]]
; CHECK:       [[WHILE_BODY_PREHEADER]]:
; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 4
; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK:       [[VECTOR_MEMCHECK]]:
; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 [[PDST1]], [[PSRC2]]
; CHECK-NEXT:    [[TMP5:%.*]] = sub i32 [[TMP0]], 1
; CHECK-NEXT:    [[DIFF_CHECK:%.*]] = icmp ult i32 [[TMP5]], 15
; CHECK-NEXT:    br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[N_MOD_VF:%.*]] = and i32 [[BLOCKSIZE]], 3
; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[BLOCKSIZE]], [[N_MOD_VF]]
; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[N_VEC]], 2
; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[TMP1]]
; CHECK-NEXT:    [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[N_VEC]]
; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[TMP1]]
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = shl i32 [[INDEX]], 2
; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i32 [[OFFSET_IDX]]
; CHECK-NEXT:    [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[OFFSET_IDX]]
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[NEXT_GEP]], align 4
; CHECK-NEXT:    [[TMP6:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], zeroinitializer
; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], splat (i32 -2147483648)
; CHECK-NEXT:    [[TMP8:%.*]] = sub nsw <4 x i32> zeroinitializer, [[WIDE_LOAD]]
; CHECK-NEXT:    [[TMP9:%.*]] = select <4 x i1> [[TMP7]], <4 x i32> splat (i32 2147483647), <4 x i32> [[TMP8]]
; CHECK-NEXT:    [[TMP10:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[TMP9]]
; CHECK-NEXT:    store <4 x i32> [[TMP10]], ptr [[NEXT_GEP4]], align 4
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[BLOCKSIZE]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[CMP_N]], label %[[WHILE_END_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; CHECK:       [[SCALAR_PH]]:
; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[PSRC]], %[[WHILE_BODY_PREHEADER]] ], [ [[PSRC]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[BLOCKSIZE]], %[[WHILE_BODY_PREHEADER]] ], [ [[BLOCKSIZE]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    [[BC_RESUME_VAL5:%.*]] = phi ptr [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[PDST]], %[[WHILE_BODY_PREHEADER]] ], [ [[PDST]], %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    br label %[[WHILE_BODY:.*]]
; CHECK:       [[WHILE_BODY]]:
; CHECK-NEXT:    [[PSRC_ADDR_017:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[BLKCNT_016:%.*]] = phi i32 [ [[DEC:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[PDST_ADDR_015:%.*]] = phi ptr [ [[INCDEC_PTR7:%.*]], %[[WHILE_BODY]] ], [ [[BC_RESUME_VAL5]], %[[SCALAR_PH]] ]
; CHECK-NEXT:    [[INCDEC_PTR]] = getelementptr inbounds i32, ptr [[PSRC_ADDR_017]], i32 1
; CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[PSRC_ADDR_017]], align 4
; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[TMP12]], 0
; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[TMP12]], -2147483648
; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[TMP12]]
; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP2]], i32 2147483647, i32 [[SUB]]
; CHECK-NEXT:    [[COND6:%.*]] = select i1 [[CMP1]], i32 [[TMP12]], i32 [[COND]]
; CHECK-NEXT:    [[INCDEC_PTR7]] = getelementptr inbounds i32, ptr [[PDST_ADDR_015]], i32 1
; CHECK-NEXT:    store i32 [[COND6]], ptr [[PDST_ADDR_015]], align 4
; CHECK-NEXT:    [[DEC]] = add i32 [[BLKCNT_016]], -1
; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
; CHECK-NEXT:    br i1 [[CMP_NOT]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK:       [[WHILE_END_LOOPEXIT]]:
; CHECK-NEXT:    br label %[[WHILE_END]]
; CHECK:       [[WHILE_END]]:
; CHECK-NEXT:    ret void
;
entry:
  %cmp.not14 = icmp eq i32 %blockSize, 0
  br i1 %cmp.not14, label %while.end, label %while.body.preheader

while.body.preheader:
  br label %while.body

while.body:
  %pSrc.addr.017 = phi ptr [ %incdec.ptr, %while.body ], [ %pSrc, %while.body.preheader ]
  %blkCnt.016 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
  %pDst.addr.015 = phi ptr [ %incdec.ptr7, %while.body ], [ %pDst, %while.body.preheader ]
  %incdec.ptr = getelementptr inbounds i32, ptr %pSrc.addr.017, i32 1
  %0 = load i32, ptr %pSrc.addr.017, align 4
  %cmp1 = icmp sgt i32 %0, 0
  %cmp2 = icmp eq i32 %0, -2147483648
  %sub = sub nsw i32 0, %0
  %cond = select i1 %cmp2, i32 2147483647, i32 %sub
  %cond6 = select i1 %cmp1, i32 %0, i32 %cond
  %incdec.ptr7 = getelementptr inbounds i32, ptr %pDst.addr.015, i32 1
  store i32 %cond6, ptr %pDst.addr.015, align 4
  %dec = add i32 %blkCnt.016, -1
  %cmp.not = icmp eq i32 %dec, 0
  br i1 %cmp.not, label %while.end.loopexit, label %while.body

while.end.loopexit:
  br label %while.end

while.end:
  ret void
}

attributes #0 = { "target-features"="+mve" }