llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir

# RUN: not llc -mtriple=amdgpu6.00 -run-pass=none -filetype=null %s 2>&1 | FileCheck %s
---
name: empty_frame_offset_reg
machineFunctionInfo:
  frameOffsetReg:  ''
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
body:             |
  bb.0:

    S_ENDPGM
...