llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mattr=addsubiw < %s -mtriple=avr | FileCheck %s

; This verifies that the backend can handle an unaligned atomic load and store.
;
; In the past, an assertion inside the SelectionDAGBuilder would always
; hit an assertion for unaligned loads and stores.

%AtomicI16 = type { %CellI16, [0 x i8] }
%CellI16 = type { i16, [0 x i8] }

define void @foo(ptr %self) {
; CHECK-LABEL: foo:
; CHECK:       ; %bb.0: ; %start
; CHECK-NEXT:    mov r30, r24
; CHECK-NEXT:    mov r31, r25
; CHECK-NEXT:    in r0, 63
; CHECK-NEXT:    cli
; CHECK-NEXT:    ld r24, Z
; CHECK-NEXT:    ldd r25, Z+1
; CHECK-NEXT:    out 63, r0
; CHECK-NEXT:    ldi r24, 5
; CHECK-NEXT:    ldi r25, 0
; CHECK-NEXT:    in r0, 63
; CHECK-NEXT:    cli
; CHECK-NEXT:    std Z+1, r25
; CHECK-NEXT:    st Z, r24
; CHECK-NEXT:    out 63, r0
; CHECK-NEXT:    ret
start:
  %a = getelementptr inbounds %AtomicI16, ptr %self, i16 0, i32 0, i32 0
  load atomic i16, ptr %a seq_cst, align 1
  store atomic i16 5, ptr %a seq_cst, align 1
  ret void
}